MUX/
GAIN
STAGE
VDD
IN1+
IN1-
SGND
OUT+
OUT-
+2.7V to +5.5V
CS
CBST
BOOST
CONVERTER
ALC
SCL/GAIN
SW
PGND
VBST
L1
SHDN
D1
4.7 PH
1 PF
10:
I2C
INTERFACE
IN2+
IN2-
SDA/SEL
0.47 PF
CIN
CIN
CIN
CIN SET
SW/HW
0.47 PF
0.47 PF
0.47 PF
RL
CL
Product
Folder
Sample &
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Technical
Documents
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Software
Support &
Community
LM48560
SNAS513F AUGUST 2011REVISED NOVEMBER 2015
LM48560 Boomer™ Audio Power Amplifier Series High Voltage Class H Ceramic Speaker
Driver With Automatic Level Control
1 Features 3 Description
The LM48560 device is a high voltage, high
1 Class H Topology efficiency, Class H driver for ceramic speakers and
Integrated Boost Converter piezo actuators. The LM48560 device’s Class H
Bridge-Tied Load (BTL) Output architecture offers significant power savings
compared to traditional Class AB amplifiers. The
Selectable Differential Inputs device provides 30 VP-P output drive while consuming
Selectable Control Interfaces just 4 mA of quiescent current from a 3.6 V supply.
(Hardware or Software mode) The LM48560 device features TI’s unique automatic
I2C Programmable ALC level control (ALC) that provides output limiter
Low Supply Current functionality. The LM48560 device features two fully
differential inputs with separate gain settings, and a
Minimum External Components selectable control interface. In software control mode,
Micro-Power Shutdown the gain control and device modes are configured
Available in Space-Saving DSBGA Package through the I2C interface. In hardware control mode,
Key Specifications: the gain and input mux are configured through a pair
of logic inputs.
Output Voltage at VDD = 3.6 V,
RL= 1.5 μF + 10 , THD+N 1% The LM48560 device has a low power shutdown
mode that reduces quiescent current consumption to
30 VP-P (Typical) 0.1 μA. The LM48560 device is available in an ultra-
Quiescent Power Supply Current small 16–bump DSBGA package (1.97 mm × 1.97
at 3.6 V (ALC Enabled) mm).
4 mA (Typical) Device Information(1)
Power Dissipation at 25 VP-P, 1 W (Typical) PART NUMBER PACKAGE BODY SIZE (NOM)
Shutdown Current, 0.1 μA (Typical) LM48560 DSBGA (16) 1.97 mm × 1.97 mm
2 Applications (1) For all available packages, see the orderable addendum at
the end of the data sheet.
Touch Screen Smart Phones
Tablet PCs Typical Application Circuit
Portable Electronic Devices
MP3 Players
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM48560
SNAS513F AUGUST 2011REVISED NOVEMBER 2015
www.ti.com
Table of Contents
8.4 Device Functional Modes........................................ 13
1 Features.................................................................. 18.5 Programming .......................................................... 14
2 Applications ........................................................... 18.6 Register Maps......................................................... 15
3 Description............................................................. 19 Application and Implementation ........................ 17
4 Revision History..................................................... 29.1 Application Information............................................ 17
5 Pin Configuration and Functions......................... 39.2 Typical Application ................................................. 17
6 Specifications......................................................... 410 Power Supply Recommendations ..................... 20
6.1 Absolute Maximum Ratings ...................................... 411 Layout................................................................... 20
6.2 ESD Ratings.............................................................. 411.1 Layout Guidelines ................................................. 20
6.3 Recommended Operating Conditions....................... 411.2 Layout Example .................................................... 20
6.4 Electrical Characteristics VDD = 3.6 V....................... 512 Device and Documentation Support................. 21
6.5 I2C Interface Characteristics..................................... 612.1 Community Resources.......................................... 21
6.6 Typical Characteristics.............................................. 712.2 Trademarks........................................................... 21
7 Parameter Measurement Information ................ 10 12.3 Electrostatic Discharge Caution............................ 21
8 Detailed Description............................................ 11 12.4 Glossary................................................................ 21
8.1 Overview................................................................. 11 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram....................................... 11 Information ........................................................... 21
8.3 Feature Description................................................. 11
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Rev Date Description
1.0 08/16/11 Initial WEB released.
1.01 09/21/11 Input edits under CLASS H OPERATION.
1.02 11/01/11 Edited curves 30150753, 54, 55, 56, and Figure 26 (I2C Read Cycle).
1.03 11/10/11 Edited Figure 26.
1.04 07/25/12 Input texts/limits edits in the EC table.
1.05 08/22/12 Edited Table 1 and Table 2.
E 05/02/2013 Changed layout of National Data Sheet to TI format.
F 10/21/2015 Added ESD Ratings table, Feature Description section, Device Functional Modes,Application
and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section.
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3
2
1
A B C D
4
OUT+
SGND
IN1-
IN1+
OUT-
SHDN
IN2-
IN2+
VBST
SW/HW
SCL/
GAIN
SDA/SEL
SET
VDD
SW
PGND
LM48560
www.ti.com
SNAS513F AUGUST 2011REVISED NOVEMBER 2015
5 Pin Configuration and Functions
YZR Package
16-Pin DSBGA
Top View
Pin Functions
PIN I/O DESCRIPTION
NO. NAME
A1 OUT+ O Amplifier Non-Inverting Output
A2 SGND Amplifier Ground
A3 IN1– I Amplifier Inverting Input 1
A4 IN1+ I Amplifier Non-Inverting Input 1
B1 OUT– O Amplifier Inverting Output
Active Low Shutdown. Connect SHDN to GND to disable device.
B2 SHDN I Connect SHDN to VDD for normal operation
B3 IN2– I Amplifier Inverting Input 2
B4 IN2+ I Amplifier Non-Inverting Input 2
C1 VBST Boost Converter Output
Mode Selection Control:
C2 SW/HW I SW/HW = 0 Hardware Mode
SW/HW = 1 Software Mode
I2C Serial Clock Input (Software Mode)
C3 SCL/GAIN I Gain Select Input (Hardware Mode)
see (Table 5)
I2C Serial Data Input (Software Mode)
C4 SDA/SEL I/O Amplifier Input Select (Hardware Mode)
see (Table 5)
D1 SET ALC Timing Input
D2 VDD Power Supply
D3 SW Boost Converter Switching Node
D4 PGND Boost Converter Ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD Supply voltage(2) 6 V
SW Voltage 25 V
VBST Voltage 21 V
Input voltage –0.3 VDD 0.3 V
Power dissipation(3) Internally limited
TJJunction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are measured with respect to the ground pin, unless otherwise specified.
(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX,θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX –TA) / θJA or the given in Absolute Maximum Ratings, whichever is
lower.
6.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
Charged-device model (CDM), per JEDEC specification JESD22-
V(ESD) Electrostatic discharge ±500 V
C101(2)
Machine Model(3) ±100
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) Machine model, applicable std. JESD22-A115-A.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
TAOperating free-air temperature –40 85 °C
VDD Supply voltage 2.7 5.5 V
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6.4 Electrical Characteristics VDD = 3.6 V
The following specifications apply for RL= 1.5 μF + 10 , CBST = 1 μF, CIN = 0.47 μF, CSET = 100 nF, AV= 24 dB unless
otherwise specified. Limits apply for TA= 25 °C.(1)(2)
PARAMETER TEST CONDITIONS MIN (3) TYP (4) MAX (3) UNIT
VDD Supply voltage 2.7 5.5 V
VIN = 0 V, RL=
IDD Quiescent power supply current ALC Enabled 4 6 mA
ALC Disabled 3.6 mA
PDPower consumption VOUT = 25 VP-P, f = 1 kHz 1 W
Software Mode 2.5 4.4 µA
ISD Shutdown current Hardware Mode 0.1 2 µA
TWU Wake-up time From Shutdown 15 ms
AV= 24 V 10 90 mV
VOS Differential output offset voltage AV= 0 dB (Boost Disabled) 5 20 mV
GAIN = 0 0.5 0 0.5
IN1 GAIN = 1 5.5 6 6.5
Gain (Hardware Mode) dB
GAIN = 0 23.5 24 24.5
IN2 GAIN = 1 29.5 30 30.5
GAIN1 = 0, GAIN0 = 0 –0.5 0 0.5
GAIN1 = 0, GAIN0 = 1 5.5 6 6.5
AVBoost Disabled dB
GAIN1 = 1, GAIN0 = 0 11.5 12 12.5
GAIN1 = 1, GAIN0 = 1 17.5 18 18.5
Gain (software mode) GAIN1 = 0, GAIN0 = 0 20.5 21 21.5
GAIN1 = 0, GAIN0 = 1 23.5 24 24.5
Boost Enabled dB
GAIN1 = 1, GAIN0 = 0 26.5 27 27.5
GAIN1 = 1, GAIN0 = 1 29.5 30 30.5
Gain step size (software mode) 3 dB
RIN 0 dB 46 50 58
Input resistance AVk
30 dB 46 50 58
THD+N = 1%
VOUT Output voltage 200 Hz 25 30 VP-P
f1 kHz 25 30
THD+N Total harmonic distortion + noise VOUT = 18 VP-P, f = 1 kHz 0.08%
VDD = 3.6 V + 200 mVP-P sine, Inputs = AC GND
Power supply rejection ratio
PSRR fRIPPLE = 217 Hz 55 78 dB
(Figure 22)fRIPPLE = 1 kHz 76
VCM = 200 mVP-P sine
Common mode rejection ratio
CMRR fRIPPLE = 217 Hz 68 dB
(Figure 23)fRIPPLE = 1k Hz 78 dB
Boost Disabled, A-weighted 107 dB
SNR Signal-to-noise-ratio Boost Enabled A-weighted 98 dB
A-weighted
εOS Output noise 24 dB 134
AVμVRMS
0 dB (Boost Disabled) 16
(1) All voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) Datasheet min/max specification limits are ensured by design, test, or statistical analysis.
(4) Typical values represent most likely parametric norms at TA= 25 ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
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SDA
SCL SP
START condition STOP condition
LM48560
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Electrical Characteristics VDD = 3.6 V (continued)
The following specifications apply for RL= 1.5 μF + 10 , CBST = 1 μF, CIN = 0.47 μF, CSET = 100 nF, AV= 24 dB unless
otherwise specified. Limits apply for TA= 25 °C.(1)(2)
PARAMETER TEST CONDITIONS MIN (3) TYP (4) MAX (3) UNIT
TAAttack time ATK1:ATK0 = 00, CSET = 100 nF 0.83 ms
TRRelease time RLT1:RLT0 = 00, CSET = 100 nF 0.5 s
Boost converter switching
fSW 2 MHz
frequency
ILIMIT Boost converter current limit 1.5 A
VIH Logic high input threshold SHDN 1.4 V
VIL Logic low input threshold SHDN 0.5 V
IIN Input leakage current SHDN 0.1 0.2 μA
6.5 I2C Interface Characteristics
The following specifications apply for RPU = 1 kto VDD, SW/HW = 1 (Software Mode) unless otherwise specified. Limits
apply for TA= 25 °C. (1)(2)
PARAMETER TEST CONDITIONS MIN (3) TYP (4) MAX (3) UNIT
VIH Logic Input High Threshold SDA, SCL 1.1 V
VIL Logic Input Low Threshold SDA, SCL 0.5 V
SCL Frequency 400 kHz
t1SCL Period 2.5 μs
t2SDA Setup Time 250 ns
t3SDA Stable Time 250 ns
t4Start Condition Time 250 ns
t5Stop Condition Time 250 ns
(1) All voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) Typical values represent most likely parametric norms at TA= 25 ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
(4) Charge device model, applicable std. JESD22-C101-C.
Figure 1. I2C Timing Diagram
Figure 2. Start and Stop Diagram
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20 100 1k 10k 20k
0.001
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
0.002
0.02
0.2
2
0.005
0.05
0.5
5
50 200 2k500 5k
FREQUENCY (Hz)
20 50 100 200 500 1k 20k10k5k2k
THD + N (%)
50
20
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
VOUT = 18 VP-P
VOUT = 30 VP-P
VOUT = 25 VP-P
20 100 1k 10k 20k
0.001
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
0.002
0.02
0.2
2
0.005
0.05
0.5
5
50 200 2k500 5k
FREQUENCY (Hz)
20 50 100 200 500 1k 20k10k5k2k
THD + N (%)
50
20
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
VOUT = 18 VP-P
VOUT = 25 VP-P
VOUT = 30 VP-P
FREQUENCY (Hz)
20 50 100 200 500 1k 20k10k5k2k
THD + N (%)
50
20
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
VOUT = 18 VP-P
VOUT = 30 VP-P
VOUT = 25 VP-P
LM48560
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SNAS513F AUGUST 2011REVISED NOVEMBER 2015
6.6 Typical Characteristics
All typical performance curves are taken with conditions seen in Typical Characteristics, unless otherwise specified.
Figure 3. THD+N vs Frequency Figure 4. THD+N vs Frequency
CL= 0.6 μF, VDD = 3.6 V, Boosted, AV= 24 dB CL= 1 μF, VDD = 3.6 V, Boosted, AV= 24 dB
Figure 6. THD+N vs Frequency
Figure 5. THD+N vs Frequency VDD = 3.6 V, CL= 0.6 μF, VOUT = 5 VP-P
CL= 1.5 μF, VDD = 3.6 V, Boosted, AV= 24 dB Unboosted, AV= 0 dB
Figure 7. THD+N vs Frequency Figure 8. THD+N vs Frequency
VDD = 3.6 V, CL= 1 μF, VOUT = 5 VP-P VDD = 3.6 V, CL= 1.5 μF, VOUT = 5 VP-P
Unboosted , AV= 0 dB Unboosted, AV= 0 dB
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1m 10m 100m 1
OUTPUT VOLTAGE (Vp-p)
2m 5m 20m
50m 24200m
500m
100
THD+N (%)
0.0001
0.001
0.01
0.1
1
0.0002
0.002
0.02
0.2
2
0.0005
0.005
0.05
0.5
5
10
20
50
f = 2 kHz
f = 1 kHz
f = 200 Hz
0.01 0.1 1 10 100
OUTPUT VOLTAGE (Vp-p)
0.001
0.01
0.1
1
10
100
TOTAL HARMONIC DISTORTION + NOISE (%)
f = 200 Hz
f = 1 kHz
f = 2 kHz
f = 5 kHz f = 4 kHz
f = 3 kHz
0.01 0.1 1 10 100
OUTPUT VOLTAGE (Vp-p)
0.001
0.01
0.1
1
10
100
TOTAL HARMONIC DISTORTION + NOISE (%)
f = 200 Hz
f = 1 kHz
f = 2 kHz
f = 5 kHz f = 4 kHz
f = 3 kHz
0.01 0.1 1 10 100
OUTPUT VOLTAGE (Vp-p)
0.001
0.01
0.1
1
10
100
TOTAL HARMONIC DISTORTION + NOISE (%)
f = 200 Hz
f = 1 kHz
f = 2 kHz
f = 5 kHz f = 4 kHz
f = 3 kHz
FREQUENCY (Hz)
0
5
10
15
20
25
30
35
10 100 1000 10000 100000
OUTPUT VOLTAGE (Vp-p)
0
1
2
3
4
5
6
7
8
10 100 1000 10000 100000
FREQUENCY (Hz)
OUTPUT VOLTAGE (Vp-p)
LM48560
SNAS513F AUGUST 2011REVISED NOVEMBER 2015
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Typical Characteristics (continued)
All typical performance curves are taken with conditions seen in Typical Characteristics, unless otherwise specified.
Figure 9. Output Voltage vs Frequency Figure 10. Output Voltage vs Frequency
CL= 1.5 μF, THD+N 1%, Boosted CL= 1.5 μF, THD+N 1%, Unboosted
Figure 11. THD+N vs Output Voltage Figure 12. THD+N vs Output Voltage
CL= 0.6 μF, VDD = 3.6 V, Boosted, AV= 24 dB CL= 1 μF, VDD = 3.6 V, Boosted, AV= 24 dB
Figure 13. THD+N vs Output Voltage Figure 14. THD+N vs Output Voltage
CL= 1.5 μF, VDD = 3.6 V, Boosted, AV= 24 dB CL= 1.5 μF, VDD = 3.6 V, Unboosted, AV= 0 dB
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-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10 100 1000 10000 100000
FREQUENCY (Hz)
CMRR (dB)
0 10 20 30
VOUT (VPP)
0
500
1000
1500
2000
2500
3000
3500
4000
4500
TOTAL POWER CONSUMPTION (mW)
5 15 25 35
4 kHz
2 kHz
1 kHz
200 Hz
0
100
200
300
400
500
600
700
800
900
1000
0 10 20 30
VOUT (VPP)
TOTAL POWER CONSUMPTION (mW)
5 15 25 35
4 kHz
2 kHz
1 kHz
200 Hz
0
500
1000
1500
2000
2500
0 10 20 30
VOUT (VPP)
TOTAL POWER CONSUMPTION (mW)
5 15 25 35
4 kHz
2 kHz
1 kHz
200 Hz
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4
Supply Voltage (V)
Supply Current (mA)
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
12
11.5
11
10.5
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
500m0100m200m300m
400m500m600m 1.1
1
0.9
800m
700m
ALC Off
VOUT = 28VP-P
VOUT = 25VP-P
VOUT = 22VP-P
VOUT = 20VP-P
VOUT = 17VP-P
VOUT = 14VP-P
LM48560
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Typical Characteristics (continued)
All typical performance curves are taken with conditions seen in Typical Characteristics, unless otherwise specified.
Figure 15. Input Voltage vs Output Voltage Figure 16. Supply Current vs Supply Voltage
ALC Enabled, AV= 21 dB, VDD = 3.6 V RL=
Figure 18. Total Power Consumption vs Output Voltage
Figure 17. Total Power Consumption vs Output Voltage VDD = 3.6 V, CL= 1 μF
VDD = 3.6 V, CL= 0.6 μF
Figure 19. Total Power Consumption vs Output Voltage Figure 20. Common Mode Rejection Ratio vs Frequency
VDD = 3.6 V, CL= 1.5 μFVCM= 200 mVP-P, CIN = 10 μF, VDD = 3.6 V, CL= 1.5 μF
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DUT ZL
ANALYZER
200 mVp-p
VDD
IN+
IN-
+
-
VDD
+
-
DUT ZL
ANALYZER
VDD
200 mVp-p
VDD
IN+
IN-
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k
50 100 200 500 1k 2k 5k 10k
PSRR (dB)
FREQUENCY (Hz)
LM48560
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Typical Characteristics (continued)
All typical performance curves are taken with conditions seen in Typical Characteristics, unless otherwise specified.
Figure 21. Power Supply Rejection Ratio vs Frequency
VRIPPLE = 200 mVP-P, VDD = 3.6 V, CL= 1.5 μF
7 Parameter Measurement Information
Figure 22. PSRR Test Circuit
Figure 23. CMRR Test Circuit
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MUX/
GAIN
STAGE
VDD
IN1+
IN1-
SGND
OUT+
OUT-
+2.7V to +5.5V
CS
CBST
BOOST
CONVERTER
ALC
SCL/GAIN
SW
PGND
VBST
L1
SHDN
D1
4.7 PH
1 PF
10:
I2C
INTERFACE
IN2+
IN2-
SDA/SEL
0.47 PF
CIN
CIN
CIN
CIN SET
SW/HW
0.47 PF
0.47 PF
0.47 PF
RL
CL
LM48560
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8 Detailed Description
8.1 Overview
The LM48560 device is a fully differential Class H driver for ceramic speakers and piezo actuators. The
integrated, high efficiency boost converter dynamically adjusts the amplifier’s supply voltage based on the output
signal to maintain sufficient headroom while improving efficiency. The LM48560 device’s Class H architecture
offers significant power savings compared to conventional Class AB drivers. The LM48560 features two fully
differential inputs with separate gain settings, and a selectable control interface. In software control mode, the
gain control and device modes are configured through the I2C interface. In hardware control mode, the gain and
input mux are configured through a pair of logic inputs.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 General Amplifier Function
The LM48560 device is a fully differential, Class H piezo driver for ceramic speakers and haptic actuators. The
integrated, high efficiency boost converter dynamically adjusts the amplifier’s supply voltage based on the output
signal, increasing headroom and improving efficiency compared to a conventional Class AB driver. The fully
differential amplifier takes advantage of the increased headroom and bridge-tied load (BTL) architecture,
delivering significantly more voltage than a single-ended amplifier.
8.3.2 Class H Operation
Class H is a modification of another amplifier class (typically Class B or Class AB) to increase efficiency and
reduce power dissipation. To decrease power dissipation, Class H uses a tracking power supply that monitors
the output signal and adjusts the supply accordingly. When the amplifier output is below 3VP-P, the nominal boost
voltage is 6 V. As the amplifier output increases above 3 VP-P, the boost voltage tracks the amplifier output as
shown in Figure 24. When the amplifier output falls below 3 VP-P, the boost converter returns to its nominal output
voltage. Power dissipation is greatly reduced compared to conventional Class AB drivers.
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(2V/DIV)
VOUT
(2V/DIV)
2 ms/DIV
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Feature Description (continued)
Figure 24. Class H Operation
8.3.3 Differential Amplifier Explanation
The LM48560 device features a fully differential amplifier. A differential amplifier amplifies the difference between
the two input signals. A major benefit of the fully differential amplifier is the improved common mode rejection
ratio (CMRR) over single ended input amplifiers. The increased CMRR of the differential amplifier reduces
sensitivity to ground offset related noise injection, especially important in noisy systems.
8.3.4 Automatic Level Control (ALC)
The ALC is available in software mode only, and only in boosted mode. In hardware mode ALC is always
disabled. The ALC limits the peak output voltage to the programmed value. Consequently, it limits the peak boost
voltage, as this is derived from the output voltage. The ALC is continuous, in that it provides a continuous
adjustment of the voltage gain to limit the output voltage to the programmed value. The available gain adjustment
range is typically 8 dB. When the input amplitude is further increased beyond the ALC attenuation range, the
output will again increase. This is illustrated in the Typical Performance Graphs, as seen on the 14 VPP plot in the
Input voltage vs Output Voltage curve. The attack and decay of the ALC is programmed by software and works
in conjunction with the external capacitor CSET. Typically CSET is 0.1 μF, although it can be changed from 0.1 μF
to 4.7 μF to select other ranges of attack and decay time.
8.3.5 Attack Time
Attack time (tATK) is the time it takes for the gain to be reduced by 6 dB once the audio signal exceeds the ALC
threshold. Fast attack times allow the ALC to react quickly and prevent transients such as symbol crashes from
being distorted. However, fast attack times can lead to volume pumping, where the gain reduction and release
becomes noticeable, as the ALC cycles quickly. Slower attack times cause the ALC to ignore the fast transients,
and instead act upon longer, louder passages. Selecting an attack time that is too slow can lead to increased
distortion in the case of the No Clip function, and possible output overload conditions in the case of the Voltage
limiter. The attack time is set by a combination of the value of CSET and the attack time coefficient as given by
Equation 1:
tATK = 20 kCSET /αATK (1)
Where αATK is the attack time coefficient (Table 1) set by bits B4:B3 in the Voltage Limit Control Register. The
attack time coefficient allows the user to set a nominal attack time. The internal 20 kresistor is subject to
temperature change, and it has tolerance between –11% to +20%.
Table 1. Attack Time Coefficient
B4 B3 αATK
0 0 2.4
0 1 1.7
1 0 1.3
1 1 0.9
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8.3.6 Release Time
Release time (tRL) is the time it takes for the gain to return from 6 dB to its normal level once the audio signal
returns below the ALC threshold. A fast release time allows the ALC to react quickly to transients, preserving the
original dynamics of the audio source. However, similar to a fast attack time, a fast release time contributes to
volume pumping. A slow release time reduces the effect of volume pumping. The release time is set by a
combination of the value of CSET and release time coefficient as given by Equation 2:
tRL = 20 MCSET /αRL (s) (2)
where αRL is the release time coefficient (Table 2) set by bits B6:B5 in the No Clip Control Register. The release
time coefficient allows the user to set a nominal release time. The internal 20 Mis subject to temperature
change, and it has tolerance between -11% to +20%.
Table 2. Release Time Coefficient
B6 B5 αRL
0 0 4
0 1 5.3
1 0 9.5
1 1 11.8
8.3.7 Boost Converter
The LM48560 device features an integrated boost converter with a dynamic output control. The device monitors
the output signal of the amplifier, and adjusts the output voltage of the boost converter to maintain sufficient
headroom while improving efficiency.
8.3.8 Gain Setting
The LM48560 device features four internally configured gain settings 0 db, 6 dB, and 30 dB. The device gain is
selected through a single pin (GAIN). The gain settings are shown in Table 3.
Table 3. Gain Setting
GAIN SETTING GAIN SETTING
GAIN IN1 IN2
0 0 dB 24 dB
1 6 dB 30 dB
8.3.9 Shutdown Function
The LM48560 device features a low current shutdown mode. Set SD = GND to disable the amplifier and boost
converter and reduce supply current to 0.01 µA.
8.4 Device Functional Modes
8.4.1 Software or Hardware Mode
Device operation in hardware or software mode is determined by the state of the SW/HW pin. Connect SW/HW
to ground for hardware mode, and connect to VDD for software mode.
SW/HW SDA/SEL SCL/GAIN MODE
0 IN1, Av = 0
0
(Boost Disabled) 1 IN1, Av = 6
00 IN2, Av = 24
1
(Boost Enabled) 1 IN2, Av = 30
1 SDA SCL I2C Mode
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START MSB DEVICE ADDRESS R/W
LSB ACK
SCL
SDA REGISTER ADDRESS REGISTER DATA
ACK ACK STOP
IN-
IN+
LM48560
SINGLE-ENDED
INPUT
LM48560
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8.4.2 Single-Ended Input Configuration
The LM48560 device is compatible with single-ended sources. When configured for single-ended inputs, input
capacitors must be used to block and DC component at the input of the device. Figure 25 shows the typical
single-ended applications circuit.
Figure 25. Single-Ended Input Configuration
8.5 Programming
8.5.1 Read/Write I2C Compatible Interface
The LM48560 device is controlled through an I2C compatible serial interface that consists of a serial data line
(SDA) and a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open drain). The
LM48560 device and the master can communicate at clock rates up to 400 kHz. Figure 1 shows the I2C interface
timing diagram. Data on the SDA line must be stable during the HIGH period of SCL. The LM48560 device is a
transmit/receive slave-only device, reliant upon the master to generate the SCL signal. Each transmission
sequence is framed by a START condition and a STOP condition Figure 2. Each data word, device address and
data, transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse Figure 26. The
LM48560 device address is 1101111.
8.5.2 Write Sequence
The example write sequence is shown in Figure 26. The START signal, the transition of SDA from HIGH to LOW
while SDA is HIGH, is generated, altering all devices on the bus that a device address is being written to the bus.
The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit (R/W = 0
indicating the master is writing to the LM48560 device). The data is latched in on the rising edge of the clock.
Each address bit must be stable while SDA is HIGH. After the R/W bit is transmitted, the master device releases
SDA, during which time, an acknowledge clock pulse is generated by the slave device. If the LM48560 device
receives the correct address, the device pulls the SDA line low, generating and acknowledge bit (ACK).
Once the master device registers the ACK bit, the 8-bit register address word is sent, MSB first. Each data bit
should be stable while SCL is HIGH. After the 8-bit register address is sent, the LM48560 device sends another
ACK bit. Upon receipt of the acknowledge, the 8-bit register data is sent, MSB first. The register data word is
followed by an ACK, upon receipt of which, the master issues a STOP bit, allowing SDA to go high while SDA is
high.
Figure 26. Example I2C Write Cycle
8.5.3 Read Sequence
The example read sequence is shown in Figure 27. The START signal, the transition of SDA from HIGH to LOW
while SDA is HIGH, is generated, altering all devices on the bus that a device address is being written to the bus.
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ack from slave
ack from slave
w rs r stop
ack from slave ack from masterrepeated start data from slave
start w ack ack rs r ack ack stop
start
SCL
SDA
MSB Device Address
LSB
Device address =
1101111 register address = 0x00h
MSB Register 0x00h LSB MSB Data LSB
Device address =
1101111 register 0x00h data
ack ack ack ack
MSB Device Address
LSB
LM48560
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Programming (continued)
The 7-bit device address is written to the bus, followed by the R/W = 1 (R/W = 1 indicating the master wants to
read data from the LM48560 device). After the R/W bit is transmitted, the master device releases SDA, during
which time, an acknowledge clock pulse is generated by the slave device. If the LM48560 device receives the
correct address, the device pulls the SDA line low, generating and acknowledge bit (ACK). Once the master
device registers the ACK bit, the 8-bit register address word is sent, MSB first, followed by an ACK and selected
register data from the LM48560 device. The register data is sent MSB first. Following the acknowledgment of the
register data word [7:0], the master issues a STOP bit, allowing SDA to go high while SDA is high.
Figure 27. Example I2C Read Cycle
Table 4. Device Address
B7 B6 B5 B4 B3 B2 B1 B0 (R/W)
Device Address 1 1 0 1 1 1 1 0
Table 5. Mode Selection
SW/HW SDA/SEL SCL/GAIN MODE
0 IN1, AV= 0
0
(Boost Disabled) 1 IN1, AV= 6
00 IN2, AV= 24
1
(Boost Enabled) 1 IN2, AV= 30
1 X X I2C Mode
8.6 Register Maps
Table 6. I2C Control Registers
REGISTER Register B7 B6 B5 B4 B3 B2 B1 B0
ADDRESS Name
SHUTDOWN TURN BOOST
0x00h X X X X IN_SEL SHDN
CONTROL _ON _EN
NO CLIP
0x01h X RLT1 RLT0 ATK1 ATK0 PLEV2 PLEV1 PLEV0
CONTROL
0x02h GAIN CONTROL X X X X X X GAIN1 GAIN0
0x03h TEST MODE X X X X X X X X
Table 7. Shutdown Control Register
BIT NAME VALUE DESCRIPTION
B7:B4 UNUSED X Unused, set to 0
0 Normal turn on time, tWU = 15 ms
B3 TURN_ON 1 Fast turn on time, tWU = 5 ms
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Table 7. Shutdown Control Register (continued)
BIT NAME VALUE DESCRIPTION
0 Input 1 selected
B2 IN_SEL 1 Input 2 selected
0 Boost disabled
B1 BOOST_EN 1 Boost enabled
0 Device shutdown
B0 SHDN 1 Device enabled
Table 8. No Clip Control Register
BIT NAME VALUE DESCRIPTION
B7 UNUSED X Unused, set to 0
Sets Release Time based on CSET.
B6 B5 See Release Time section.
0 0 TR= 0.5 s
RLT1 (B6)
B6:B5 RLT0 (B5) 0 1 TR= 0.38 s
1 0 TR= 0.21 s
1 1 TR= 0.17 s
Sets Attack Time based on CSET.
B4 B3 See Attack Time section.
0 0 TA= 0.83 ms
ATK1 (B4)
B4:B3 ATK0 (B3) 0 1 TA= 1.2 ms
1 0 TA= 1.5 ms
1 1 TA= 2.2 ms
B2 B1 B0 Sets output voltage limit level.
0 0 0 Voltage Limit disabled
0 0 1 VTH(VLIM) = 14 VP-P
0 1 0 VTH(VLIM) = 17 VP-P
PLEV2 (B2)
B2:B0 PLEV1 (B1) 0 1 1 VTH(VLIM) = 20 VP-P
PLEV0 (B0) 1 0 0 VTH(VLIM) = 22 VP-P
1 0 1 VTH(VLIM) = 25 VP-P
1 1 0 VTH(VLIM) = 28 VP-P
1 1 1 Voltage Limit disabled
Table 9. Gain Control Register
BIT NAME VALUE DESCRIPTION
B7:B2 UNUSED X Unused, set to 0
Sets amplifier gain.
B1 B0 Boost disabled (BOOST_EN = 0)
0 0 0 dB
GAIN1(B1)
B1:B0 GAIN0 (B0) 0 1 6 dB
1 0 12 dB
1 1 18 dB
Sets amplifier gain.
B1 B0 Boost enabled (BOOST_EN = 1)
0 0 21 dB
GAIN1(B1)
B1:B0 GAIN0 (B0) 0 1 24 dB
1 0 27 dB
1 1 30 dB
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LM48560 device is a high voltage, high efficiency Class H driver for ceramic speakers and piezo actuators.
The integrated, high efficiency boost converter dynamically adjusts the amplifier’s supply voltage based on the
output signal to increase headroom and improve efficiency. The LM48560 device’s Class H architecture offers
significant power savings compared to traditional Class AB amplifiers. The device provides 30Vp-p output drive
while consuming just 4 mA of quiescent current from a 3.6 V supply.
The LM48560 device features two fully differential inputs with separate gain settings, and a selectable control
interface. In software control mode, the gain control and device modes are configured through the I2C interface.
In hardware control mode, the gain and input mux are configured through a pair of logic inputs. The LM48560
device has a low current shutdown mode that disables the amplifier and boost converter and reduces quiescent
current consumption to 0.1 μA.
9.2 Typical Application
Figure 28. Demo Board Schematic
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Typical Application (continued)
9.2.1 Design Requirements
Table 10 shows the design parameters for this design example.
Table 10. Design Parameters
PARAMETERS VALUES
Supply voltage 2.7 V to 5.5 V
Temperature 40 °C to 85 °C
Input voltage –0.3 V to Vdd 0.3 V
9.2.2 Detailed Design Procedure
9.2.2.1 Proper Selection of External Components
9.2.2.1.1 ALC Timing (CSET) Capacitor Selection
The recommended range value of CSET is between 0.01 μF to 1 μF. Lowering the value below 0.01 μF can
increase the attack time but LM48560 device ALC ability to regulate its output can be disrupted and approaches
the hard limiter circuit. This in turn increases the THD+N and audio quality will be severely affected.
9.2.2.1.2 Power Selection of External Components
Proper power supply bypassing is critical for low noise performance and high PSRR. Place the supply bypass
capacitors as close to the device as possible. Place a 1-µF ceramic capacitor from VDD to GND. Additional bulk
capacitance may be added as required.
9.2.2.1.3 Boost Converter Capacitor Selection
The LM48560 device boost converter requires three external capacitors for proper operation: a 1-μF supply
bypass capacitor, and 1-μF + 100-pF output reservoir capacitors. Place the supply bypass capacitor as close to
VDD as possible. Place the reservoir capacitors as close to VBST and VAMP as possible. Low ESR surface-
mount multi-layer ceramic capacitors with X7R or X5R temperature characteristics are recommended. Select
output capacitors with voltage rating of 25 V or higher. Tantalum, OS-CON and aluminum electrolytic capacitors
are not recommended.
9.2.2.1.4 Inductor Selection
The LM48560 device boost converter is designed for use with a 4.7-μH inductor. Choose an inductor with a
saturation current rating greater than the maximum operating peak current of the LM48560 device (> 1A). This
ensures that the inductor does not saturate, preventing excess efficiency loss, over heating and possible damage
to the inductor. Additionally, choose an inductor with the lowest possible DCR (series resistance) to further
minimize efficiency losses.
9.2.2.1.5 Diode Selection
Use a Schottkey diode as shown in Figure 28. A 20-V diode such as the NSR0520V2T1G from On
Semiconductor is recommended. The NSR0520V2T1G is designed to handle a maximum average current of 500
mA.
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9.2.3 Application Curve
Figure 29. Out+, Out– and Vbst Waveforms for a 100 Hz Input Sine Wave
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Use wide traces for power supply
inputs and amplifier outputs
Route digital signal traces far
from analog traces
LM48560
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10 Power Supply Recommendations
The LM48560 device is designed be operate with a power supply between 2.7 V and 5.5 V. Proper power supply
bypassing is critical for low noise performance and high PSRR. Place the supply bypass capacitors as close to
the device as possible. Place a 1-μF ceramic capacitor from VDD to GND. Additional bulk capacitance may be
added as required.
11 Layout
11.1 Layout Guidelines
Minimize trace impedance of the power, ground and all output traces for optimum performance. Voltage loss due
to trace resistance between the LM48560 device and the load results in decreased output power and efficiency.
Trace resistance between the power supply and ground has the same effect as a poorly regulated supply,
increased ripple and reduced peak output power. Use wide traces for power supply inputs and amplifier outputs
to minimize losses due to trace resistance, as well as route heat away from the device. Proper grounding
improves audio performance, minimizes crosstalk between channels and prevents switching noise from
interfering with the audio signal. Use of power and ground planes is recommended.
Place all digital components and route digital signal traces as far as possible from analog components and
traces. Do not run digital and analog traces in parallel on the same PCB layer. If digital and analog signal lines
must cross either over or under each other, ensure that they cross in a perpendicular fashion.
11.2 Layout Example
Figure 30. PCB Layout Example
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12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM48560TL/NOPB ACTIVE DSBGA YZR 16 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 GO5
LM48560TLX/NOPB ACTIVE DSBGA YZR 16 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 GO5
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Jan-2017
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM48560TL/NOPB DSBGA YZR 16 250 178.0 8.4 2.08 2.08 0.76 4.0 8.0 Q1
LM48560TLX/NOPB DSBGA YZR 16 3000 178.0 8.4 2.08 2.08 0.76 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jun-2015
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM48560TL/NOPB DSBGA YZR 16 250 210.0 185.0 35.0
LM48560TLX/NOPB DSBGA YZR 16 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jun-2015
Pack Materials-Page 2
MECHANICAL DATA
YZR0016xxx
www.ti.com
TLA16XXX (Rev C)
0.600±0.075 D
E
A
. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
4215051/A 12/12
D: Max =
E: Max =
1.99 mm, Min =
1.99 mm, Min =
1.93 mm
1.93 mm
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Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
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LM48560TL/NOPB LM48560TLX/NOPB