DS39755C-page 49 © 2009 Microchip Technology Inc.
INDEX
A
A/D ...................................................................................... 25
A/D Converter Interrupt, Configuring .......................... 29
Acquisition Requirements ........................................... 30
ADCON0 Register.......................................................25
ADCON1 Register.......................................................25
ADCON2 Register.......................................................25
ADRESH Register................................................. 25, 28
ADRESL Register .......................................................25
Analog Port Pins, Configuring..................................... 32
Associated Registers ..................................................34
Configuring the Module...............................................29
Conversion Clock (TAD) .............................................. 31
Conversion Status (GO/DONE Bit) .............................28
Conversions ................................................................ 33
Converter Characteristics ........................................... 40
Discharge.................................................................... 33
Operation in Power-Managed Modes ......................... 32
Selecting and Configuring Acquisition Time ............... 31
Special Event Trigger (CCP)....................................... 34
Use of the CCP2 Trigger............................................. 34
Absolute Maximum Ratings ................................................ 37
ADCON0 Register............................................................... 25
GO/DONE Bit..............................................................28
ADCON1 Register............................................................... 25
ADCON2 Register............................................................... 25
ADRESH Register...............................................................25
ADRESL Register ......................................................... 25, 28
Analog-to-Digital Converter. See A/D.
B
Block Diagrams
A/D .............................................................................. 28
Analog Input Model .....................................................29
PIC18F2423/2523 (28-Pin) ......................................... 12
PIC18F4423/4523 (40/44-Pin) .................................... 13
C
Compare (CCP Module)
Special Event Trigger.................................................. 34
Conversion Considerations .................................................46
Customer Change Notification Service ............................... 51
Customer Notification Service.............................................51
Customer Support ............................................................... 51
D
Device Differences..............................................................45
Device Overview ................................................................... 9
Details on Individual Family Members ........................ 10
Features (table)........................................................... 11
New Core Features.......................................................9
Other Special Features ............................................... 10
Documentation
Related Data Sheet....................................................... 9
E
Electrical Characteristics..................................................... 37
Equations
A/D Acquisition Time...................................................30
A/D Minimum Charging Time...................................... 30
Calculating the Minimum Required
Acquisition Time.................................................. 30
Errata .................................................................................... 8
I
Internet Address ................................................................. 51
Interrupt Sources
A/D Conversion Complete .......................................... 29
M
Microchip Internet Web Site................................................ 51
Migration from Baseline to Enhanced Devices ................... 46
Migration from High-End to Enhanced Devices.................. 47
Migration from Mid-Range to Enhanced Devices ............... 47
P
Packaging Information ........................................................ 43
Pin Functions
MCLR/VPP/RE3 .................................................... 14, 18
OSC1/CLKI/RA7 ................................................... 14, 18
OSC2/CLKO/RA6 ................................................. 14, 18
RA0/AN0............................................................... 15, 19
RA1/AN1............................................................... 15, 19
RA2/AN2/VREF-/CVREF......................................... 15, 19
RA3/AN3/VREF+ ................................................... 15, 19
RA4/T0CKI/C1OUT .............................................. 15, 19
RA5/AN4/SS/HLVDIN/C2OUT.............................. 15, 19
RB0/INT0/FLT0/AN12........................................... 16, 20
RB1/INT1/AN10.................................................... 16, 20
RB2/INT2/AN8 ...................................................... 16, 20
RB3/AN9/CCP2 .................................................... 16, 20
RB4/KBI0/AN11.................................................... 16, 20
RB5/KBI1/PGM..................................................... 16, 20
RB6/KBI2/PGC ..................................................... 16, 20
RB7/KBI3/PGD ..................................................... 16, 20
RC0/T1OSO/T13CKI ............................................ 17, 21
RC1/T1OSI/CCP2................................................. 17, 21
RC2/CCP1.................................................................. 17
RC2/CCP1/P1A .......................................................... 21
RC3/SCK/SCL ...................................................... 17, 21
RC4/SDI/SDA ....................................................... 17, 21
RC5/SDO.............................................................. 17, 21
RC6/TX/CK ........................................................... 17, 21
RC7/RX/DT........................................................... 17, 21
RD0/PSP0 .................................................................. 22
RD1/PSP1 .................................................................. 22
RD2/PSP2 .................................................................. 22
RD3/PSP3 .................................................................. 22
RD4/PSP4 .................................................................. 22
RD5/PSP5/P1B .......................................................... 22
RD6/PSP6/P1C .......................................................... 22
RD7/PSP7/P1D .......................................................... 22
RE0/RD/AN5............................................................... 23
RE1/WR/AN6.............................................................. 23
RE2/CS/AN7............................................................... 23
VDD ....................................................................... 17, 23
VSS ....................................................................... 17, 23
Pinout I/O Descriptions
PIC18F2423/2523 ...................................................... 14
PIC18F4423/4523 ...................................................... 18
Power-Managed Modes
and A/D Operation...................................................... 32