Original Creation Date: 10/18/94
Last Update Date: 02/14/95
Last Major Revision Date: 10/18/94
MNDS3884A-X REV 0B0 MILITARY DATA SHEET
BTL HANDSHAKE TRANSCEIVER
General Description
The DS3884A is one in a series of transceivers designed specifically for the
implementation of high performance Futurebus+ and proprietary bus interfaces. The DS3884A
is a BTL 6-bit Handshake Transceiver designed to conform to IEEE 1194.1 (Backplane
Transceiver Logic-BTL) as specified in the IEEE 896.2 Futurebus+ specification.
Utilization of the DS3884A simplifies the implementation of all handshake signals which
require Wired-OR glitch filtering. Three of the six bits have an additional parallel
Wired-OR filtered receive output giving a total of nine receiver outputs.
In Wired-OR applications, the glitch generated as drivers are released from the bus, is
dependent upon the backplane and parasitic wiring components causing the characteristics
of the glitch to vary in pulse width and amplitude. To accommodate this variation the
DS3884A features two pins defined as PS1 and PS2 which allow selection of Four Different
Filter Settings to optimize glitch filtering for a given situation. The REXT pin is issued
in conjunction with the filtering circuitry and requires a 15K Ohm resistor to ground.
The DS3884A driver output configuration is an NPN open collector which allows Wired-OR
connection on the bus. Each driver output incorporates a Schottky diode in series with
its collector to isolate the transistor output capacitance from the bus thus reducing the
bus loading in the inactive state. The driver also has high sink current capability.
Backplane Transceiver Logic (BTL) is a signaling standard that was invented and first
introduced by National Semiconductor, then developed by the IEEE to enhance the
performance of backplane buses. BTL compatible transceivers feature low output capacitance
drivers to minimize bus loading, a 1V nominal signal swing for reduced power consumption
and receivers with precision thresholds for maximum noise immunity. The BTL standard
eliminates settling time delays that severely limit TTL bus performance, and thus provide
significantly higher bus transfer rates. The backplane bus is intended to be operated with
termination resistors (selected to match the bus impedance) connected to 2.1V at both
ends. The low voltage is typically 1V at 25 C, 125 C and 1.1V at -55 C.
Separate ground pins are provided for each BTL output to minimize induced ground noise
during simultaneous switching.
The device's unique drive circuitry meets a maximum slew rate of 0.5V/ns which allows
controlled rise and fall times to reduce noise coupling to adjacent lines.
The transceiver's high impedance control and driver inputs are fully TTL compatible.
The receiver is a high speed comparator that utilizes a bandgap reference for precision
threshold control allowing maximum noise immunity to the BTL 1V signaling level.
Separate QVcc and QGND pins are provided to minimize the effects of high current switching
noise. Output pins FR1-FR3 are the filtered outputs and R1-R6 are unfiltered outputs. All
receiver outputs are fully TTL compatible.
The DS3884A supports live insertion as defined for Futurebus+ through the LI (Live
Insertion) pin. To implement live insertion the LI pin should be connected to the live
insertion power connector. If this function is not supported the LI pin must be tied to
the Vcc pin. The DS3884A also provides power up/down glitch free protection during power
sequencing.
The DS3884A has two types of power connections in addition to the LI pin. They are the
Logic Vcc (Vcc) and the Quiet Vcc (QVcc). There are two Vcc pins on the DS3884A that
provide the supply voltage for the logic and control circuitry. Multiple connections are
provided to reduce the effects of package inductance and thereby minimize switching noise.
As these pins are common to the Vcc bus internal to the device, a voltage difference
should never exist between these pins and the voltage difference between Vcc and QVcc
should never exceed +0.5V because of ESD circuitry. Additionally, the ESD circuitry
between the Vcc pins and all other pins except for BTL I/Os and LI pins requires that any
voltage on these pins should not exceed the voltage on Vcc + 0.5V.
There are three different types of ground pins on the DS3884A. They are the Logic ground
(GND), BTL grounds (B1GND-B6GND) and the Bandgap reference ground (QGND). All of these
ground reference pins are isolated within the chip to minimize the effects of high current
switching transients. For optimum performance the QGND should be returned to the connector
through a quiet channel that does not carry transient switching current. The GND and
B1GND-B6GND should be connected to the nearest backplane ground pin with the shortest
possible path.
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