OPA694
OPA694
OPA694
+5V
402W
75W
75W
VLOAD
VIN
RG-59
75W
402W-5V
OPA694
www.ti.com
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
Wideband, Low-Power, Current Feedback
Operational Amplifier
Check for Samples: OPA694
1FEATURES DESCRIPTION
2• UNITY GAIN STABLE BANDWIDTH: 1.5GHz
• HIGH GAIN OF 2V/V BANDWIDTH: 690MHz The OPA694 is an ultra-wideband, low-power, current
feedback operational amplifier featuring high slew
• LOW SUPPLY CURRENT: 5.8mA rate and low differential gain/phase errors. An
• HIGH SLEW RATE: 1700V/msec improved output stage provides ±80mA output drive
• HIGH FULL-POWER BANDWIDTH: 675MHz with < 1.5V output voltage headroom. Low supply
current with > 500MHz bandwidth meets the
• LOW DIFFERENTIAL GAIN/PHASE: requirements of high-density video routers. Being a
0.03%/0.015° current feedback design, the OPA694 holds its
• Pb-FREE AND GREEN SOT23-5 PACKAGE bandwidth to very high gains—at a gain of 10, the
OPA694 will still provide 200MHz bandwidth.
APPLICATIONS RF applications can use the OPA694 as a low-power
• WIDEBAND VIDEO LINE DRIVER SAW pre-amplifier. Extremely high 3rd-order intercept
• MATRIX SWITCH BUFFER is provided through 70MHz at much lower quiescent
• DIFFERENTIAL RECEIVER power than many typical RF amplifiers.
• ADC DRIVER The OPA694 is available in an industry-standard
• IMPROVED REPLACEMENT FOR OPA658 pinout in both SO-8 and SOT23-5 packages.
OPA694 RELATED PRODUCTS
SINGLES DUALS TRIPLES QUADS FEATURES
—OPA2694 — — Dual Version
Low-Power,
OPA683 OPA2683 — — CFBPlus
Low-Power,
OPA684 OPA2684 OPA3684 OPA4684 CFBPlus
OPA691 OPA2691 OPA3691 — High Output
OPA695 OPA2695 OPA3695 — High Intercept
Gain 2V/V Video Line Driver
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2004–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
1
2
3
4
8
7
6
5
NC
InvertingInput
NoninvertingInput
-VS
NC
+VS
Output
NC
1
2
3
5
4
Output
-VS
NoninvertingInput
+VS
InvertingInput
BIA
1
2
3
5
4
PinOrientation/PackageMarking
OPA694
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
SPECIFIED
PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
OPA694ID Rails, 100
OPA694 SO-8 D -40°C to +85°C OPA694 OPA694IDR Tape and Reel, 2500
OPA694IDBVT Tape and Reel, 250
OPA694 SOT23-5 DBV -40°C to +85°C BIA OPA694IDBVR Tape and Reel, 3000
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see
the TI web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted. OPA694 UNIT
Power Supply ±6.5 VDC
Internal Power Dissipation See Thermal Characteristics
Differential Input Voltage ±1.2 V
Input Voltage Range ±VSV
Storage Temperature Range: D, DBV –65 to +125 °C
Junction Temperature (TJ) +150 °C
Human Body Model (HBM) 1500 V
ESD Ratings: Charge Device Model (CDM) 1000 V
Machine Model (MM) 100 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
D PACKAGE DRB PACKAGE
SO-8 SOT23-5
(TOP VIEW) (TOP VIEW)
2Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA694
OPA694
www.ti.com
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
ELECTRICAL CHARACTERISTICS: VS= ±5V
Boldface limits are tested at +25°C. At RF= 402Ω, RL= 100Ω, and G = +2V/V, unless otherwise noted.
OPA694ID, IDBV
MIN/MAX OVER
TYP TEMPERATURE
0°C to
+70°C(-40°C to MIN/ TEST
PARAMETER TEST CONDITIONS +25°C +25°C(2) 3) +85°C(3) UNIT MAX LEVELS(1)
AC Performance (see Figure 31)
Small-Signal Bandwidth G = +1, VO= 0.5VPP, RF= 430Ω1500 MHz typ C
G = +2, VO= 0.5VPP, RF= 402Ω690 350 340 330 MHz min B
G = +5, VO= 0.5VPP, RF= 318Ω250 200 180 160 MHz min B
G = +10, VO= 0.5VPP, RF= 178Ω200 150 130 120 MHz min B
Bandwidth for 0.1dB Gain Flatness G = +1, VO= 0.5VPP, RF= 430Ω90 MHz typ C
Peaking at a Gain of +1 VO≤0.1VPP, RF= 430Ω2 dB typ C
Large-Signal Bandwidth G = +2, VO= 2VPP 675 MHz typ C
Slew Rate G = +2, 2V Step 1700 1300 1275 1250 V/ms min B
Rise Time and Fall Time G = +2, VO= 0.2V Step 0.8 ns typ C
Settling Time to 0.01% G = +2, VO= 2V Step 20 ns typ C
Settling Time to 0.1% G = +2, VO= 2V Step 13 ns typ C
Harmonic Distortion G = +2, f = 5MHz, VO= 2VPP — — —
xxx2nd-Harmonic RL= 100Ω–68 –63 –62 –61 dBc max B
RL≥500Ω–92 –87 –85 –83 dBc max B
xxx3rd-Harmonic RL= 100Ω–72 –69 –67 –66 dBc max B
RL≥500Ω–93 –88 –86 –84 dBc max B
Input Voltage Noise Density f > 1MHz 2.1 2.4 2.8 3.0 nV/√Hz max B
Inverting Input Current Noise Density f > 1MHz 22 24 26 28 pA/√Hz max B
Noninverting Input Current Noise f > 1MHz 24 26 28 30 pA/√Hz max B
Density
NTSC Differential Gain VO- 1.4VPP, RL= 150Ω0.03 % max C
VO- 1.4VPP, RL= 37.5Ω0.05 % max C
NTSC Differential Phase G = +2, VO- 1.4VPP, RL= 150Ω0.015 ° typ C
VO- 1.4VPP, RL= 37.5Ω0.16 ° typ C
DC PERFORMANCE(4)
Open-Loop Transimpedance VO= 0V, RL= 100Ω145 90 65 60 kΩmin A
Input Offset Voltage VCM = 0V ±0.5 ±3.0 ±3.7 ±4.1 mV max A
Average Input Offset Voltage Drift VCM = 0V 12 15 mV/°C max B
Noninverting Input Bias Current VCM = 0V ±5 ±20 ±26 ±31 mA max A
Average Input Bias Current Drift VCM = 0V ±100 ±150 nA/°C max B
Inverting Input Bias Current VCM = 0V ±2 ±18 ±26 ±38 mA max A
Average Input Bias Current Drift VCM = 0V ±150 ±200 nA/°C max B
INPUT
Common-mode Input Voltage(5) ±2.5 ±2.3 ±2.2 ±2.1 V min A
(CMIR)
Common-Mode Rejection Ratio VCM = 0V 60 55 53 51 dB min A
(CMRR)
Noninverting Input Impedance 280 | | 1.2 kΩ| | pF typ C
Inverting Input Resistance Open-Loop 30 Ωtyp C
(1) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
(2) Junction temperature = ambient for +25°C specifications.
(3) Junction temperature = ambient at low temperature limits; junction temperature = ambient +9°C at high temperature limit for over
temperature specifications.
(4) Current is considered positive out of node. VCM is the input common-mode voltage.
(5) Tested < 3dB below minimum specified CMRR at ±CMIR limits.
Copyright © 2004–2010, Texas Instruments Incorporated 3
Product Folder Link(s): OPA694
OPA694
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
www.ti.com
ELECTRICAL CHARACTERISTICS: VS= ±5V (continued)
Boldface limits are tested at +25°C. At RF= 402Ω, RL= 100Ω, and G = +2V/V, unless otherwise noted.
OPA694ID, IDBV
MIN/MAX OVER
TYP TEMPERATURE
0°C to
+70°C(-40°C to MIN/ TEST
PARAMETER TEST CONDITIONS +25°C +25°C(2) 3) +85°C(3) UNIT MAX LEVELS(1)
OUTPUT
Voltage Output Voltage No Load ±4 ±3.8 ±3.7 ±3.6 V min A
RL= 100Ω±3.4 ±3.1 ±3.1 ±3.0 V min A
Output Current VO= 0V ±80 ±60 ±58 ±50 mA min A
Short-Circuit Output Current VO= 0V ±200 mA min C
Closed-Loop Output Impedance G = +2, f =100kHz 0.02 Ωtyp C
POWER SUPPLY
Specified Operating Voltage ±5 V typ C
Maximum Operating Voltage Range ±6.3 ±6.3 ±6.3 V max A
Minimum Operating Voltage Range ±3.5 ±3.5 ±3.5 V max B
Maximum Quiescent Current VS= ±5V 5.8 6.0 6.2 6.3 mA max A
Minimum Quiescent Current VS= ±5V 5.8 5.6 5.3 5.0 mA min A
Power-Supply Rejection Ratio min
Input-Referred 58 54 52 50 dB A
(PSRR)
THERMAL CHARACTERISTICS
Specification: ID, IDBV -40 to +85 °C typ C
Thermal Resistance, qJA Junction-to-Ambient — — — —
xxxDxxxx x SO-8 125 °C/W typ C
xxxDBV xxx SOT23 150 °C/W typ C
4Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA694
0 200 400 600 800 1000
Frequency(MHz)
NormalizedGain(dB)
VO PP
=0.5V
RW
L=100
G=+2V/V
RW
F=402
SeeFigure31
G=+5V/V
RW
F=318
G=+10V/V
RW
F=178
3
0
3
6
9
12
-
-
-
-
6004000 200 800 1000
Frequency(MHz)
NormalizedGain(dB)
VO PP
=0.5V
RL=100W
SeeFigure32
G= -10V/V
RF=500W
G= -5V/V
RF=318W
G= -1V/V
RF=430W
G= -2V/V
RF=402W
3
0
3
6
9
12
15
18
-
-
-
-
-
-
6004000 200 800 1000
Frequency(MHz)
Gain(dB)
VO PP
=1V
VO PP
=2V
VO PP
=7V VO PP
=4V
SeeFigure31
G=+2V/V
RW
F=402
9
6
3
0
3
6
9
12
-
-
-
-
6004000 200 800 1000
Frequency(MHz)
Gain(dB)
VO PP
=1V
VO PP
=2V
VO PP
=7V
VO PP
=4V
G= 2V/V-
RW
F=402
SeeFigure32
9
6
3
0
3
6
9
12-
-
-
-
OutputVoltage(1V/div)
G=+2V/V
Time(5ns/div)
OutputVoltage(200mV/div)
SeeFigure31
SmallSignal,0.5VPP
RightScale
LargeSignal,5VPP
LeftScale
3
2
1
0
1
2
3-
-
-
0.6
0.4
0.2
0
0.2
0.4
0.6-
-
-
OutputVoltage(1V/div)
G= 2V/V-
Time(5ns/div)
OutputVoltage(200mV/div)
SeeFigure32
SmallSignal,0.5VPP
RightScale
LargeSignal,5VPP
LeftScale
3
2
1
0
1
2
3
-
-
-
0.6
0.4
0.2
0
0.2
0.4
0.6
-
-
-
OPA694
www.ti.com
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
TYPICAL CHARACTERISTICS: VS= ±5V
At RF= 402Ω, RL= 100Ω, and G = +2V/V, unless otherwise noted.
NONINVERTING SMALL−SIGNAL FREQUENCY RESPONSE INVERTING SMALL−SIGNAL FREQUENCY RESPONSE
Figure 1. Figure 2.
NONINVERTING LARGE−SIGNAL FREQUENCY RESPONSE INVERTING LARGE−SIGNAL FREQUENCY RESPONSE
Figure 3. Figure 4.
NONINVERTING PULSE RESPONSE INVERTING PULSE RESPONSE
Figure 5. Figure 6.
Copyright © 2004–2010, Texas Instruments Incorporated 5
Product Folder Link(s): OPA694
3.5 4.0 4.5 5.0 5.5 6.0
SupplyVoltage( V )±S
HarmonicDistortion(dBc)
G=+2V/V
f=5MHz
R =100
LW
V =2V
O PP
3rdHarmonic
2ndHarmonic
SeeFigure31
-
-
-
-
-
60
65
70
75
80
0.1 1 10 20
Frequency(MHz)
HarmonicDistortion(dBc)
G=+2V/V
R =100W
L
V =2V
O PP
3rdHarmonic
2ndHarmonic
SeeFigure31
-
-
-
-
-
-
50
60
70
80
90
100
0.1 1 10
OutputVoltageSwing(VPP)
HarmonicDistortion(dBc)
G=+2V/V
R =100W
L
f=5MHz
3rdHarmonic
2ndHarmonic
SeeFigure31
-
-
-
-
-
65
70
75
80
85
1 10
Gain(V/V)
HarmonicDistortion(dBc)
R =100W
L
f=5MHz
V =2V
O PP
3rdHarmonic
2ndHarmonic
SeeFigure31
-
-
-
-
60
65
70
75
1 10
Gain(|V/V|)
HarmonicDistortion(dBc)
R =100W
L
f=5MHz
V =2V
O PP
3rdHarmonic
2ndHarmonic
SeeFigure32
-
-
-
-
60
65
70
75
OPA694
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
www.ti.com
TYPICAL CHARACTERISTICS: VS= ±5V (continued)
At RF= 402Ω, RL= 100Ω, and G = +2V/V, unless otherwise noted.
HARMONIC DISTORTION vs HARMONIC DISTORTION vs
LOAD RESISTANCE SUPPLY VOLTAGE
Figure 7. Figure 8.
HARMONIC DISTORTION vs HARMONIC DISTORTION vs
FREQUENCY OUTPUT VOLTAGE
Figure 9. Figure 10.
HARMONIC DISTORTION vs HARMONIC DISTORTION vs
NONINVERTING GAIN INVERTING GAIN
Figure 11. Figure 12.
6Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA694
10 100 1k 10k 100k 1M 10M 100M
Frequency(Hz)
NoninvertingCurrentNoise(24pA/ )ÖHz
InvertingCurrentNoise(22pA/ )ÖHz
VoltageNoise(2.1nV/ )ÖHz
1k
100
10
1
VoltageNoise(nV/ )
CurrentNoise(pA/ )
Ö
Ö
Hz
Hz
500 10 20 30 40 60 70 80 90 100
Frequency(MHz)
InterceptPoint(+dBm)
50W
OPA694
50W
50W
PI
PO
402W
402W
55
50
45
40
35
30
25
20
10 100
CapacitiveLoad(pF)
R ( )W
S
0dBPeakingTargeted
60
50
40
30
20
10
0
1M 1G100M10M
Frequency(Hz)
NormalizedGain(dB)
RS
50W
OPA694
CL
VI
VO
402W
402W1kW(1)
NOTE:(1)1k loadisoptionalW
C =100pF
L
C =47pF
L
C =10pF
L
C =22pF
L
3
0
3
6
9
12
15
18
-
-
-
-
-
-
100 1G100M1M10k1k 100k 10M
Frequency(Hz)
Open-LoopZ Gain(dB )W
OL
Open-LoopZ Phase( )°
OL
<ZOL
120
110
100
90
80
70
60
50
40
30
0
30
60
90
120
150
180
210-
-
-
-
-
-
-
20log|Z |
OL
100 100M1M10k1k 100k 10M
Frequency(Hz)
70
60
50
40
30
20
10
0
CMRR(dB)
PSRR(dB)
CMRR
+PSRR
-PSRR
OPA694
www.ti.com
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
TYPICAL CHARACTERISTICS: VS= ±5V (continued)
At RF= 402Ω, RL= 100Ω, and G = +2V/V, unless otherwise noted. TWO−TONE, THIRD−ORDER
INPUT VOLTAGE AND CURRENT NOISE INTERMODULATION INTERCEPT
Figure 13. Figure 14.
RECOMMENDED RSvs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD
Figure 15. Figure 16.
COMMON−MODE REJECTION RATIO AND
POWER−SUPPLY REJECTION RATIO vs FREQUENCY OPEN−LOOP ZOL GAIN AND PHASE
Figure 17. Figure 18.
Copyright © 2004–2010, Texas Instruments Incorporated 7
Product Folder Link(s): OPA694
1 432
VideoLoads
DifferentialGain(%)
DifferentialPhase( )°
dPPositiveVideo
dGNegativeVideo
dPNegativeVideo
dGPositiveVideo
0.08
0.06
0.04
0.02
0
0.16
0.12
0.08
0.04
0
-50 -25 +125+100+75+50+250
AmbientTemperature( C)°
InputOffsetVoltage(mV)
InputBiasandOffsetCurrent( A)m
InputOffsetVoltage(V )
OS
LeftScale
NoninvertingInputBiasCurrent(I )
BN
RightScale
InvertingInputBiasCurrent(I )
BI
RightScale
1.0
0.5
0
0.5
1.0
-
-
10
5
0
5
10
-
-
-200 -100 2000 100
OutputCurrent(mA)
OutputVoltage(V)
RW
L=100
RW
L=25
RW
L=50
1WInternalPowerLimit
1WInternalPowerLimit
Output
Current
Limit
Output
Current
Limit
4
3
2
1
0
1
2
3
4-
-
-
-
-50 -25 +125+100+75+50+250
AmbientTemperature( C)°
OutputCurrent(mA)
SupplyCurrent(mA)
LeftScale
SourcingOutputCurrent
SinkingOutputCurrent
SupplyCurrent
RightScale
LeftScale
100
90
80
70
60
50
40
10
9
8
7
6
5
4
Time(10ns/div)
OutputVoltage(V)
R =100W
L
G= 1V/V-
Input
RightScale
SeeFigure32
Output
LeftScale
InputVoltage(V)
4
2
0
2
4
-
-
4
2
0
2
4
-
-
Time(10ns/div)
OutputVoltage(V)
InputVoltage(V)
R =100W
L
G=+2V/V
Input
RightScale
SeeFigure31
Output
LeftScale
8
4
0
4
8
-
-
4
2
0
2
4
-
-
OPA694
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
www.ti.com
TYPICAL CHARACTERISTICS: VS= ±5V (continued)
At RF= 402Ω, RL= 100Ω, and G = +2V/V, unless otherwise noted.
VIDEO DIFFERENTIAL GAIN/DIFFERENTIAL PHASE
(No Pulldown) TYPICAL DC DRIFT OVER TEMPERATURE
Figure 19. Figure 20.
OUTPUT VOLTAGE AND CURRENT LIMITATIONS SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
Figure 21. Figure 22.
NONINVERTING OVERDRIVE RECOVERY INVERTING OVERDRIVE RECOVERY
Figure 23. Figure 24.
8Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA694
2500 50 100 150 200 300 350 400 450 500
Frequency(MHz)
NormalizedGain(dB)
VO PP
=2V
RW
L=400
G =1
D
RW
F=430
G =2
D
RW
F=402
G =5
D
RW
F=330
G =10D
RW
F=250
3
0
3
6
9
12-
-
-
-
RG
RG
RF
+5V
RL
400W
VO
VI
= =
VO
VI
RTRF
OPA694
OPA694
-5V
RFGD
RG
10 100 1000
Resistance( )W
HarmonicDistortion(dBc)
VO PP
=4V
f=5MHz
GD=2 3rdHarmonic
2ndHarmonic
-60
65
70
75
80
85
90
-
-
-
-
-
-
2500 50 100 150 200 300 350 400 450 500
Frequency(MHz)
Gain(dB)
GD=2
RW
L=400
VO PP
=12V
VO PP
=5V
VO PP
=16V
VO PP
=8V
9
6
3
0
3
6
-
-
1 10 20
Frequency(MHz)
HarmonicDistortion(dBc)
G =2
D
VO PP
=4V
RW
L=400
3rdHarmonic
2ndHarmonic
-
-
-
-
-
-
55
65
75
85
95
105
0.1 100101
OutputVoltageSwing(V )
PP
HarmonicDistortion(dBc)
G =2
D
f=5MHz
RW
L=400
3rdHarmonic
2ndHarmonic
-
-
-
-
-
-
-
65
70
75
80
85
90
95
OPA694
www.ti.com
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
TYPICAL CHARACTERISTICS: VS= ±5V (continued)
At RF= 402Ω, RL= 100Ω, and G = +2V/V, unless otherwise noted.
DIFFERENTIAL PERFORMANCE TEST CIRCUIT DIFFERENTIAL SMALL−SIGNAL FREQUENCY RESPONSE
Figure 25. Figure 26.
DIFFERENTIAL LARGE−SIGNAL FREQUENCY RESPONSE DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
Figure 27. Figure 28.
DIFFERENTIAL DISTORTION vs FREQUENCY DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
Figure 29. Figure 30.
Copyright © 2004–2010, Texas Instruments Incorporated 9
Product Folder Link(s): OPA694
OPA694
+5V
+VS
-VS
-5V
50 LoadW
50W
20W
RT
66.5W
RG
200W
+
6.8 Fm0.1 Fm
+
6.8 Fm0.1 Fm
Optional
0.01 Fm
VI
50 SourceWRF
402W
VO
OPA694
+5V
+
-5V
-VS
+VS
50 LoadW
50W
50WVO
VI
50 SourceW
RG
402W
RF
402W
+
6.8 Fm
0.1 Fm6.8 Fm
0.1 Fm
0.1 Fm
OPA694
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
www.ti.com
APPLICATION INFORMATION
rate for inverting operation is higher and the distortion
performance is slightly improved. An additional input
WIDEBAND CURRENT FEEDBACK resistor, RT, is included in Figure 32 to set the input
OPERATION impedance equal to 50Ω. The parallel combination of
The OPA694 provides exceptional AC performance RTand RGsets the input impedance. Both the
for a wideband, low-power, current-feedback noninverting and inverting applications of Figure 31
operational amplifier. Requiring only 5.8mA quiescent and Figure 32 will benefit from optimizing the
current, the OPA694 offers a 690MHz bandwidth at a feedback resistor (RF) value for bandwidth (see the
gain of +2, along with a 1700V/ms slew rate. An discussion in the Setting Resistor Values to Optimize
improved output stage provides ±80mA output drive, Bandwidth section). The typical design sequence is to
along with < 1.5V output voltage headroom. This select the RFvalue for best bandwidth, set RGfor the
combination of low power and high bandwidth can gain, then set RTfor the desired input impedance. As
benefit high-resolution video applications. the gain increases for the inverting configuration, a
point will be reached where RGwill equal 50Ω, where
Figure 31 shows the DC-coupled, gain of +2, dual RTis removed and the input match is set by RGonly.
power-supply circuit configuration used as the basis With RGfixed to achieve an input match to 50Ω, RFis
of the ±5V Electrical Characteristics table and Typical simply increased, to increase gain. This will, however,
Characteristic curves. For test purposes, the input quickly reduce the achievable bandwidth, as shown
impedance is set to 50Ωwith a resistor to ground and by the inverting gain of –10 frequency response in the
the output impedance is set to 50Ωwith a series Typical Characteristic curves. For gains > 10V/V
output resistor. Voltage swings reported in the (14dB at the matched load), noninverting operation is
Electrical Characteristics are taken directly at the recommended to maintain broader bandwidth.
input and output pins, while load powers (dBm) are
defined at a matched 50Ωload. For the circuit of
Figure 31, the total effective load will be 100Ω|| 804Ω
= 89Ω. One optional component is included in
Figure 31. In addition to the usual power-supply
decoupling capacitors to ground, a 0.1mF capacitor is
included between the two power-supply pins. In
practical printed circuit board (PCB) layouts, this
optional added capacitor will typically improve the
2nd-harmonic distortion performance by 3dB to 6dB.
Figure 32. DC-Coupled, G = −2V/V,
Bipolar-Supply Specification and Test Circuit
ADC DRIVER
Figure 31. DC-Coupled, G = +2, Bipolar-Supply Most modern, high-performance analog-to-digital
Specification and Test Circuit converters (ADCs) require a low-noise, low-distortion
driver. The OPA694 combines low-voltage noise
(2.1nV/√Hz) with low harmonic distortion. See
Figure 32 shows the DC-coupled, gain of −2V/V, dual Figure 33 for an example of a wideband, AC-coupled,
power-supply circuit used as the basis of the inverting 12-bit ADC driver.
Typical Characteristic curves. Inverting operation
offers several performance benefits. Since there is no
common-mode signal across the input stage, the slew
10 Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA694
Single-to-Differential
Gainof10
Power-supplydecouplingnotshown.
OPA694
L
+5V
L
R1
R1
R2
R2
C
V-
V+
12-Bit
ADC
OPA694
500W
-5V
0.1 Fm
25W
100W
100W500W
C1
C1
VI
50W
1:2
25W
VCM
100W
50WOPA694
+5V
-5V
100MHz, 1dBCompression=15dBm-
50W
50W
50W
50W
50W
RG-58
50W
30W
V1
V2
V3
V4
V5
V V V +V +V +V
O 12345
= ( + )-
OPA694
www.ti.com
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
Two OPA694s are used in the circuit of Figure 33 to have been adjusted to maintain both maximum
form a differential driver for a 12-bit ADC. The two bandwidth and input impedance matching. If each RF
OPA694s offer > 250MHz bandwidth at a differential signal is assumed to be driven from a 50Ωsource,
gain of 5V/V, with a 2VPP output swing. A 2nd-order the NG for this circuit will be [1 + 100Ω/(100Ω/5)] = 6.
RLC filter is used in order to limit the noise from the The total feedback impedance (from VOto the
amplifier and provide some attenuation for inverting error current) is the sum of RF+ (RI• NG),
higher-frequency harmonic distortion. where RIis the impedance looking into the inverting
input from the summing junction (see the Setting
Resistor Values to Optimize Performance section).
WIDEBAND INVERTING SUMMING Using 100Ωfeedback (to get a signal gain of –2 from
AMPLIFIER each input to the output pin) requires an additional
Since the signal bandwidth for a current-feedback op 30Ωin series with the inverting input to increase the
amp can be controlled independently of the noise feedback impedance. With this resistor added to the
gain (NG, which is normally the same as the typical internal RI= 30Ω, the total feedback
noninverting signal gain), wideband inverting impedance is 100Ω+ (60Ω• 6) = 460Ω, which is
summing stages may be implemented using the equal to the required value to get a maximum
OPA694. The circuit in Figure 34 shows an example bandwidth flat frequency response for NG = 6.
inverting summing amplifier, where the resistor values
Figure 33. Wideband, AC-Coupled, Low-Power ADC Driver
Figure 34. 200MHz RF Summing Amplifier
Copyright © 2004–2010, Texas Instruments Incorporated 11
Product Folder Link(s): OPA694
OPA694
+5V
RO
50W
VO
RF
430W
RG
430W
RM
50W-5V
VI
OPA694
SAW
Filter
+12V
Matching
Network
=12dB (SAWLoss)-
50W
Source 50W
50W
PO
PO
PI
PI
400W
50W
0.1 Fm1000pF
1000pF
5kW
5kW
3
0
-3
-6
-9
-12
NormalizedGain(dB)
10M 100M 3G1G
Frequency(Hz)
G=+1,Figure1
G=+1,Figure6
OPA694
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
www.ti.com
SAW FILTER BUFFER small-signal frequency response for the unity gain
buffer of Figure 31 compared to the improved
One common requirement in an IF strip is to buffer approach shown in Figure 36. Either approach gives
the output of a mixer with enough gain to recover the a low-power unity-gain buffer with > 1.56GHz
insertion loss of a narrowband SAW filter. Figure 35 bandwidth.
shows one possible configuration driving a SAW filter.
The Two-Tone, Third-Order Intermodulation Intercept
plot (Figure 14) is shown in the Typical
Characteristics curves. Operating in the inverting
mode at a voltage gain of –8V/V, this circuit provides
a 50Ωinput match using the gain set resistor, has the
feedback optimized for maximum bandwidth (250MHz
in this case), and drives through a 50Ωoutput resistor
into the matching network at the input of the SAW
filter. If the SAW filter gives a 12dB insertion loss, a
net gain of 0dB to the 50Ωload at the output of the
SAW (which could be the input impedance of the next
IF amplifier or mixer) will be delivered in the
passband of the SAW filter. Using the OPA694 in this Figure 36. Improve Unity Gain Buffer
application will isolate the first mixer from the
impedance of the SAW filter and provide very low
two-tone, 3rd-order spurious levels in the SAW filter
bandwidth.
Figure 35. IF Amplifier Driving SAW Filter
Figure 37. Gain of +1 Frequency Response
WIDEBAND UNITY GAIN BUFFER WITH
IMPROVED FLATNESS DESIGN-IN TOOLS
The unity gain buffer configuration of Figure 31
shows a peaking in the frequency response DEMONSTRATION FIXTURES
exceeding 2dB. This gives the slight amount of
overshoot and ringing apparent in the gain of +1V/V Two printed circuit boards (PCBs) are available to
pulse response curves. A similar circuit that holds a assist in the initial evaluation of circuit performance
flatter frequency response, giving improved pulse using the OPA694 in its two package options. Both of
fidelity, is shown in Figure 36.these are offered free of charge as unpopulated
PCBs, delivered with a user’s guide. The summary
This circuit removes the peaking by bootstrapping out information for these fixtures is shown in Table 1.
any parasitic effects on RG. The input impedance is
still set by RMas the apparent impedance looking into Table 1. Demonstration Fixtures by Package
RGis very high. RMmay be increased to show a
higher input impedance, but larger values will start to ORDERING LITERATURE
impact DC output offset voltage. This circuit creates PRODUCT PACKAGE NUMBER NUMBER
an additional input offset voltage as the difference in DEM-OPA-
OPA694ID SO-8 SBOU026
the two input bias currents times the impedance to SO-1B
ground at VI.Figure 37 shows a comparison of DEM-OPA-
OPA694IDBV SOT23-5 SBOU027
SOT-1B
12 Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA694
= =
V
V
O
I
a1+ R
R
F
G
(
(
R +R
F I
Z(s)
R
R
F
G
(
(
1+
1+
aNG
R +R
FI·NG
Z(s)
NG=1+ R
R
F
G
(
(
Z
R +R NG
(s)
F I
·=LoopGain
RF
VO
RG
RIZ i
(S) ERR
iERR
a
VI
OPA694
www.ti.com
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
The demonstration fixtures can be requested at the The key elements of this current-feedback op amp
Texas Instruments web site (www.ti.com) through the model are:
OPA694 product folder.a→Buffer gain from the noninverting input to the
inverting input
MACROMODELS AND APPLICATIONS SUPPORT RI→Buffer output impedance
Computer simulation of circuit performance using iERR →Feedback error current signal
SPICE is often useful when analyzing the Z(s) →Frequency-dependent, open-loop
performance of analog circuits and systems. This is transimpedance gain from iERR to VO
particularly true for video and RF amplifier circuits The buffer gain is typically very close to 1.00 and is
where parasitic capacitance and inductance can have normally neglected from signal gain considerations. It
a major effect on circuit performance. A SPICE model will, however, set the CMRR for a single op amp
for the OPA694 is available through the TI web site differential amplifier configuration.
(www.ti.com). These models do a good job of
predicting small-signal AC and transient performance For a buffer gain a< 1.0, the CMRR = –20 × log (1–
under a wide variety of operating conditions. They do a) dB.
not do as well in predicting the harmonic distortion or RI, the buffer output impedance, is a critical portion of
dG/dfcharacteristics. These models do not attempt the bandwidth control equation. RIfor the OPA694 is
to distinguish between package types in their typically about 30Ω.
small-signal AC performance. A current-feedback op amp senses an error current in
OPERATING SUGGESTIONS the inverting node (as opposed to a differential input
error voltage for a voltage-feedback op amp) and
space passes this on to the output through an internal
frequency dependent transimpedance gain. The
SETTING RESISTOR VALUES TO OPTIMIZE Typical Characteristics show this open-loop
BANDWIDTH transimpedance response. This is analogous to the
A current-feedback op amp like the OPA694 can hold open-loop voltage gain curve for a voltage-feedback
an almost constant bandwidth over signal gain op amp. Developing the transfer function for the
settings with the proper adjustment of the external circuit of Figure 38 gives Equation 1:
resistor values. This is shown in the Typical
Characteristic curves; the small-signal bandwidth
decreases only slightly with increasing gain. Those
curves also show that the feedback resistor has been
changed for each gain setting. The resistor values on
the inverting side of the circuit for a current-feedback (1)
op amp can be treated as frequency response
compensation elements while their ratios set the where:
signal gain. Figure 38 shows the small-signal
frequency response analysis circuit for the OPA694.
This is written in a loop-gain analysis format, where
the errors arising from a noninfinite open-loop gain
are shown in the denominator. If Z(s) were infinite
over all frequencies, the denominator of Equation 1
would reduce to 1 and the ideal desired signal gain
shown in the numerator would be achieved. The
fraction in the denominator of Equation 1 determines
the frequency response. Equation 2 shows this as the
loop-gain equation:
(2)
If 20 × log(RF+ NG × RI) were drawn on top of the
open-loop transimpedance plot, the difference
Figure 38. Recommended Feedback Resistor between the two would be the loop gain at a given
Versus Noise Gain frequency. Eventually, Z(s) rolls off to equal the
denominator of Equation 2, at which point the loop
Copyright © 2004–2010, Texas Instruments Incorporated 13
Product Folder Link(s): OPA694
R =462 NGW -
F I
·R
450
400
350
300
250
200
150
NoiseGain
0 2010 155
FeedbackResistor( )W
OPA694
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
www.ti.com
gain reduces to 1 (and the curves intersect). This bandwidth. Inserting a series resistor between the
point of equality is where the amplifier closed-loop inverting input and the summing junction will increase
frequency response given by Equation 1 starts to roll the feedback impedance (denominator of Equation 1),
off, and is exactly analogous to the frequency at decreasing the bandwidth. This approach to
which the noise gain equals the open-loop voltage bandwidth control is used for the inverting summing
gain for a voltage-feedback op amp. The difference circuit on the front page. The internal buffer output
here is that the total impedance in the denominator of impedance for the OPA694 is slightly influenced by
Equation 2 may be controlled somewhat separately the source impedance looking out of the noninverting
from the desired signal gain (or NG). input terminal. High source resistors will have the
effect of increasing RI, decreasing the bandwidth.
The OPA694 is internally compensated to give a
maximally flat frequency response for RF= 402Ωat OUTPUT CURRENT AND VOLTAGE
NG = 2 on ±5V supplies. Evaluating the denominator
of Equation 2 (which is the feedback transimpedance) The OPA694 provides output voltage and current
gives an optimal target of 462Ω. As the signal gain capabilities that are not usually found in wideband
changes, the contribution of the NG × RIterm in the amplifiers. Under no-load conditions at +25°C, the
feedback transimpedance will change, but the total output voltage typically swings closer than 1.2V to
can be held constant by adjusting RF.Equation 3 either supply rail; the +25°C swing limit is within 1.2V
gives an approximate equation for optimum RFover of either rail. Into a 15Ωload (the minimum tested
signal gain: load), it is tested to deliver more than ±60mA.
(3) The specifications described above, though familiar in
the industry, consider voltage and current limits
As the desired signal gain increases, this equation separately. In many applications, it is the (voltage ×
will eventually predict a negative RF. A somewhat current), or V-I product, which is more relevant to
subjective limit to this adjustment can also be set by circuit operation. Refer to the Output Voltage and
holding RGto a minimum value of 20Ω. Lower values Current Limitations plot (Figure 21) in the Typical
will load both the buffer stage at the input and the Characteristics. The X and Y axes of this graph show
output stage, if RFgets too low, actually decreasing the zero-voltage output current limit and the
the bandwidth. Figure 39 shows the recommended zero-current output voltage limit, respectively. The
RFversus NG for ±5V operation. The values for RFfour quadrants give a more detailed view of the
versus gain shown here are approximately equal to OPA694 output drive capabilities, noting that the
the values used to generate the Typical graph is bounded by a Safe Operating Area of 1W
Characteristics. They differ in that the optimized maximum internal power dissipation. Superimposing
values used in the Typical Characteristics are also resistor load lines onto the plot shows that the
correcting for board parasitics not considered in the OPA694 can drive ±2.5V into 25Ωor ±3.5V into 50Ω
simplified analysis leading to Equation 2. The values without exceeding the output capabilities or the 1W
shown in Figure 39 give a good starting point for dissipation limit. A 100Ωload line (the standard test
design where bandwidth optimization is desired. circuit load) shows the full ±3.4V output swing
capability, as shown in the Electrical Characteristics.
The minimum specified output voltage and current
over-temperature are set by worst-case simulations at
the cold temperature extreme. Only at cold startup
will the output current and voltage decrease to the
numbers shown in the Electrical Characteristic tables.
As the output transistors deliver power, the junction
temperatures will increase, decreasing both VBE
(increasing the available output voltage swing) and
increasing the current gains (increasing the available
output current). In steady-state operation, the
available output voltage and current will always be
greater than that shown in the over-temperature
specifications, since the output stage junction
temperatures will be higher than the minimum
specified operating ambient.
Figure 39. Feedback Resistor vs Noise Gain
The total impedance going into the inverting input
may be used to adjust the closed-loop signal
14 Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA694
4kT
RG
RG
RF
RS
OPA694
IBI
EO
IBN
4kT=1.6 10 J´-20
at290K
ERS
ENI
4kTRF
Ö
4kTRS
Ö
OPA694
www.ti.com
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
DRIVING CAPACITIVE LOADS a little less than the expected 2x rate, while the
3rd-harmonic increases at a little less than the
One of the most demanding and yet very common expected 3x rate. Where the test power doubles, the
load conditions for an op amp is capacitive loading. 2nd-harmonic increases by less than the expected
Often, the capacitive load is the input of an 6dB, while the 3rd-harmonic increases by less than
ADC—including additional external capacitance that the expected 12dB. This also shows up in the
may be recommended to improve ADC linearity. A two-tone, third-order intermodulation spurious (IM3)
high-speed, high open-loop gain amplifier like the response curves. The 3rd-order spurious levels are
OPA694 can be very susceptible to decreased extremely low at low output power levels. The output
stability and closed-loop response peaking when a stage continues to hold them low even as the
capacitive load is placed directly on the output pin. fundamental power reaches very high levels. As the
When the amplifier open−loop output resistance is Typical Characteristics show, the spurious
considered, this capacitive load introduces an intermodulation powers do not increase as predicted
additional pole in the signal path that can decrease by a traditional intercept model. As the fundamental
the phase margin. Several external solutions to this power level increases, the dynamic range does not
problem have been suggested. When the primary decrease significantly.
considerations are frequency response flatness,
pulse response fidelity, and/or distortion, the simplest NOISE PERFORMANCE
and most effective solution is to isolate the capacitive
load from the feedback loop by inserting a series Wideband, current-feedback op amps generally have
isolation resistor between the amplifier output and the a higher output noise than comparable
capacitive load. This does not eliminate the pole from voltage-feedback op amps. The OPA694 offers an
the loop response, but rather shifts it and adds a zero excellent balance between voltage and current noise
at a higher frequency. The additional zero acts to terms to achieve low output noise. The inverting
cancel the phase lag from the capacitive load pole, current noise (24pA/√Hz) is significantly lower than
thus increasing the phase margin and improving earlier solutions, while the input voltage noise
stability. (2.1nV/√Hz) is lower than most unity-gain stable,
wideband, voltage-feedback op amps. This low input
The Typical Characteristics show the recommended voltage noise was achieved at the price of higher
RSvs Capacitive Load (Figure 15) and the resulting noninverting input current noise (22pA/√Hz). As long
frequency response at the load. Parasitic capacitive as the AC source impedance looking out of the
loads greater than 2pF can begin to degrade the noninverting node is less than 100Ω, this current
performance of the OPA694. Long PCB traces, noise will not contribute significantly to the total
unmatched cables, and connections to multiple output noise. The op amp input voltage noise and the
devices can easily cause this value to be exceeded. two input current noise terms combine to give low
Always consider this effect carefully, and add the output noise under a wide variety of operating
recommended series resistor as close as possible to conditions. Figure 40 shows the op amp noise
the OPA694 output pin (see the Board Layout analysis model with all the noise terms included. In
Guidelines section). this model, all noise terms are taken to be noise
voltage or current density terms in either nV/√Hz or
DISTORTION PERFORMANCE pA/√Hz.
The OPA694 provides good distortion performance
into a 100Ωload on ±5V supplies. Generally, until the
fundamental signal reaches very high frequency or
power levels, the 2nd-harmonic will dominate the
distortion with a negligible 3rd-harmonic component.
Focusing then on the 2nd-harmonic, increasing the
load impedance improves distortion directly.
Remember that the total load includes the feedback
network—in the noninverting configuration (see
Figure 31), this is the sum of RF+ RG, while in the
inverting configuration it is just RF. Also, providing an
additional supply decoupling capacitor (0.1mF)
between the supply pins (for bipolar operation)
improves the 2nd-order distortion slightly (3dB to
6dB).
In most op amps, increasing the output voltage swing Figure 40. Op Amp Noise Analysis Model
increases harmonic distortion directly. The Typical
Characteristics show the 2nd-harmonic increasing at
Copyright © 2004–2010, Texas Instruments Incorporated 15
Product Folder Link(s): OPA694
E =E +(I R ) +4kTR NG +(I R ) +4kTR NG
O NI BN S S BI F F
2 2 2 2
(
(
E =E +(I R ) +4kTR +
N NI BN S S
2 2 4kTR
NG
F
(
(
I R
BI F
NG
2
+
OPA694
180W
2.86kW
20W
+5V
-5V
VO
Power-supply
decouplingnotshown.
OPA237
-5V
+5V
VI
18kW
2kW
1.8kW
OPA694
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
www.ti.com
The total output spot noise voltage can be computed xx = ±(2 × 3mV) ± (20mA × 25Ω× 2) ± (402Ω× 18mA)
as the square root of the sum of all squared output xx = ±6mV + 1mV ±7.24mV = ±14.24mV
noise voltage contributors. Equation 4 shows the
general form for the output noise voltage using the A fine-scale, output offset null, or DC operating point
terms shown in Figure 40.adjustment, is sometimes required. Numerous
techniques are available for introducing DC offset
control into an op amp circuit. Most simple
adjustment techniques do not correct for temperature
(4) drift. It is possible to combine a lower speed,
precision op amp with the OPA694 to get the DC
Dividing this expression by the noise gain [NG = (1 + accuracy of the precision op amp along with the
RF/RG)] will give the equivalent input-referred spot signal bandwidth of the OPA694. Figure 41 shows a
noise voltage at the noninverting input, as shown in noninverting G = +10 circuit that holds an output
Equation 5.offset voltage less than ±7.5mV over-temperature
with > 150MHz signal bandwidth.
(5)
Evaluating these two equations for the OPA694
circuit and component values (see Figure 31) gives a
total output spot noise voltage of 11.2nV/√Hz and a
total equivalent input spot noise voltage of 5.6nV/√Hz.
This total input-referred spot noise voltage is higher
than the 2.1nV/√Hz specification for the op amp
voltage noise alone. This reflects the noise added to
the output by the inverting current noise times the
feedback resistor. If the feedback resistor is reduced
in high-gain configurations (as suggested previously),
the total input-referred voltage noise given by
Equation 5 will approach just the 2.1nV/√Hz of the op
amp itself. For example, going to a gain of +10 using
RF= 178Ωwill give a total input-referred noise of
2.36nV/√Hz. Figure 41. Wideband, DC-Connected Composite
DC ACCURACY AND OFFSET CONTROL Circuit
A current-feedback op amp like the OPA694 provides This DC-coupled circuit provides very high signal
exceptional bandwidth in high gains, giving fast pulse bandwidth using the OPA694. At lower frequencies,
settling, but only moderate DC accuracy. The the output voltage is attenuated by the signal gain
Electrical Characteristics show an input offset voltage and compared to the original input voltage at the
comparable to high-speed, voltage-feedback inputs of the OPA237 (this is a low-cost, precision
amplifiers. However, the two input bias currents are voltage-feedback op amp with 1.5MHz gain
somewhat higher and are unmatched. Whereas bias bandwidth product). If these two do not agree (due to
current cancellation techniques are very effective with DC offsets introduced by the OPA694), the OPA237
most voltage-feedback op amps, they do not sums in a correction current through the 2.86kΩ
generally reduce the output DC offset for wideband, inverting summing path. Several design
current-feedback op amps. Since the two input bias considerations will allow this circuit to be optimized.
currents are unrelated in both magnitude and polarity, First, the feedback to the OPA237 noninverting input
matching the source impedance looking out of each must be precisely matched to the high-speed signal
input to reduce their error contribution to the output is gain. Making the 2kΩresistor to ground an adjustable
ineffective. Evaluating the configuration of Figure 31,resistor would allow the low- and high-frequency
using worst-case +25°C input offset voltage and the gains to be precisely matched. Second, the crossover
two input bias currents, gives a worst-case output frequency region where the OPA237 passes control
offset range equal to: to the OPA694 must occur with exceptional phase
±(NG × VOS) ± (IBN × RS/2 × NG) ± (IBI × RF)linearity. These two issues reduce to designing for
pole/zero cancellation in the overall transfer function.
where NG = noninverting signal gain Using the 2.86kΩresistor will nominally satisfy this
space
space
16 Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA694
OPA694
www.ti.com
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
requirement for the circuit in Figure 41. Perfect BOARD LAYOUT GUIDELINES
cancellation over process and temperature is not Achieving optimum performance with a
possible. However, this initial resistor setting and high-frequency amplifier like the OPA694 requires
precise gain matching will minimize long-term pulse careful attention to board layout parasitics and
settling tails. external component types. Recommendations that
will optimize performance include:
THERMAL ANALYSIS a) Minimize parasitic capacitance to any AC ground
Due to the high output power capability of the for all of the signal I/O pins. Parasitic capacitance on
OPA694, heatsinking or forced airflow may be the output and inverting input pins can cause
required under extreme operating conditions. instability: on the noninverting input, it can react with
Maximum desired junction temperature will set the the source impedance to cause unintentional
maximum allowed internal power dissipation, as bandlimiting. To reduce unwanted capacitance, a
described below. In no case should the maximum window around the signal I/O pins should be opened
junction temperature be allowed to exceed +150°C. in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be
Operating junction temperature (TJ) is given by TA+unbroken elsewhere on the board.
PD×qJA. The total internal power dissipation (PD) is
the sum of quiescent power (PDQ) and additional b) Minimize the distance (< 0.25in, or 0.635cm)
power dissipated in the output stage (PDL) to deliver from the power-supply pins to high-frequency 0.1mF
load power. Quiescent power is simply the specified decoupling capacitors. At the device pins, the ground
no-load supply current times the total supply voltage and power plane layout should not be in close
across the part. PDL will depend on the required proximity to the signal I/O pins. Avoid narrow power
output signal and load but would, for a grounded and ground traces to minimize inductance between
resistive load, be at a maximum when the output is the pins and the decoupling capacitors. The
fixed at a voltage equal to 1/2 either supply voltage power-supply connections (on pins 4 and 7) should
(for equal bipolar supplies). Under this condition PDL always be decoupled with these capacitors. An
= VS2/(4 × RL) where RLincludes feedback network optional supply decoupling capacitor across the two
loading. power supplies (for bipolar operation) will improve
2nd-harmonic distortion performance. Larger (2.2mF
Note that it is the power in the output stage and not in to 6.8mF) decoupling capacitors, effective at lower
the load that determines internal power dissipation. frequencies, should also be used on the main supply
As a worst-case example, compute the maximum TJpins. These may be placed somewhat farther from
using an OPA694IDBV (SOT23-5 package) in the the device and may be shared among several
circuit of Figure 31 operating at the maximum devices in the same area of the PCB.
specified ambient temperature of +85°C and driving a c) Careful selection and placement of external
grounded 20Ωload to +2.5V DC: components will preserve the high-frequency
PD= 10V × 6.0mA + 52/[4 × (20Ω|| 804Ω)] = 380mΩperformance of the OPA694. Resistors should be a
very low reactance type. Surface-mount resistors
Maximum TJ= +85°C + (0.38W × (150°C/W) = 142°C work best and allow a tighter overall layout. Metal-film
Although this is still below the specified maximum and carbon composition, axially-leaded resistors can
junction temperature, system reliability considerations also provide good high-frequency performance.
may require lower junction temperatures. Remember, Again, keep their leads and PCB trace length as short
this is a worst-case internal power dissipation—use as possible. Never use wirewound type resistors in a
your actual signal and load to compute PDL. The high-frequency application. Since the output pin and
highest possible internal dissipation will occur if the inverting input pin are the most sensitive to parasitic
load requires current to be forced into the output for capacitance, always position the feedback and series
positive output voltages or sourced from the output output resistor, if any, as close as possible to the
for negative output voltages. This puts a high current output pin. Other network components, such as
through a large internal voltage drop in the output noninverting input termination resistors, should also
transistors. The Output Voltage and Current be placed close to the package. Where double-side
Limitations plot (Figure 21) shown in the Typical component mounting is allowed, place the feedback
Characteristics includes a boundary for 1W maximum resistor directly under the package on the other side
internal power dissipation under these conditions. of the board between the output and inverting input
pins. The frequency response is primarily determined
space by the feedback resistor value, as described
space previously. Increasing its value will reduce the
bandwidth, while decreasing it will give a more
space peaked frequency response. The 402Ωfeedback
Copyright © 2004–2010, Texas Instruments Incorporated 17
Product Folder Link(s): OPA694
-VCC
+VCC
External
Pin
Internal
Circuitry
OPA694
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
www.ti.com
resistor used in the Electrical Characteristic tables at trace as a capacitive load in this case and set the
a gain of +2 on ±5V supplies is a good starting point series resistor value as shown in the plot of
for design. Note that a 430Ωfeedback resistor, rather Recommended RSvs Capacitive Load. This will not
than a direct short, is recommended for the unity-gain preserve signal integrity as well as a
follower application. A current-feedback op amp doubly-terminated line. If the input impedance of the
requires a feedback resistor even in the unity-gain destination device is low, there will be some signal
follower configuration to control stability. attenuation due to the voltage divider formed by the
series output into the terminating impedance.
d) Connections to other wideband devices on the
board may be made with short, direct traces or e) Socketing a high-speed part like the OPA694 is
through onboard transmission lines. For short not recommended. The additional lead length and
connections, consider the trace and the input to the pin-to-pin capacitance introduced by the socket can
next device as a lumped capacitive load. Relatively create an extremely troublesome parasitic network
wide traces (50mils to 100mils, or 1,270mm to which can make it almost impossible to achieve a
2,540mm) should be used, preferably with ground smooth, stable frequency response. Best results are
and power planes opened up around them. Estimate obtained by soldering the OPA694 onto the board..
the total capacitive load and set RSfrom the plot of The additional lead length and pin-to-pin capacitance
Recommended RSvs Capacitive Load (Figure 15). introduced by the socket can create an extremely
Low parasitic capacitive loads (< 5pF) may not need troublesome parasitic network which can make it
an RS, since the OPA694 is nominally compensated almost impossible to achieve a smooth, stable
to operate with a 2pF parasitic load. If a long trace is frequency response. Best results are obtained by
required, and the 6dB signal loss intrinsic to a soldering the OPA694 onto the board.
doubly-terminated transmission line is acceptable,
implement a matched impedance transmission line INPUT AND ESD PROTECTION
using microstrip or stripline techniques (consult an The OPA694 is built using a very high speed
ECL design handbook for microstrip and stripline complementary bipolar process. The internal junction
layout techniques). A 50Ωenvironment is normally breakdown voltages are relatively low for these very
not necessary onboard, and in fact, a higher small geometry devices. These breakdowns are
impedance environment will improve distortion, as reflected in the Absolute Maximum Ratings table. All
shown in the Distortion versus Load plots. With a device pins have limited ESD protection using internal
characteristic board trace impedance defined based diodes to the power supplies, as shown in Figure 42.
on board material and trace dimensions, a matching
series resistor into the trace from the output of the These diodes provide moderate protection to input
OPA694 is used as well as a terminating shunt overdrive voltages above the supplies as well. The
resistor at the input of the destination device. protection diodes can typically support 30mA
Remember also that the terminating impedance will continuous current. Where higher currents are
be the parallel combination of the shunt resistor and possible (for example, in systems with ±15V supply
the input impedance of the destination device: this parts driving into the OPA694), current-limiting series
total effective impedance should be set to match the resistors should be added into the two inputs. Keep
trace impedance. The high output voltage and current these resistor values as low as possible, since high
capability of the OPA694 allows multiple destination values degrade both noise performance and
devices to be handled as separate transmission lines, frequency response.
each with their own series and shunt terminations. If
the 6dB attenuation of a doubly-terminated
transmission line is unacceptable, a long trace can be
series-terminated at the source end only. Treat the
Figure 42. Internal ESD Protection
18 Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA694
OPA694
www.ti.com
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (August, 2008) to Revision G Page
• Updated document format to current standards ................................................................................................................... 1
• Deleted lead temperature specifications from Absolute Maximum Ratings table ................................................................ 2
• Revised ADC Driver section to remove references to TI ADS522x devices ...................................................................... 10
• Changed Figure 33 ............................................................................................................................................................. 11
• Updated Figure 34 .............................................................................................................................................................. 11
• Changed Figure 36 ............................................................................................................................................................. 12
• Updated Figure 41 .............................................................................................................................................................. 16
REVISION HISTORY
Changes from Revision E (March, 2006) to Revision F Page
• Changed Storage Temperature minimum value from −40°C to −65°C ................................................................................ 2
Copyright © 2004–2010, Texas Instruments Incorporated 19
Product Folder Link(s): OPA694
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
OPA694ID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA694IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA694IDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA694IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA694IDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA694IDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA694IDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA694IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 7-Oct-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
OPA694IDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.1 1.39 4.0 8.0 Q3
OPA694IDBVT SOT-23 DBV 5 250 180.0 8.4 3.2 3.1 1.39 4.0 8.0 Q3
OPA694IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA694IDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
OPA694IDBVT SOT-23 DBV 5 250 210.0 185.0 35.0
OPA694IDR SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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