AOZ1110QI - Alpha & Omega Semiconductor

Rev. 1.0 October 2010 www.aosmd.com Page 1 of 16

AOZ1110

4A Synchronous EZBuck Regula tor

General Description

The AOZ1110QI is a high efficiency, easy to use, 4A

synchronous buck regulator optimized for portable

electronic devices. The AOZ1110QI works from a 2.7V to

5.5V input voltage range, and provides up to 4A of

continuous output current with an output voltage

adjustable down to 0.8V. With a 1% output accuracy

rating, the AOZ1110 is designed for low tolerance

applications, such as DSPs and FPGAs.

The AOZ1110QI is available in a 24-pin 4X4 QFN

package and is rated over a -40°C to +85°C ambient

temperature range.

Features

z2.7V to 5.5V input voltage range

z30mΩ high-side and 20mΩ low-side MOSFET

zEfficiency up to 95%

zAdjustable soft start

zOutput voltage adjustable down to 0.8V

z4A continuous output current

zSelectable 500kHz & 1MHz PWM operation

zCycle-by-cycle current limit

zOver-voltage protection

zShort-circuit protection

zThermal shutdown

zPower good indicator

zSmall size 4x4 QFN-24 package

Applications

zPoint of load DC/DC conversion for DSPs, FPGAs,

ASICs and microprocessors

zDVD and HDD

zNotebook PCs

zTelecom/Networking/Datacom equipment

Typical Application

Figure 1. Typical Application

VINVDD

FSEL

COMP

AGND PGND

PGOOD

VIN

VOUT

Css = NC

AOZ1110QI

C2, C3

22µF

Ceramic

22µF

Ceramic

MCU

1.0uH

AOZ1110

Rev. 1.0 October 2010 www.aosmd.com Page 2 of 16

Ordering Information

AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.

Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.

Pin Configuration

Pin Description

Part Number Ambient Temperature Range Package Environmental

AOZ1110QI -40°C to +85°C 24-pin 4mm x 4mm QFN Green Product

Pin Number Pin Name Pin Function

1 COMP External loop compensation pin.

2 FB The FB pin is used to determine the output voltage via a resistor divider between the

output and GND.

3 EN Device enable pin, active high.

4 PGOOD Power good signal output pin. It is an open drain logic output used to indicate the status of

output voltages. Connect a pull up resistor to VIN.

5,6 NC No connect.

7 FSEL Frequency Selection Pin. Tie this pin to ground, to set the switching frequency to 500kHz;

tie this pin to VDD, to set the switching frequency to 1MHz.

8, 23 AGND Reference connection for controller circuit. All AGND pins are connected internally.

Electrically needs to be connected to PGND. Also used as thermal connection for

controller circuit.

9 VDD Supply voltage to control circuit and gate drivers. Connect a 10Ω resistor between VIN

and VDD and a 0.1μF capacitor from VDD to AGND to decouple noise voltage.

10, 11, 12 VIN Supply voltage input. All VIN pins must be connected together externally. When VIN

voltage rises above the UVLO threshold the device starts up.

13, 14, 15, 16, 17,

18, 19, 20

LX PWM output connection to inductor. All LX pins must be connected together externally.

Also used as thermal connection for internal MOSFET.

21, 22 PGND Power ground. All PGND pins must be connected together. Electrically needs to be

connected to AGND.

24 SS Soft start pin. Connect a capacitor externally to control soft start period. Leave it open for

internal set soft-start time.

24 23 22 21 20 19

78 9101112

COMP

AGND

PGND

FSEL

AGND

VDD

VIN

24-Pin 4mm x 4mm QFN

(Top View)

Rev. 1.0 October 2010 www.aosmd.com Page 3 of 16

AOZ1110

Functional Block Diagram

Absolute Maximum Ratings

Exceeding the Absolute Maximum ratings may damage th e

device.

Recommended Operating Conditions

The device is not guaranteed to operate beyond the Maximum

Recommended Operating Conditions.

Note:

1. Devices are inherently ESD sensitive, handling precautions are

required. Human body model rating: 1.5kΩ in series with 100pF.

2. The value of ΘJA is measured with the device mounted on 1-in2

FR-4 board with 2oz. Copper, in a still air environment with TA = 25°C.

The value in any given application depends on the user's specific board

design.

500kHz / 1 MHz

Oscillator

AGND PGND

VIN

VDD

COMP

PGOOD

OTP

ILimit

PWM

Control

Logic

UVLO

& POR

Softstart

Reference

& Bias

0.8V

PWM

Comp

Level

Shifter

FET

Driver

ISen

EAmp

–

PGood Logic

FESL

Parameter Rating

Supply Voltage (VIN)6V

Supply Voltage (VDD)6V

LX to GND -0.7V to 6V

EN to GND -0.3V to 6V

FB to GND -0.3V to 6V

COMP to GND -0.3V to 6V

SS to GND -0.3V to 6V

Junction Temperature (TJ) +150°C

Storage Temperature (TS) -65°C to +150°C

ESD Rating(1) 2kV

PGOOD -0.3V to 6V

FSEL -0.3V to 6V

NC -0.3V to 6V

Parameter Rating

Supply Voltage (VIN) 2.7V to 5.5V

Output Voltage Range 0.8V to VIN

Ambient Temperature (TA) -40°C to +85°C

Package Thermal Resistance (2)

4x4 QFN-24 (ΘJA)

45°C/W

AOZ1110

Rev. 1.0 October 2010 www.aosmd.com Page 4 of 16

Electrical Characteristics

TA = 25°C, VIN = VEN = 3.3V, unless otherwise specified(3)

Symbol Parameter Condition Min. Typ. Max. Units

VIN Supply Voltage 2.7 5.5 V

VUVLO Input Under-Voltage Lockout

Threshold

VIN rising

VIN falling 2.20 2.50

2.30 2.60 V

IIN Supply Current (Quiescent) VFB = 1.0V, L disconnected 1.5 3 mA

IOFF Shutdown Supply Current VEN = 0V,

Active PGood = 100kΩ

Excluding PG current

1μA

VFB Feedback Voltage TA = 25°C

TA = -40°C to 85°C

0.792

0.784

0.800

0.808

0.816

Load Regulation 0A < Iload < 3A,

VIN = 3.3V, VOUT =1 .5V

0.2 %

Line Regulation 2.7V < VIN < 5.5V,

VOUT = 1.5V Iload = 100mA

0.2 %

IFB FB Input Current 200 nA

ENABLE

VEN EN Input Threshold Off threshold

On threshold 1.2 0.4 V

VHYS EN Input Hysteresis 200 mV

OSCILLATOR

fOFrequency FSEL = VDD 0.85 1.0 1.15 MHz

FSEL = GND 425 500 575 kHz

DMAX Maximum Duty Cycle(4) 100 %

tON_MIN Minimum Controllable on time(4) 200 ns

ERROR AMPLIFIER

GVEA Error Amplifier Open Loop Voltage

gain(4)

60 dB

GEA Error Amplifier

Transconductance(4)

200 μA / V

OVER CURRENT, OVER VOLTAGE AND OVER TEMPERATURE

ILIM Current Limit VIN = 3.3V 5 6 7 A

Current Limit Response Time(4) 200 ns

TLO Short Circuit Latch off Time VFB = 0V 2 ms

OVP Over Voltage Protection 115 %

OVP Hyteresis 3 %

Over-Temperature shutdown limit TJ rising

TJ falling

150

100

°C

OSCILLATOR

ISS_OUT Soft Start Pin Source Current SS = 0V,

CSS = 0.001μF to 0.1μF

1.5 2.0 3.0 μA

ISS_IN Soft Start Pin Sink Current VIN = 2.7V,

CSS = 0.001μF to 0.1μF

1.5 3.0 5.0 mA

tSS Internal Soft Time CSS = open 500 μs

AOZ1110

Rev. 1.0 October 2010 www.aosmd.com Page 5 of 16

Notes:

3. Specification in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design.

4. Guaranteed by design.

PWM OUTPUT STAGE

RDS(ON) High-Side PFET On-Resistance VIN = 5V 33 64 mΩ

High-Side PFET Leakage VEN = 0V, VLX = 0V 10 μA

RDS(ON) Low-Side NFET On-Resistance VLX = 5V 19 30 mΩ

Low-Side NFET Leakage VEN = 0V 10 μA

POWER GOOD

VOLPG PG LOW Voltage I(sink) = 1.0mA 0.3 V

PG Leakage Current V = 5.5V ±1 μA

PG Upper Threshold Voltage Fraction of set point 110 115 120 %

PG Lower Threshold Voltage Fraction of set point 80 85 90 %

PG Hysteresis Voltage 3%

tPG PG Falling Edge Deglitch Time 120 μs

Symbol Parameter Condition Min. Typ. Max. Units

Electrical Characteristics (Continued)

TA = 25°C, VIN = VEN = 3.3V, unless otherwise specified(3)

AOZ1110

Rev. 1.0 October 2010 www.aosmd.com Page 6 of 16

Typical Performance Characteristics

Circuit of Figure 1 with internal soft-start. TA = 25°C, VIN = VEN = 3.3V, VOUT = 1.2V unless otherwise specified.

Switching Waveforms at Light Load Switching Waveforms at Heavy Load

Vo ripple

10mV/div

Vin ripple

0.1V/div

VLX

5V/div

1A/div

Enable

5V/div

Pgood

2V/div

0.5V/div

IIN

2A/div

5V/div

Pgood

2V/div

1V/div

5A/div

50mV/div

2A/div

5V/div

Pgood

2V/div

1V/div

5A/div

Vo ripple

10mV/div

Vin ripple

0.1V/div

VLX

5V/div

1A/div

Start Up Waveforms Short-Circuit Protection Waveforms

Load Transient Waveforms Short-Circuit Recovery Waveforms

400ns/div 400ns/div

200us/div 1ms/div

1ms/div 1ms/div

AOZ1110

Rev. 1.0 October 2010 www.aosmd.com Page 7 of 16

Efficiency

Efficiency (fSW = 1MHz, VIN = 5V) vs. Load Current

100

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Load Current (A)

Efficieny (%)

Efficiency (fSW = 1MHz, VIN = 3.3V) vs. Load Current

100

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Load Current (A)

Efficieny (%)

OUTPUT:

Efficiency (fSW = 500kHz, VIN = 5V) vs. Load Current

100

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Load Current (A)

Efficieny (%)

Efficiency (fSW = 500kHz, VIN = 3.3V) vs. Load Current

100

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Load Current (A)

Efficieny (%)

3.3V

1.8V

1.2V

OUTPUT:

3.3V

1.8V

1.2V

OUTPUT:

1.8V

1.2V

OUTPUT:

1.8V

1.2V

AOZ1110

Rev. 1.0 October 2010 www.aosmd.com Page 8 of 16

Detailed Description

The AOZ1110QI is a current-mode synchronous step

down regulator with complimentary MOSFET switches.

The operating input voltage range is 2.7V to 5.5V. The

output range can be adjusted to a minimum of 0.8V and

supplies up to 4A

of continuous current. Features include

cycle-by-cycle current limiting, short circuit protection,

adjustable soft start and a power good output signal.

Enable and Soft Start

The AOZ1110QI has both internal and external soft start

feature to limit in-rush current and ensure the output

voltage ramps up smoothly to regulation voltage. A soft

start process begins when the input voltage rises to 2.5V

and voltage on EN pin is HIGH. In the soft start, a 2

internal current source charges the external capacitor at

SS. As the SS capacitor is charged, the voltage at SS

rises. The SS voltage clamps the reference voltage of the

error amplifier, therefore output voltage rising time follows

the SS pin voltage. With the slow ramping up output

voltage, the inrush current can be prevented. If there is no

external capacitor connected to the SS pin, the internal

soft start will operate at 500

Power Good

The output of power good is an open drain N-MOSFET,

which supplies an active high power good stage. A pull-

up resistor (R3) should connect this pin to a DC power

trail with maximum voltage no higher than 6V. The

AOZ1110QI monitors the FB voltage: when the FB pin

voltage is lower than 85% of the target voltage or higher

than 115% of the target voltage, N-MOSFET turns on and

the power good pin is pulled low, which indicates the

power is abnormal.

Steady-State Operation

Under steady-state conditions, the converter operates in

fixed frequency and Continuous-Conduction Mode

(CCM).

The AOZ1110QI integrates an internal P-MOSFET as the

high-side switch. Inductor current is sensed by amplifying

the voltage drop across the drain to source of the high

side power MOSFET. Output voltage is divided down by

the external voltage divider at the FB pin. The difference

of the FB pin voltage and reference is amplified by the

internal transconductance error amplifier. The error

voltage, which shows on the COMP pin, is compared

against the current signal, which is sum of inductor

current signal and ramp compensation signal, at PWM

comparator input. If the current signal is less than the

error voltage, the internal high-side switch is on. The

inductor current flows from the input through the inductor

to the output. When the current signal exceeds the error

voltage, the high-side switch is off. The inductor current is

freewheeling through the internal low-side N-MOSFET

switch to output. The internal adaptive FET driver

guarantees no turn on overlap of both high-side and

low-side switch.

Comparing with regulators using freewheeling Schottky

diodes, the AOZ1110QI uses freewheeling N-MOSFET to

realize synchronous rectification. It greatly improves the

converter efficiency and reduces power loss in the

low-side switch.

The AOZ1110QI uses a P-MOSFET as the high-side

switch. It saves the bootstrap capacitor normally seen in

a circuit which is using an N-MOSFET switch.

Switching Frequency

The AOZ1110QI switching frequency can be selected by

FSEL pin. When the FSEL logic is tied to VDD, the

switching frequency will be 1.0 MHz. When the FSEL

logic is tied to GND, the switching frequency will be

0.5 MHz.

Output Voltage Programming

Output voltage can be set by feeding back the output to

the FB pin by using a resistor divider network. In the

application circuit shown in Figure 1. The resistor divider

network includes R1 and R2. Usually, a design is started

by picking a fixed R2 value and calculating the required

R1 with equation below.

Some standard value of R1, R2 and most used output

voltage values are listed in Table 1.

Table 1.

The combination of R1 and R2 should be large enough to

avoid drawing excessive current from the output, which

will cause power loss.

Vo (V) R1 (kΩ) Rs (kΩ)

0.8 1.0 open

1.2 4.99 10

1.5 10 11.5

1.8 12.7 10.2

2.5 21.5 10

3.3 31.1 10

5.0 52.3 10

VO0.8 1 R1

-------

⎝⎠

⎜⎟

⎛⎞

×=

AOZ1110

Rev. 1.0 October 2010 www.aosmd.com Page 9 of 16

Since the switch duty cycle can be as high as 100%, the

maximum output voltage can be set as high as the input

voltage minus the voltage drop on upper P-MOSFET and

inductor.

Protection Features

The AOZ1110QI has multiple protection features to

prevent system circuit damage under abnormal

conditions.

Over Current Protection (OCP)

The sensed inductor current signal is also used for over

current protection. Since the AOZ1110QI employs peak

current mode control, the COMP pin voltage is

proportional to the peak inductor current. The COMP pin

voltage is limited to be between 0V and 2.2V internally.

The peak inductor current is automatically limited cycle

by cycle.

Power-On Reset (POR)

A power-on reset circuit monitors the input voltage. When

the input voltage exceeds 2.5V, the converter starts

operation. When input voltage falls below 2.3V, the

converter will be shut down.

Output Over Voltage Protection (OVP)

The AOZ1110QI monitors the feedback voltage: when

the feedback voltage is higher than 15% of set value, it

immediately turns off P-MOSFET cycle by cycle to

protect the output voltage overshoot at fault condition.

Thermal Protection

An internal temperature sensor monitors the junction

temperature. It shuts down both high side P-MOSFET

and low side N-MOSFET if the junction temperature

exceeds 150ºC. The regulator will restart automatically

under the control of soft start circuit when the junction

temperature decreases to 100ºC.

Application Information

The basic AOZ1110QI application circuit is show in

Figure 1. Component selection is explained below.

Input Capacitor

The input capacitor must be connected to the VIN pin and

PGND pin of AOZ1110QI to maintain steady input voltage

and filter out the pulsing input current. The voltage rating

of input capacitor must be greater than maximum input

voltage plus ripple voltage.

The input ripple voltage can be approximated by

equation below:

Since the input current is discontinuous in a buck

converter, the current stress on the input capacitor is

another concern when selecting the capacitor. For a buck

circuit, the RMS value of input capacitor current can be

calculated by:

if we let m equal the conversion ratio:

The relation between the input capacitor RMS current

and voltage conversion ratio is calculated and shown in

Figure 2. It can be seen that when VO is half of VIN,

CIN is under the worst current stress. The worst current

stress on CIN is 0.5 x IO.

Figure 2. ICIN vs. Voltage Conversion Ratio

For reliable operation and best performance, the input

capacitors must have current rating higher than ICIN_RMS

at worst operating conditions. Ceramic capacitors are

preferred for input capacitors because of their low ESR

and high current rating. Depending on the application

circuits, other low ESR tantalum capacitor may also be

used. When selecting ceramic capacitors, X5R or X7R

type dielectric ceramic capacitors should be used for

their better temperature and voltage characteristics.

Note that the ripple current rating from capacitor

manufactures are based on certain amount of life time.

Further de-rating may be necessary in practical design.

ΔVIN IO

----------------- 1VO

VIN

---------

–

⎝⎠

⎜⎟

⎛⎞

VIN

---------

××=

ICIN_RMS IOVO

VIN

---------1VO

VIN

---------

–

⎝⎠

⎜⎟

⎛⎞

×=

VIN

---------m=

0.1

0.2

0.3

0.4

0.5

0 0.5 1

CIN_RMS

(m)

AOZ1110

Rev. 1.0 October 2010 www.aosmd.com Page 10 of 16

Inductor

The inductor is used to supply constant current to output

when it is driven by a switching voltage. For given input

and output voltage, inductance and switching frequency

together decide the inductor ripple current, which is:

The peak inductor current is:

High inductance gives low inductor ripple current but

requires larger size inductor to avoid saturation. Low

ripple current reduces inductor core losses. It also

reduces RMS current through inductor and switches,

which results in less conduction loss. Usually, peak to

peak ripple current on inductor is designed to be

20% to 30% of output current.

When selecting the inductor, make sure it is able to

handle the peak current without saturation even at the

highest operating temperature.

The inductor takes the highest current in a buck circuit.

The conduction loss on inductor need to be checked for

thermal and efficiency requirements.

Surface mount inductors in different shape and styles are

available from Coilcraft, Elytone and Murata. Shielded

inductors are small and radiate less EMI noise. But they

cost more than unshielded inductors. The choice

depends on EMI requirement, price and size.

Output Capacitor

The output capacitor is selected based on the DC output

voltage rating, output ripple voltage specification and

ripple current rating.

The selected output capacitor must have a higher rated

voltage specification than the maximum desired output

voltage including ripple. De-rating needs to be

considered for long term reliability.

Output ripple voltage specification is another important

factor for selecting the output capacitor. In a buck

converter circuit, output ripple voltage is determined by

inductor value, switching frequency, output capacitor

value and ESR. It can be calculated by the equation

below:

where;

CO is output capacitor value,

and ESRCO is the Equivalent Series Resistor of output

capacitor.

When low ESR ceramic capacitor is used as output

capacitor, the impedance of the capacitor at the switching

frequency dominates. Output ripple is mainly caused by

capacitor value and inductor ripple current. The output

ripple voltage calculation can be simplified to:

If the impedance of ESR at switching frequency

dominates, the output ripple voltage is mainly decided by

capacitor ESR and inductor ripple current. The output

ripple voltage calculation can be further simplified to:

For lower output ripple voltage across the entire

operating temperature range, X5R or X7R dielectric type

of ceramic, or other low ESR tantalum are recommended

to be used as output capacitors.

In a buck converter, output capacitor current is

continuous. The RMS current of output capacitor is

decided by the peak to peak inductor ripple current. It can

be calculated by:

Usually, the ripple current rating of the output capacitor is

a smaller issue because of the low current stress. When

the buck inductor is selected to be very small and

inductor ripple current is high, output capacitor could be

overstressed.

Loop Compensation

The AOZ1110QI employs peak current mode control for

easy use and fast transient response. Peak current mode

control eliminates the double pole effect of the output

L&C filter. It greatly simplifies the compensation loop

design.

With peak current mode control, the buck power stage

can be simplified to be a one-pole and one-zero system

in frequency domain. The pole is dominant pole can be

calculated by:

ΔILVO

fL×

-----------1VO

VIN

---------

–

⎝⎠

⎜⎟

⎛⎞

×=

ILpeak IO

ΔIL

--------

ΔVOΔILESRCO 1

8fC

××

-------------------------

⎝⎠

⎛⎞

×=

ΔVOΔIL1

8fC

××

-------------------------

⎝⎠

⎛⎞

×=

ΔVOΔILESRCO

×=

ICO_RMS

ΔIL

----------

fp1

2πCORL

××

-----------------------------------

AOZ1110

Rev. 1.0 October 2010 www.aosmd.com Page 11 of 16

The zero is a ESR zero due to output capacitor and its

ESR. It is can be calculated by:

where;

CO is the output filter capacitor,

RL is load resistor value,

ESRCO is the equivalent series resistance of output capacitor.

The compensation design is actually to shape the

converter control loop transfer function to get desired

gain and phase. Several different types of compensation

network can be used for the AOZ1110QI. For most

cases, a series capacitor and resistor network connected

to the COMP pin sets the pole-zero and is adequate for a

stable high-bandwidth control loop.

In the AOZ1110QI, FB pin and COMP pin are the

inverting input and the output of internal error amplifier. A

series R and C compensation network connected to

COMP provides one pole and one zero. The pole is:

where;

GEA is the error amplifier transconductance, which is

200 x 10-6 A/V,

GVEA is the error amplifier voltage gain, which is 500 V/V,

and, CC is the compensation capacitor in Figure1.

The zero given by the external compensation network,

capacitor CC and resistor RC, is located at:

To design the compensation circuit, a target crossover

frequency fC for close loop must be selected. The system

crossover frequency is where control loop has unity gain.

The crossover is the also called the converter bandwidth.

Generally a higher bandwidth means faster response to

load transient. However, the bandwidth should not be too

high because of system stability concern. When

designing the compensation loop, converter stability

under all line and load condition must be considered.

Usually, it is recommended to set the bandwidth to be

equal or less than 1/10 of switching frequency. The

strategy for choosing Rc and Cc is to set the cross over

frequency with Rc and set the compensator zero with CC.

Using selected crossover frequency, fC, to calculate RC:

where;

fC is desired crossover frequency. For best performance, fC is

set to be about 1/10 of switching frequency,

VFB is 0.8V,

GEA is the error amplifier transconductance, which is

200 x 10-6 A/V;

GCS is the current sense circuit transconductance, which is

10 A/V.

The compensation capacitor CC and resistor RC together

make a zero. This zero is put somewhere close to the

dominate pole fp1 but lower than 1/5 of selected cross-

over frequency. CC can is selected by:

The equation above can also be simplified to:

An easy-to-use application software which helps to

design and simulate the compensation loop can be found

at www.aosmd.com.

fZ1

2πCOESRCO

××

------------------------------------------------

fp2

GEA

2πCCGVEA

××

-------------------------------------------

fZ2

2πCCRC

××

-----------------------------------

RCfCVO

VFB

---------- 2πCO

GEA GCS

------------------------------

××=

CC1.5

2πRCfp1

××

-----------------------------------

CCCORL

---------------------

AOZ1110

Rev. 1.0 October 2010 www.aosmd.com Page 12 of 16

Thermal Management and Layout

Consideration

In the AOZ1110QI buck regulator circuit, high pulsing

current flows through two circuit loops. The first loop

starts from the input capacitors, to the VIN pin, to the LX

pins, to the filter inductor, to the output capacitor and

load, and then return to the input capacitor through

ground. Current flows in the first loop when the high side

switch is on. The second loop starts from inductor, to the

output capacitors and load, to the low-side N-MOSFET.

Current flows in the second loop when the low side N-

MOSFET is on.

In PCB layout, minimizing the two loops area reduces the

noise of this circuit and improves efficiency. A ground

plane is strongly recommended to connect input

capacitor, output capacitor, and PGND pin of the

AOZ1110QI.

In the AOZ1110QI buck regulator circuit, the major power

dissipating components are the AOZ1110QI and the

output inductor. The total power dissipation of converter

circuit can be measured by input power minus output

power:

The power dissipation of inductor can be approximately

calculated by output current and DCR of inductor:

The actual junction temperature can be calculated with

power dissipation in the AOZ1012D and thermal

impedance from junction to ambient:

The maximum junction temperature of AOZ1110QI is

150ºC, which limits the maximum load current capability.

The thermal performance of the AOZ1110QI is strongly

affected by the PCB layout. Extra care should be taken

by users during design process to ensure that the IC will

operate under the recommended environmental

conditions.

Several layout tips are listed below for the best electric

and thermal performance.

1. The LX pins are connected to internal P-MOSFET

and N-MOSFET drains. They are low resistance

thermal conduction path and most noisy switching

node. Connect a large copper plane to LX pin to help

thermal dissipation. For full load (4A) application,

also connect the LX pads to the bottom layer by

thermal vias to enhance the thermal dissipation.

2. Do not use thermal relief connection to the VIN and

the PGND pin. Pour a maximized copper area to the

PGND pin and the VIN pin to help thermal

dissipation.

3. Input capacitor should be connected to the VIN pin

and the PGND pin as close as possible.

4. A ground plane is preferred. If a ground plane is not

used, separate PGND from AGND and connect them

only at one point to avoid the PGND pin noise

coupling to the AGND pin.

5. Make the current trace from LX pins to L to Co to the

PGND as short as possible.

6. Pour copper plane on all unused board area and

connect it to stable DC nodes, like VIN, GND or

VOUT.

7. Keep sensitive signal trace far away form the LX

pins.

Ptotal_loss VIN IIN VOIO

×–×=

Pinductor_loss IO2Rinductor 1.1××=

Tjunction Ptotal_loss Pinductor_loss

–()Θ

×=

AOZ1110

Rev. 1.0 October 2010 www.aosmd.com Page 13 of 16

Package Dimensions, QFN 4x4-24L

TOP VIEW

SIDE VIEW

BOTTOM VIEW

L1 (4x)

D/2

E/2

INDEX AREA

(D/2xE/2)

aaa C

SEATING

PLANE

24 x b

Cbbb MAB

e/2

PIN#1 DIA

R0.30

e/2

ccc C

ddd C

aaa C

18 13

D1/2

AOZ1110

Rev. 1.0 October 2010 www.aosmd.com Page 14 of 16

Package Dimensions, QFN 4x4-24L (Continued)

RECOMMENDED LAND PATTERN

Dimensions in millimeters

0.80

0.05

0.30

2.70

1.35

1.05

0.45

0.40

0.45

0.15

0.75

0.02

0.20 REF

0.25

4.00 BSC

2.60

4.00 BSC

1.25

0.95

0.50 BSC

0.40

0.30

0.35

0.05

0.15

0.10

0.08

0.70

0.00

0.20

2.50

1.15

0.85

0.35

0.20

0.25

---

aaa

bbb

ccc

ddd

UNIT: MM

0.30

Symbols Min. Typ. Max.

Dimensions in inches

0.031

0.002

0.012

0.106

0.053

0.041

0.018

0.016

0.018

0.006

0.030

0.001

0.008 REF.

0.010

0.157 BSC

0.102

0.157 BSC

0.049

0.037

0.020 BSC

0.016

0.012

0.014

0.002

0.006

0.004

0.003

0.028

0.000

0.008

0.098

0.045

0.033

0.014

0.008

0.010

---

aaa

bbb

ccc

ddd

Symbols Min. Typ. Max.

1.30

2.60 0.30

0.30

0.95

0.35

0.30

1.85

0.25

0.50 Ref (20x)

0.50

0.05

1.25 2.60

0.25 x 45˚

1.30

0.25

AOZ1110

Rev. 1.0 October 2010 www.aosmd.com Page 15 of 16

Tape and Reel Dimensions, QFN 4x4-24L

Package

QFN 4x4

(12 mm)

A0 B0 K0 E E1 E2D0 D1 P0 P1 P2 T

4.35

±0.10 ±0.10

1.10

Min.

1.50 1.50

+0.1/-0.0 ±0.3

12.0

±0.10

1.75

±0.05

5.50

±0.10

8.00

±0.10

4.00

±0.05

2.00

±0.05

0.30

WNM

ø79.0ø330.0

±2.0

12.412 mm

Tape Size VRSK

±0.5

2.010.5

———

HW1

ø13.0

±0.5

17.0

Reel Size

ø330

UNIT: MM

±1.0 +2.0/-0.0 +2.6/-1.2

D1 P1

±0.2

±0.10

4.35

Carrier Tape

Reel

Trailer Tape

300mm min. or

75 empty pockets

Components Tape

Orientation in Pocket

Leader Tape

500mm min. or

125 empty pockets

Leader/Trailer and Orientation

Feeding Direction

Rev. 1.0 October 2010 www.aosmd.com Page 16 of 16

AOZ1110

As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant into

the body or (b) support or sustain life, and (c) whose

failure to perform when properly used in accordance

with instructions for use provided in the labeling, can be

reasonably expected to result in a significant injury of

the user.

2. A critical component in any component of a life

support, device, or system whose failure to perform can

be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or

effectiveness.

This datasheet contains preliminary data; supplementary data may be published at a later date.

Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.

LIFE SUPPORT POLICY

ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL

COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.

Part Marking

Part Number Code

Assembly Lot Code

Fab & Assembly Location

Year & Week Code

Z1110QI

FAYWLT

AOZ1110QI

(QFN 4 x 4)