FC-PBGA–783
29 mm 29 mm
Freescale Semiconductor
Data Sheet
© 2008–2013 Freescale Semiconductor, Inc. All rights reserved.
MSC8156
Document Number: MSC8156
Rev. 6, 7/2013
Six StarCore SC3850 DSP subsystems, each with an SC3850
DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache,
unified 512 Kbyte L2 cache configurable as M2 memory in
64 Kbyte increments, memory management unit (MMU),
extended programmable interrupt controller (EPIC), two
general-purpose 32-bit timers, debug and profiling support,
low-power Wait, Stop, and power-down processing modes, and
ECC/EDC support.
Chip-level arbitration and switching system (CLASS) that
provides full fabric non-blocking arbitration between the cores
and other initiators and the M2 memory, shared M3 memory,
DDR SRAM controllers, device configuration control and status
registers, MAPLE-B, and other targets.
1056 Kbyte 128-bit wide M3 memory, 1024 Kbytes of which can
be turned off to save power.
96 Kbyte boot ROM.
Three input clocks (one global and two differential).
Five PLLs (three global and two Serial RapidIO PLLs).
Multi-Accelerator Platform Engine for Baseband (MAPLE-B)
with a programmable system interface, Turbo decoding, Viterbi
decoding, and FFT/iFFT and DFT/iDFT processing. MAPLE-B
can be disabled when not required to reduce overall power
consumption.
Two DDR controllers with up to a 400 MHz clock (800 MHz data
rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in up to
four banks (two per controller) and support for DDR2 and DDR3.
DMA controller with 32 unidirectional channels supporting 16
memory-to-memory channels with up to 1024 buffer descriptors
per channel, and programmable priority, buffer, and multiplexing
configuration. It is optimized for DDR SDRAM.
Up to four independent TDM modules with programmable word
size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion,
up to 62.5 Mbps data rate for each TDM link, and with glueless
interface to E1 or T1 framers that can interface with
H-MVIP/H.110 devices, TSI, and codecs such as AC-97.
High-speed serial interface that supports two Serial RapidIO
interfaces, one PCI Express interface, and two SGMII interfaces
(multiplexed). The Serial RapidIO interfaces support 1x/4x
operation up to 3.125 Gbaud with a single messaging unit and two
DMA units. The PCI Express controller supports 32- and 64-bit
addressing, x4, x2, and x1 link.
QUICC Engine technology subsystem with dual RISC
processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction
RAM, supporting two communication controllers for two Gigabit
Ethernet interfaces (RGMII or SGMII), to offload scheduling
tasks from the DSP cores, and an SPI.
I/O Interrupt Concentrator consolidates all chip maskable
interrupt and non-maskable interrupt sources and routes then to
INT_OUT, NMI_OUT, and the cores.
UART that permits full-duplex operation with a bit rate of up to
6.25 Mbps.
Two general-purpose 32-bit timers for RTOS support per SC3850
core, four timer modules with four 16-bit fully programmable
timers, and eight software watchdog timers (SWT).
Eight programmable hardware semaphores.
Up to 32 virtual interrupts and a virtual NMI asserted by simple
write access.
•I
2C interface.
Up to 32 GPIO ports, sixteen of which can be configured as
external interrupts.
Boot interface options include Ethernet, Serial RapidIO interface,
I2C, and SPI.
Supports standard JTAG interface
Low power CMOS design, with low-power standby and
power-down modes, and optimized power-management circuitry.
45 nm SOI CMOS technology.
Six-Core Digital Signal
Processor
MSC8156 Six-Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor2
Table of Contents
1 Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 FC-PBGA Ball Layout Diagram. . . . . . . . . . . . . . . . . . . .4
1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .5
2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.2 Recommended Operating Conditions. . . . . . . . . . . . . .25
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .25
2.4 CLKIN Requirements . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .26
2.6 AC Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . .37
3 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .55
3.1 Power Supply Ramp-Up Sequence. . . . . . . . . . . . . . . .55
3.2 PLL Power Supply Design Considerations . . . . . . . . . .58
3.3 Clock and Timing Signal Board Layout Considerations 59
3.4 SGMII AC-Coupled Serial Link Connection Example . .59
3.5 Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .60
3.6 Guide to Selecting Connections for Remote Power
Supply Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
6 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
List of Figures
Figure 1. MSC8156 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. StarCore SC3850 DSP Subsystem Block Diagram . . . . 3
Figure 3. MSC8156 FC-PBGA Package, Top View . . . . . . . . . . . . 4
Figure 4. Differential Voltage Definitions for Transmitter or
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 5. Receiver of SerDes Reference Clocks . . . . . . . . . . . . . 30
Figure 6. SerDes Transmitter and Receiver Reference Circuits. . 31
Figure 7. Differential Reference Clock Input DC Requirements
(External DC-Coupled) . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 8. Differential Reference Clock Input DC Requirements
(External AC-Coupled) . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 9. Single-Ended Reference Clock Input DC Requirements 33
Figure 10.SGMII Transmitter DC Measurement Circuit. . . . . . . . . 35
Figure 11.DDR2 and DDR3 SDRAM Interface Input Timing
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 12.MCK to MDQS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 13.DDR SDRAM Output Timing . . . . . . . . . . . . . . . . . . . . . 40
Figure 14.DDR2 and DDR3 Controller Bus AC Test Load. . . . . . . 40
Figure 15.DDR2 and DDR3 SDRAM Differential Timing
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 16.Differential Measurement Points for Rise and Fall Time 42
Figure 17.Single-Ended Measurement Points for Rise and Fall Time
Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 18.Single Frequency Sinusoidal Jitter Limits . . . . . . . . . . . 45
Figure 19.SGMII AC Test/Measurement Load. . . . . . . . . . . . . . . . 46
Figure 20.TDM Receive Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 21.TDM Transmit Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 22.TDM AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 23.Timer AC Test Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 24.MII Management Interface Timing. . . . . . . . . . . . . . . . . 50
Figure 25.RGMII AC Timing and Multiplexing . . . . . . . . . . . . . . . . 51
Figure 26.SPI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 27.SPI AC Timing in Slave Mode (External Clock). . . . . . . 52
Figure 28.SPI AC Timing in Master Mode (Internal Clock) . . . . . . 52
Figure 29.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 30.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . . . 54
Figure 31.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 32.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 33.Supply Ramp-Up Sequence with VDD Ramping Before
VDDIO and CLKIN Starting With VDDIO . . . . . . . . . . . . . 55
Figure 34.Supply Ramp-Up Sequence . . . . . . . . . . . . . . . . . . . . . 57
Figure 35.Reset Connection in Functional Application . . . . . . . . . 57
Figure 36.Reset Connection in Debugger Application. . . . . . . . . . 57
Figure 37.PLL Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 38.SerDes PLL Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 39.4-Wire AC-Coupled SGMII Serial Link Connection
Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 40.MSC8156 Mechanical Information, 783-ball FC-PBGA
Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
MSC8156 Six-Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor 3
Figure 1. MSC8156 Block Diagram
Figure 2. StarCore SC3850 DSP Subsystem Block Diagram
JTAG
RMU
Note: The arrow direction indicates master or slave.
DDR Interface 64/32-bit
4 TDMs
DMA
I/O-Interrupt
Concentrator
UART
Clocks
Timers
Reset
Semaphores
Other
DDR
CLASS
High-Speed Serial Interface
Modules
QUICCEngine
Four TDMs 256-Channels each
4x 3.125 Gbaud
Boot ROM
I2C
Virtual
Interrupts
Controller
SPI
DMA
Serial
DMA
Serial
MAPLE-B
4x 3.125 Gbaud
Six DSP Cores at 1 GHz
Tu r b o / SGMII
Viterbi
FFT/
IFFT
DFT/
IDFT
Two S G M II
RGMII RGMII
M3 Memory
1056 Kbyte
PCI-EX 1x/2x/4x
Subsystem
Dual RISC Processors
EthernetEthernetSPI
SC3850
DSP Core
512 Kbyte
32 Kbyte 32 Kbyte
L1
ICache
L1
DCache
L2 Cache / M2 Memory
RapidIO RapidIO
DDR Interface 64/32-bit
DDR
Controller
PCI
Expr
SerDes 1 SerDes 2
x2
Two S G MII
32 Kbyte Address
Translation
Task
Protection
32 Kbyte
(WTB) (WBB)
EPIC
Interrupts
P-bus 128 bit
Xa-bus 64 bit
Xb-bus 64-bit
DQBus
Debug Support
OCE30
512 Kbyte L2 Cache / M2 Memory
MMU
Timer
128 bits master
IQBus
DPU
SC3850
Core
TWB
Write-
Through
Buffer
Write-
Back
Buffer
Instruction
Cache Data
Cache
bus to CLASS 128 bits slave
bus from CLASS
MSC8156 Six-Core Digital Signal Processor Data Sheet, Rev. 6
Pin Assignment
Freescale Semiconductor4
1 Pin Assignment
This section includes diagrams of the MSC8156 package ball grid array layouts and tables showing how the pinouts are
allocated for the package.
1.1 FC-PBGA Ball Layout Diagram
The top view of the FC-PBGA package is shown in Figure 3 with the ball location index numbers.
Figure 3. MSC8156 FC-PBGA Package, Top View
MSC8156
Top View
1342567810 151312119
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
14 16 17 18 19 20 21 22 23 24 25 26 27 28
AH
MSC8156 Six-Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor 5
1.2 Signal List By Ball Location
Table 1 presents the signal list sorted by ball number. When designing a board, make sure that the power rail for each signal is
appropriately considered. The specified power rail must be tied to the voltage level specified in this document if any of the
related signal functions are used (active)
Note: The information in Table 1 and Table 2 distinguishes among three concepts. First, the power pins are the balls of the
device package used to supply specific power levels for different device subsystems (as opposed to signals). Second,
the power rails are the electrical lines on the board that transfer power from the voltage regulators to the device. They
are indicated here as the reference power rails for signal lines; therefore, the actual power inputs are listed as N/A
with regard to the power rails. Third, symbols used in these tables are the names for the voltage levels (absolute,
recommended, and so on) and not the power supplies themselves.
Table 1. Signal List by Ball Number
Ball Number Signal Name1,2 Pin Type10 Power Rail
Name
A2 M2DQS3 I/O GVDD2
A3 M2DQS3 I/O GVDD2
A4 M2ECC0 I/O GVDD2
A5 M2DQS8I/O GVDD2
A6 M2DQS8 I/O GVDD2
A7 M2A5 OGVDD2
A8 M2CK1OGVDD2
A9 M2CK1 OGVDD2
A10 M2CS0OGVDD2
A11 M2BA0 OGVDD2
A12 M2CAS OGVDD2
A13 M2DQ34 I/O GVDD2
A14 M2DQS4I/O GVDD2
A15 M2DQS4 I/O GVDD2
A16 M2DQ50 I/O GVDD2
A17 M2DQS6I/O GVDD2
A18 M2DQS6 I/O GVDD2
A19 M2DQ48 I/O GVDD2
A20 M2DQ49 I/O GVDD2
A21 VSS Ground N/A
A22 Reserved NC
A23 SXPVDD1 Power N/A
A24 SXPVSS1 Ground N/A
A25 Reserved NC
A26 Reserved NC
A27 SXCVDD1 Power N/A
A28 SXCVSS1 Ground N/A
B1 M2DQ24 I/O GVDD2
B2 GVDD2 Power N/A
B3 M2DQ25 I/O GVDD2
B4 VSS Ground N/A
B5 GVDD2 Power N/A
B6 M2ECC1 I/O GVDD2
MSC8156 Six-Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor6
B7 VSS Ground N/A
B8 GVDD2 Power N/A
B9 M2A13 OGVDD2
B10 VSS Ground N/A
B11 GVDD2 Power N/A
B12 M2CS1OGVDD2
B13 VSS Ground N/A
B14 GVDD2 Power N/A
B15 M2DQ35 I/O GVDD2
B16 VSS Ground N/A
B17 GVDD2 Power N/A
B18 M2DQ51 I/O GVDD2
B19 VSS Ground N/A
B20 GVDD2 Power N/A
B21 Reserved NC
B22 Reserved NC
B23 SR1_TXD0 O SXPVDD1
B24 SR1_TXD0 O SXPVDD1
B25 SXCVDD1 Power N/A
B26 SXCVSS1 Ground N/A
B27 SR1_RXD0 I SXCVDD1
B28 SR1_RXD0 I SXCVDD1
C1 M2DQ28 I/O GVDD2
C2 M2DM3 OGVDD2
C3 M2DQ26 I/O GVDD2
C4 M2ECC4 I/O GVDD2
C5 M2DM8 OGVDD2
C6 M2ECC2 I/O GVDD2
C7 M2CKE1 OGVDD2
C8 M2CK0 OGVDD2
C9 M2CK0OGVDD2
C10 M2BA1 OGVDD2
C11 M2A1 OGVDD2
C12 M2WE OGVDD2
C13 M2DQ37 I/O GVDD2
C14 M2DM4 OGVDD2
C15 M2DQ36 I/O GVDD2
C16 M2DQ32 I/O GVDD2
C17 M2DQ55 I/O GVDD2
C18 M2DM6 OGVDD2
C19 M2DQ53 I/O GVDD2
C20 M2DQ52 I/O GVDD2
C21 Reserved NC
Table 1. Signal List by Ball Number (continued)
Ball Number Signal Name1,2 Pin Type10 Power Rail
Name
MSC8156 Six-Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor 7
C22 SR1_IMP_CAL_RX I SXCVDD1
C23 SXPVSS1 Ground N/A
C24 SXPVDD1 Power N/A
C25 SR1_REF_CLK I SXCVDD1
C26 SR1_REF_CLK I SXCVDD1
C27 Reserved NC
C28 Reserved NC
D1 GVDD2 Power N/A
D2 VSS Ground N/A
D3 M2DQ29 I/O GVDD2
D4 GVDD2 Power N/A
D5 VSS Ground N/A
D6 M2ECC5 I/O GVDD2
D7 GVDD2 Power N/A
D8 VSS Ground N/A
D9 M2A8 OGVDD2
D10 GVDD2 Power N/A
D11 VSS Ground N/A
D12 M2A0 OGVDD2
D13 GVDD2 Power N/A
D14 VSS Ground N/A
D15 M2DQ39 I/O GVDD2
D16 GVDD2 Power N/A
D17 VSS Ground N/A
D18 M2DQ54 I/O GVDD2
D19 GVDD2 Power N/A
D20 VSS Ground N/A
D21 SXPVSS1 Ground N/A
D22 SXPVDD1 Power N/A
D23 SR1_TXD1 O SXPVDD1
D24 SR1_TXD1 O SXPVDD1
D25 SXCVSS1 Ground N/A
D26 SXCVDD1 Power N/A
D27 SR1_RXD1 I SXCVDD1
D28 SR1_RXD1 I SXCVDD1
E1 M2DQ31 I/O GVDD2
E2 M2DQ30 I/O GVDD2
E3 M2DQ27 I/O GVDD2
E4 M2ECC7 I/O GVDD2
E5 M2ECC6 I/O GVDD2
E6 M2ECC3 I/O GVDD2
E7 M2A9 OGVDD2
E8 M2A6 OGVDD2
Table 1. Signal List by Ball Number (continued)
Ball Number Signal Name1,2 Pin Type10 Power Rail
Name
MSC8156 Six-Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor8
E9 M2A3 OGVDD2
E10 M2A10 OGVDD2
E11 M2RAS OGVDD2
E12 M2A2 OGVDD2
E13 M2DQ38 I/O GVDD2
E14 M2DQS5I/O GVDD2
E15 M2DQS5 I/O GVDD2
E16 M2DQ33 I/O GVDD2
E17 M2DQ56 I/O GVDD2
E18 M2DQ57 I/O GVDD2
E19 M2DQS7I/O GVDD2
E20 Reserved NC
E21 Reserved NC
E22 Reserved NC
E23 SXPVDD1 Power N/A
E24 SXPVSS1 Ground N/A
E25 SR1_PLL_AGND9Ground SXCVSS1
E26 SR1_PLL_AVDD9Power SXCVDD1
E27 SXCVSS1 Ground N/A
E28 SXCVDD1 Power N/A
F1 VSS Ground N/A
F2 GVDD2 Power N/A
F3 M2DQ16 I/O GVDD2
F4 VSS Ground N/A
F5 GVDD2 Power N/A
F6 M2DQ17 I/O GVDD2
F7 VSS Ground N/A
F8 GVDD2 Power N/A
F9 M2BA2 OGVDD2
F10 VSS Ground N/A
F11 GVDD2 Power N/A
F12 M2A4 OGVDD2
F13 VSS Ground N/A
F14 GVDD2 Power N/A
F15 M2DQ42 I/O GVDD2
F16 VSS Ground N/A
F17 GVDD2 Power N/A
F18 M2DQ58 I/O GVDD2
F19 M2DQS7 I/O GVDD2
F20 GVDD2 Power N/A
F21 SXPVDD1 Power N/A
F22 SXPVSS1 Ground N/A
F23 SR1_TXD2/SG1_TX4O SXPVDD1
Table 1. Signal List by Ball Number (continued)
Ball Number Signal Name1,2 Pin Type10 Power Rail
Name
MSC8156 Six-Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor 9
F24 SR1_TXD2/SG1_TX4O SXPVDD1
F25 SXCVDD1 Power N/A
F26 SXCVSS1 Ground N/A
F27 SR1_RXD2/SG1_RX4I SXCVDD1
F28 SR1_RXD2/SG1_RX4I SXCVDD1
G1 M2DQS2I/O GVDD2
G2 M2DQS2 I/O GVDD2
G3 M2DQ19 I/O GVDD2
G4 M2DM2 OGVDD2
G5 M2DQ21 I/O GVDD2
G6 M2DQ22 I/O GVDD2
G7 M2CKE0 OGVDD2
G8 M2A11 OGVDD2
G9 M2A7 OGVDD2
G10 M2CK2OGVDD2
G11 M2APAR_OUT OGVDD2
G12 M2ODT1 OGVDD2
G13 M2APAR_IN IGVDD2
G14 M2DQ43 I/O GVDD2
G15 M2DM5 OGVDD2
G16 M2DQ44 I/O GVDD2
G17 M2DQ40 I/O GVDD2
G18 M2DQ59 I/O GVDD2
G19 M2DM7 OGVDD2
G20 M2DQ60 I/O GVDD2
G21 Reserved NC
G22 Reserved NC
G23 SXPVSS1 Ground N/A
G24 SXPVDD1 Power N/A
G25 SR1_IMP_CAL_TX I SXCVDD1
G26 SXCVSS1 Ground N/A
G27 Reserved NC
G28 Reserved NC
H1 GVDD2 Power N/A
H2 VSS Ground N/A
H3 M2DQ18 I/O GVDD2
H4 GVDD2 Power N/A
H5 VSS Ground N/A
H6 M2DQ20 I/O GVDD2
H7 GVDD2 Power N/A
H8 VSS Ground N/A
H9 M2A15 OGVDD2
H10 M2CK2 OGVDD2
Table 1. Signal List by Ball Number (continued)
Ball Number Signal Name1,2 Pin Type10 Power Rail
Name
MSC8156 Six-Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor10
H11 M2MDIC0 I/O GVDD2
H12 M2VREF IGVDD2
H13 M2MDIC1 I/O GVDD2
H14 M2DQ46 I/O GVDD2
H15 M2DQ47 I/O GVDD2
H16 M2DQ45 I/O GVDD2
H17 M2DQ41 I/O GVDD2
H18 M2DQ62 I/O GVDD2
H19 M2DQ63 I/O GVDD2
H20 M2DQ61 I/O GVDD2
H21 Reserved NC
H22 Reserved NC
H23 SR1_TXD3/SG2_TX4O SXPVDD1
H24 SR1_TXD3/SG2_TX4O SXPVDD1
H25 SXCVSS1 Ground N/A
H26 SXCVDD1 Power N/A
H27 SR1_RXD3/SG2_RX4I SXCVDD1
H28 SR1_RXD3/SG2_RX4I SXCVDD1
J1 M2DQS1 I/O GVDD2
J2 M2DQS1I/O GVDD2
J3 M2DQ10 I/O GVDD2
J4 M2DQ11 I/O GVDD2
J5 M2DQ14 I/O GVDD2
J6 M2DQ23 I/O GVDD2
J7 M2ODT0 OGVDD2
J8 M2A12 OGVDD2
J9 M2A14 OGVDD2
J10 VSS Ground N/A
J11 GVDD2 Power N/A
J12 VSS Ground N/A
J13 GVDD2 Power N/A
J14 VSS Ground N/A
J15 GVDD2 Power N/A
J16 VSS Ground N/A
J17 GVDD2 Power N/A
J18 VSS Ground N/A
J19 GVDD2 Power N/A
J20 Reserved NC
J21 Reserved NC
J22 Reserved NC
J23 SXPVDD1 Power N/A
J24 SXPVSS1 Ground N/A
J25 SXCVDD1 Power N/A
Table 1. Signal List by Ball Number (continued)
Ball Number Signal Name1,2 Pin Type10 Power Rail
Name
MSC8156 Six-Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor 11
J26 SXCVSS1 Ground N/A
J27 SXCVDD1 Power N/A
J28 SXCVSS1 Ground N/A
K1 VSS Ground N/A
K2 GVDD2 Power N/A
K3 M2DM1 OGVDD2
K4 VSS Ground N/A
K5 GVDD2 Power N/A
K6 M2DQ0 I/O GVDD2
K7 VSS Ground N/A
K8 GVDD2 Power N/A
K9 M2DQ5 I/O GVDD2
K10 VSS Ground N/A
K11 VDD Power N/A
K12 VSS Ground N/A
K13 VDD Power N/A
K14 VSS Ground N/A
K15 VDD Power N/A
K16 VSS Ground N/A
K17 VDD Power N/A
K18 VSS Ground N/A
K19 VDD Power N/A
K20 Reserved NC
K21 Reserved NC
K22 Reserved NC
K23 SXPVDD2 Power N/A
K24 SXPVSS2 Ground N/A
K25 SXCVDD2 Power N/A
K26 SXCVSS2 Ground N/A
K27 SXCVDD2 Power N/A
K28 SXCVSS2 Ground N/A
L1 M2DQ9 I/O GVDD2
L2 M2DQ12 I/O GVDD2
L3 M2DQ13 I/O GVDD2
L4 M2DQS0I/O GVDD2
L5 M2DQS0 I/O GVDD2
L6 M2DM0 OGVDD2
L7 M2DQ3 I/O GVDD2
L8 M2DQ2 I/O GVDD2
L9 M2DQ4 I/O GVDD2
L10 VDD Power N/A
L11 VSS Ground N/A
L12 M3VDD Power N/A
Table 1. Signal List by Ball Number (continued)
Ball Number Signal Name1,2 Pin Type10 Power Rail
Name