ST1310EHB-FREQ2 - Pericom Semiconductor Corp.

SaRonix

Voltage Controlled Crystal Oscillator

Technical Data

SaRonix

3.3 & 5V, HCMOS

141 Jefferson Drive • Menlo Park, CA 94025 • USA • 650-470-7700 • 800-227-8974 • Fax 650-462-9894

DS-162 REV D 5.2.1

S1310 / S1510 Series

Frequency Range:

ACTUAL SIZE

Description

A voltage controlled crystal oscillator

with a wide range of performance op-

tions available up to 125 MHz. This

economic part is designed for phase-

locked loop circuits commonly encoun-

tered in telecom, LAN and wireless data,

and in video processing applications.

The HCMOS output can drive both high

speed CMOS and TTL loads. The de-

vices are packaged in either standard 14-

pin or 8-pin DIP compatible all metal,

resistance welded packages for com-

mercial or industrial temperature range

applications.

32 MHz to 125 MHz

Frequency Stability: ±25 or ±50 ppm over all conditions: operating temperature,

voltage change, load change, calibration tolerance, with VC

= 2.5V @ 5V, VC = 1.65V @ 3.3V

Output Waveform

Applications & Features

•

Wide frequency range up to 125 MHz

HCMOS compatible

Full and half size standard DIP pack-

ages

Tri-state version available, see part

numbering guide for options

CMOS

TrTf

VDD

GND

0 Level

20% VDD

50% VDD

80% VDD

1 Level

SYMMETRY

Temperature Range:

Operating:

Storage:

0 to +70°C, -40 to +85°C

-55 to +125°C

Supply Voltage:

Recommended Operating: 5 V ±5% or 3.3V ±10%

Supply Current:

32 to 70 MHz:

70+ to 125 MHz:

50mA max, 35mA max @ 3.3V

65mA max, 35mA max @ 3.3V

Output Drive:

Symmetry:

Rise & Fall Times:

Logic 0:

Logic 1:

Load:

Jitter:

3.3V: 45/55% max @ 50% VDD for 0 to 70°C,

3.3V: 40/60% max @ 50% VDD for -40 to +85°C

5.0V: 45/55% max @ 50% VDD or 40/60% max @ 1.4V TTL level

4ns max: 20% to 80% VDD

1.5ns max: 0.5V to 2.5V @ 5V TTL only

0.5V max @ 5V or 20% VDD max @ 3.3V

2.5V min @ 5V or 80% VDD min @ 3.3V

5V: 5TTL or 50pF, 32 to 50 MHz

5V: 5TTL or 30pF 50+ to 125 MHz

3.3V: 30pF up to 80 MHz, 95Ω AC up to 125 MHz

20ps max RMS period jitter

MIL-STD-883, Method 2002, Condition B

MIL-STD-883, Method 2003

MIL-STD-202, Method 211, Conditions A and C

MIL-STD-883, Method 2007, Condition A

MIL-STD-202, Method 215

MIL-STD-202, Method 210, Condition A, B or C

Mechanical:

Shock:

Solderability:

Terminal Strength:

Vibration:

Solvent Resistance:

Resistance to Soldering Heat:

Environmental:

MIL-STD-883, Method 1014, Condition C

MIL-STD-883, Method 1014, Condition A2

MIL-STD-883, Method 1011, Condition A

MIL-STD-883, Method 1004

Gross Leak Test:

Fine Leak Test:

Thermal Shock:

Moisture Resistance:

Pull Characteristics:

Input Impedance:

Frequency Response (-3dB):

Pullability:

Control Voltage:

Transfer Function:

Linearity:

Center Control Voltage:

50KΩ min

50 kHz min

±25, ±50, ±75, ±100 ppm APR*

0.5 to 4.5 V @ 5V or 0.3 to 3.0V @ 3.3V

Frequency increases when Control Voltage increases

5% or 10% max

2.5V @ 5V, 1.65V @ 3.3V

* APR = (VCXO Pull relative to specified Output Frequency) – (VCXO Frequency Stability)

Aging: @ 40°C: ±10 ppm max for 5 years or ±12 ppm max for 10 years

SaRonix

S1310 / S1510 Series

SaRonix

Voltage Controlled Crystal Oscillator

Technical Data

3.3 & 5V, HCMOS

141 Jefferson Drive • Menlo Park, CA 94025 • USA • 650-470-7700 • 800-227-8974 • Fax 650-462-9894

DS-162 REV D 5.2.2

All specifications are subject to change without notice.

inches

Package Details Part Numbering Guide

5.08

.200 max

.46±.08

.018±.003

0.91

.036 max

7.62±.20

.300±.008

120°

120° 120°

7.62±.20

.300±.008

1.5

.059

Pin 5

Output

Pin 8

VDD

Pin 1

Control Voltage

Pin 4

GND Case (VSS)

Scale: None (Dimensions in )

SARONIX

Denotes Pin 1

Pin 3 Input

Logic 1 or NC

Logic 0 or GND

Pin 8 Output

Oscillation

High Impedance

Required Input Levels on Pin 3:

Logic 1 = 3.0 V min

Logic 0 = 0.3V max

S T 151 0 A A B J - 60.0000

SaRonix Frequency (MHz)

T = Tri-State

optional: full size 3.3 or 5V

standard: 1/2 size 5V

not available: 1/2 size 3.3V

Blank = Non Tri-State

Linearity

A = 5%

B = 10%

POWER

SUPPLY

HALF SIZE PACKAGE

SARONIX

VCXO

Denotes Pin 1

12.2±.13

.480±.005

Pin 3

Pin 1

Pin 7

4.57±.13

.18±.005

7.62±.13

.300±.005

Pin 12

Pin 14

15.24±.13

.600±.005

5.08

.200 max

4.85±.25

.191±.01

3.94±.25

.155±.010 .46±.05

.018±.002

FULL SIZE PACKAGE

CONTROL VOLTAGE

CL = 30pF or 50pF

(Note A)

GND

OSCILLATOR

VDD OUT

Pin 7 (4)

Pin 14 (8) Pin 8 (5)

Pin 1 (1)

V M

CONTROL VOLTAGE

NOTE A: CL includes probe and fixture capacitance

( ) Indicates pin numbers for half size package

Figure 2 – TTL load Test Circuit

Pin 14 (8) Pin 8 (5)

Pin 1 (1)

Pin 7 (4)

OSCILLATOR

GND

N/C

OUTVDD

V M

POWER

SUPPLY

CL = 15pF

(Note A)

MMDB7000

or Equiv

RL = 780

Ω

Pullability (minimum APR)

A = ±50 ppm

B = ±100 ppm

G = ±25 ppm

H = ±75 ppm

TEST

POINT

TEST

POINT

A = ±25 ppm, 0 to 70°C

B = ±50 ppm, 0 to 70°C

E = ±50 ppm, -40 to +85°C

Stability Tolerance

Series

131 = 3.3V, HCMOS/TTL VCXO

151 = 5V, HCMOS/TTL VCXO

Model

0 = Full size package

9 = Half size package

NOTE A: CL includes probe and fixture capacitance (50pF max 32 to 50 MHz, 30pF max 50+ to 125 MHz)

( ) Indicates pin numbers for half size package

Figure 1 – 30pF or 50pF load Test Circuit

21.0

.825 max

0.91

.036

13.0

.510

max

Tri-State Logic Table

Test Circuits

(4) Glass

Insulators Pin 8

Pin Function:

Pin 8: Output

Pin 12: N/C

(Tri-State version only)

Pin 14: VDC (VDD)

Pin 1: Control Voltage

Pin 3: Tri-State control

(Tri-State version only)

Pin 7: GND / Case (VSS)

Standard Marking Format

Includes Date Code, Frequency & Model

13.0

.510 max

10.87

.428 max

6.86

.270

13.0

.510

max

6.0

.236

1.5

.059

Standard Marking Format

Includes Date Code, Frequency & Model

Lead Style

Blank = Thru-Hole

J = Gull Wing