© 2005 Fairchild Semiconductor Corporation DS500167 www.fairchildsemi.com
June 1999
Revised April 2005
74VCX245 Low Voltage Bidirecti onal Transceiver with 3.6V Tolerant Inputs and Output s
74VCX245
Low Voltage Bidirecti onal Transceiver
with 3.6V Tolerant Inputs and Outputs
General Descript ion
The VCX245 contains eight non-inverting bidirectional buff-
ers with 3-STATE out puts and is intended for bus or iented
applications. The T/R input determines the direction of data
flow. The OE input disables both the A and B ports by plac-
ing them in a high impedance state.
The 74VCX245 is designed for low voltage (1.4V to 3.6V)
VCC applications with I/O compatibility up to 3.6V.
The 74VCX245 is fabricated with an advanced CMOS
technology to achieve high-speed operation while main-
taining low CMOS power dissipation.
Features
■1.4V to 3.6V VCC supply operatio n
■3.6V tolerant inputs and out puts
■Power-off high impedance inputs and outputs
■Supports Live Insertion and Withdrawal (Note 1)
■tPD
3.5 ns max for 3.0V to 3.6V VCC
■Static Drive (IOH/IOL)
r
24 mA @ 3.0V VCC
circuitry
■Latchup performance exceeds 300 mA
■ESD performa nce :
Human bod y mode l
!
2000V
Machine model
!
200V
■Leadless DQFN Pb-Free package
Note 1: To ensure the high impedance state during power up and power
down, O En sh ould be tied to VCC throug h a p ull up r esistor. The m inimu m
value of the resist or is de term ined b y the cu rre nt so urcin g capab ility o f t he
driver.
Ordering Code:
Pb-Free package per JEDEC J-STD-020B.
Note 2: Devices also available in Tape and Re el. Specify by appending the suffix let te r “X” to the or dering code.
Note 3: DQFN packag e av ailable in Tape and Reel only,
Logic Symbol Pin Descriptions
Order Number Package
Number Package Description
74VCX245WM
(Note 2) M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74VCX245BQX
(Note 3) MLP020B Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 4.5mm
74VCX245MTC
(Note 2) MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Nam es Description
OE Output Enable Input (Active LOW)
T/R Transmit/Receive Input
A0–A7Side A Inp uts or 3-STATE Outputs
B0–B7Side B Inp uts or 3-STATE Outputs
■Uses proprietary noise /E MI reduct ion
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74VCX245
Connection Diagrams
Pin Assignments for SOIC and TSSOP
Pin Assignment for DQFN
(Top Through View)
Truth Table
H
HIGH Voltage Lev el
L
LOW Voltage Level
X
Immaterial
Z
High Impedance
Note 4: Unused bus terminals during HIGH Z State must be held HIGH or
LOW.
Logic Diagram
Inputs Outputs
OE T/R
LLBus B
0–B7 Data to Bus A0–A7
LHBus A
0–A7 Data to Bus B0–B7
H X HIGH Z State on A0–A7, B0–B7 (Note 4)
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74VCX245
Absolute Maximum Ratings(Note 5) Recommended Operating
Conditions (Note 7)
Note 5: The Absolute Maximum Ratings are those values beyond which
the saf ety of the device cannot be guarante ed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tio ns f or actual device op eration.
Note 6: IO Absolute Maximum Rating must be observed.
Note 7: Floa t ing or unus ed inputs must be hel d HIGH or LOW.
DC Electrical Characteristics
Supply Voltage (VCC)
0.5V to
4.6V
DC Input Voltage (VI)
0.5V to
4.6V
DC Output Voltage (VO)
Outputs 3-STATE
0.5V to
4.6V
Outputs Active (Note 6)
0.5V to VCC
0.5V
DC Input Diode Current (IIK) VI
0V
50 mA
DC Output Diode Current (IOK)
V
O
0V
50 mA
V
O
!
VCC
50 mA
DC Output Source/Sink Current
(IOH/IOL)
r
50 mA
DC VCC or Ground Current
r
100 mA
Storage Temperature (TSTG)
65
q
C to
150
q
C
Power Supply
Operating 1.4V to 3.6V
Input Voltage
0.3V to 3.6V
Output Voltage (VO)
Output in Active St ates 0V to VCC
Output in 3-STATE 0V to 3.6V
Output Current in IOH/IOL
VCC
3.0V to 3.6V
r
24 mA
VCC
2.3V to 2.7V
r
18 mA
VCC
1.65V to 2.3V
r
6 mA
VCC
1.4V to 1.6V
r
2 mA
Free Air Operating Temperature (TA)
40
q
C to
85
q
C
Minimum Input Edge Rate (
'
t/
'
V)
V
IN
0.8V to 2.0V, VCC
3.0V 10 ns/V
Symbol Parameter Conditions VCC Min Max Units
(V)
VIH HIGH Level Input Voltage 2.7 to 3.6 2.0
V
2.3 to 2.7 1.6
1.65 to 2.3 0.65
u
VCC
1.4 to 1.6 0.65
u
VCC
VIL LOW Level Input Voltage 2.7 to 3.6 0.8
V
2.3 to 2.7 0.7
1.65 to 2.3 0.35
u
VCC
1.4 to 1.6 0.35
u
VCC
VOH HIGH Level Output Voltage IOH
100
P
A 2.7 to 3.6 VCC
0.2
V
IOH
12 mA 2.7 2.2
IOH
18 mA 3.0 2.4
IOH
24 mA 3.0 2.2
IOH
100
P
A 2.3 to 2.7 VCC
0.2
IOH
6 mA 2.3 2.0
IOH
12 mA 2.3 1.8
IOH
18 mA 2.3 1.7
IOH
100
P
A 1.65 to 2.3 VCC
0.2
IOH
6 mA 1.65 1.25
IOH
100
P
A 1.4 to 1.6 VCC
0.2
IOH
2 mA 1.4 1.05
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74VCX245
DC Electrical Characteristics (Continued)
Note 8: Outputs disabled or 3-STATE only.
AC Electrical Characteristics (Note 9)
Note 9: For CL
50PF, add app roximat ely 300 ps to the AC m aximum specif ic at ion.
Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specif ic ation ap plies to an y o ut puts switch ing in the same direc t ion, either HIGH-to- LOW (tOSHL) or LO W-to-HIGH (t OSLH).
Symbol Parameter Conditions VCC Min Max Units
(V)
VOL LOW Level Output Voltage IOL
100
P
A 2.7 to 3.6 0.2
V
IOL
12 mA 2.7 0.4
IOL
18 mA 3.0 0.4
IOL
24 mA 3.0 0.55
IOL
100
P
A 2.3 to 2.7 0.2
IOL
12 mA 2.3 0.4
IOL
18 mA 2.3 0.6
IOL
100
P
A 1.65 to 2.3 0.2
IOL
6 mA 1.65 0.3
IOL
100
P
A 1.4 to 1.6 0.2
IOL
2 mA 1.4 0.35
IIInput Leakage Current 0
d
VI
d
3.6V 1.4 to 3.6
r
5.0
P
A
IOZ 3-STATE Output Leakage 0
d
VO
d
3.6V 1.4 to 3.6
r
10
P
A
VI
VIH or VIL
IOFFI Power-OFF Leakage Current 0
d
(VI, VO)
d
3.6V 0 10
P
A
ICC Quiescent Supply Current VI
VCC or GND 1.4 to 3.6 20
P
A
VCC
d
(VI, VO)
d
3.6V (Note 8) 1.4 to 3.6
r
20
'
ICC Increase in ICC per Input VIH
VCC
0.6V 2.7 to 3.6 750
P
A
Symbol Parameter Conditions VCC TA
40
q
C to
85
q
C Units Figure
(V) Min Max Number
tPHL, tPLH Propagation Delay CL
30 pF, RL
500
:
3.3
r
0.3 0.6 3.5
ns
Figures
1, 2
An to Bn or Bn to An2.5
r
0.2 0.8 4.2
1.8
r
0.15 1.5 8.4
CL
15 pF, RL
2k
:
1.5
r
0.1 1.0 16.8 Figures
5, 6
tPZL, tPZH Output Enable Time CL
30 pF, RL
500
:
3.3
r
0.3 0.6 4.5
ns
Figures
1, 3, 4
2.5
r
0.2 0.8 5.6
1.8
r
0.15 1.5 9.8
CL
15 pF, RL
2k
:
1.5
r
0.1 1.0 19.6 Figures
5, 7, 8
tPLZ, tPHZ Output Disable Time CL
30 pF, RL
500
:
3.3
r
0.3 0.6 3.6
ns
Figures
1, 3, 4
2.5
r
0.2 0.8 4.0
1.8
r
0.15 1.5 7.2
CL
15 pF, RL
2k
:
1.5
r
0.1 1.0 14.4 Figures
5, 7, 8
tOSHL Output to Output Skew CL
30 pF, RL
500
:
3.3
r
0.3 0.5
ns
tOSLH (Note 10) 2.5
r
0.2 0.5
1.8
r
0.15 0.75
CL
15 pF, RL
2k
:
1.5
r
0.1 1.5
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74VCX245
Dynamic Switching Characteristics
Capacitance
Symbol Parameter Conditions VCC
(V)
TA
25
q
CUnits
Typical
VOLP Quiet Output Dynamic Peak VOL CL
30 pF, VIH
VCC, VIL
0V 1.8 0.3 V2.5 0.7
3.3 1.0
VOLV Quiet Output Dynamic Valley VOL CL
30 pF, VIH
VCC, V IL
0V 1.8
0.3 V2.5
0.7
3.3
1.0
VOHV Quiet Output Dynamic Va lley VOH CL
30 pF, VIH
VCC, V IL
0V 1.8 1.3 V2.5 1.7
3.3 2.0
Symbol Parameter Conditions TA
25
q
CUnits
Typical
CIN Input Capaci tance VI
0V or VCC, VCC
1.8V, 2.5V or 3.3V 6.0 pF
CI/O Input/Output Capacitance VI
0V or VCC, VCC
1.8V, 2.5V or 3.3V 7.0 pF
CPD Power Dissipation Capacitanc e VI
0V or VCC, f
10 MHz, VCC
1.8V, 2.5V or 3.3V 20.0 pF
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74VCX245
AC Loading and Waveforms (VCC 3.3 V r 0.3V to 1.8V r 0.15V)
FIGURE 1. AC Test Circuit
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Log ic
TEST SWITCH
tPLH, tPHL Open
tPZL, tPLZ 6V at VCC
3.3V
r
0.3V;
VCC x 2 at VCC
2.5V
r
0.2V; 1.8V
r
0.15V
tPZH, tPHZ GND
Symbol VCC
3.3V
r
0.3V 2.5V
r
0.2V 1.8V
r
0.15V
Vmi 1.5V VCC/2 VCC/2
Vmo 1.5V VCC/2 VCC/2
VXVOL
0.3V VOL
0.15V VOL
0.15V
VYVOH
0.3V VOH
0.15V VOH
0.15V
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74VCX245
AC Loading and Waveforms (VCC 1.5 r 0.1V)
FIGURE 5. AC Test Circuit
FIGURE 6. Waveform for Inverting and Non-Inverting Functions
FIGURE 7. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 8. 3-STATE Output Low Enable and Disable Times for Lo w Voltage Logic
TEST SWITCH
tPLH, tPHL Open
tPZL, tPLZ VCC x 2 at VCC
1.5V
r
0.1V
tPZH, tPHZ GND
Symbol VCC
1.5V
r
0.1V
Vmi VCC/2
Vmo VCC/2
VXVOL
0.1V
VYVOH
0.1V
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74VCX245
Tape and Reel Specification
Tape Format for DQ FN
TAPE DIMENSIONS inches (millimeters)
REEL DIMENSIONS inches (millimeters)
Package Tape Number Cavity Cover Tape
Designator Section Cavities Status Status
Leader (Start End) 125 (typ) Empty Sealed
BQX Carrier 3000 Filled Sealed
Trailer (Hub End) 75 (typ) Empty Sealed
Tape SizeABCDNW1W2
12 mm 13.0 0.059 0.512 0.795 2.165 0.488 0.724
(330.0) (1.50) (13.00) (20.20) (55.00) (12.4) (18.4)
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74VCX245
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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74VCX245
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm
Packag e Num b er MLP02 0B
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74VCX245 Low Voltage Bidirecti onal Transceiver with 3.6V Tolerant Input s and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide
Package Number MTC20
Fairchild does not assum e any responsibility for use of any circuitry des cribe d, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r syst ems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instruct ions fo r use provided in the l abe li ng, can be re a-
sonably expected to result in a significant injury to the
user.
2. A crit ical com ponen t in any com ponen t of a life s uppor t
device or system whose failure to perform can be rea-
sonabl y e xpec ted to cause th e fa i lure of the l ife suppor t
device or system, or to affect its safety or effectiveness.
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