A62500116W - Swatch Group - Datasheet.Directory

R

A6250

1

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High Efficiency Linear Power Supply with

Power Surveillance and Software Monitoring

Description

The A6250 offers a high level of integration by combining

voltage regulation, voltage monitoring and software

monitoring in a 16 lead package. The voltage regulator has

a low dropout voltage (typ. 260 mV at 250 mA) and a low

quiescent current (1 75 µA). The quiesce nt current increase s

only slightly in dropout prolonging battery life. Built-in

protection includes a positive transient absorber for up to

60V (load dump) and the ability to survive an unregulated

input voltage of –20 V (reverse battery). The input may be

connected to ground or a reverse voltage without reverse

current flow from the output to the input. A comparator

monitors the voltage applied at the V

IN

input comparing it

with an internal 1.52 V reference. The power-on reset

function is initialized after V

IN

reaches 1.52 V and takes the

reset output inactive after T

POR

depending of external

resistance. The reset output goes active low when the V

IN

voltage is less than 1.52 V. The

RES and EN outputs are

guaranteed to be in a correct state for a regulated output

voltage as low as 1.2 V. The watchdog function monitors

software cycle time and execution. If software clears the

watchdog too quickly (incorrect cycle time) or too slowly

(incorrect execution) it will cause the system to be reset.

The system enable output prevents critical control functions

being activated until software has successfully cleared the

watchdog three times. Such a security could be used to

prevent motor controls being energized on repeated resets

of a faulty system.

Features



Highly accurate 5 V, 250 mA guaranteed output



Low dropout voltage, t ypicall y 260 mV at 250 mA



Low quiescent current, typicall y 175

µ

A



Standby mode, maximum current 340

µ

A (with 100

µ

A

load on OUTPUT )



Unregulated DC input can withstand –20 V reverse

battery and + 60 V power transients



Fully operational for unregulated DC input voltage up to

40 V and regulated out put voltage down to 3.0 V



Reset output guaranteed for regulated output voltage

down to 1.2 V



No reverse output current



Very low temperature coefficient for the regulated output



Current limiting



Comparator for voltage monitoring, voltage reference

1.52 V



Programmable reset voltage monitoring



Programmable power on reset (POR ) delay



Watchdog with programmable time windows guarantees

a minimum time and a maxim um time between software

clearing of the watchdog



Time base accuracy

±

10%



System enable output offers added security



TTL/CMOS compatible



-40 to +125

°

C temperature range



PSOP2-16 package

Applications



Industrial electronics



Cellular telephones



Security systems



Battery powered products



High efficiency linear power supplies



Automotive electronics

Typical Operating Configuration

5V

+

V

SS

GND

Unregulated

Voltage INPUT OUTPUT

R

A6250

RES

EN

TCL

V

IN

Fig. 1

Pin Assignment

VSS

R

PSOP2-16

OUTPUT

INPUT

RES

EN

TCL

VIN

A6250

NC

NC NC

NC

Fig. 2

EM MICROELECTRONIC -

MARIN SA

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A6250

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Absolute Maximum Ratings

Parameter Symbol Conditions

Continuous voltage at INPUT

to V

SS

V

INPUT

- 0.3 to + 45V

Transients on INPUT for

t < 100 ms and duty cycle 1% V

TRANS

up to + 60V

Reverse supply voltage on

INPUT V

REV

- 20 V

Max. voltage at any sign al pin V

MAX

OUTPUT + 0.3V

Min. voltage at any signal pin V

MIN

V

SS

– 0.3V

Storage temperature T

STO

- 65 to + 150

°

C

Operating junction

temperature T

J

max. 150 °C

Electrostatic discharge max.

to MIL-STD-883C method

3015.7 with ref. to V

SS

V

Smax

1000V

Max. soldering conditions T

Smax

250

°

C x 10s

Max. output current I

OUTPUTmax

300mA

Table 1

Stresses above these listed maximum ratings may cause

permanent damages to the device. Exposure beyond

specified operat ing conditions may affect devic e reliability or

cause malfunction.

Decoupling Methods

The input capacitor is necessary to compensate the line

influences. A resistor of approx. 1

Ω

connected in series

with the input capacitor may be used to dam p the oscillation

of the input capacitor and input inductivity. The ESR value

of the capacitor plays a major role reg arding the efficiency of

the decoupling. It is recommended also to connect a

ceramic capacitor (100 nF) directly at the IC's pins. In

general the user must assure that pulses on the input line

have slew rates lower than 1 V/µs. On the output side, the

capacitor is necessary for the stability of the regulation

circuit. The stability is guaranteed for values of 22 µF or

bigger. It is especially important to choose a capacitor with

a low ESR value. Tantal capacitors are recommended.

See the notes related to Table 2. Special care must be

taken in disturbed environments (automotive, proximity of

motors and relays, etc.).

Handling Procedures

This device has built-in protection against high static

voltages or electric fields; however, it is adv ised that normal

precautions be taken as for any other CMOS component.

Unless otherwise specifie d, proper operation can only occur

when all terminal voltages are kept within the voltage range.

Unused inputs must always be tied to a defined logic

voltage level.

Operating Conditions

Parameter Symbol Min. Max. Units

Operating junction

temperature

1)

T

J

-40 +125

°

C

INPUT voltage

2)

V

INPUT

2.3 40 V

OUTPUT voltage

2)3)

V

OUTPUT

1.2 V

RES &

EN

guaranteed

4)

V

OUTPUT

1.2 V

OUTPUT current

5)

I

OUTPUT

250 mA

Comparator input voltage V

IN

0 V

OUTPUT

V

RC-oscillator programming

6)

R 10 1000 k

Ω

Thermal resistance from

junction to ambient

7)

- PSOP2-16 R

th(j-a)

30 90

°

C/W

Table 2

1)

The maximum operating temperature is confirmed by

sampling at initial device qualification. In production, all

devices are tested at +125

°

C.

2)

Full operation guaranteed. To achieve the load regulation

specified in Table 3 a 22

µ

F capacitor or greater is

required on the INPUT, see Fig. 8. The 22

µ

F must have

an effective resistance

≤

5

Ω

and a resonant frequency

above 500 kHz.

3)

A 10

µ

F load capacitor and a 100 nF dec oupling capac itor

are required on the regulator OUTPUT for stability. The

10

µ

F must have an effective series resistance of

≤

5

Ω

and a resonant frequency above 500 kHz.

4)

RES must be pulled up externally to V

OUTPUT

even if it is

unused. (Note: RES and

EN

are used as inputs by EM

test).

5)

The OUTPUT current will not apply for all possible

combinations of input voltage and output current.

Combinations that would require the A6250 to work above

the maximum junction temperature (+125

°

C) must be

avoided.

6)

Resistor values close to 1000 k

Ω

are not recommended

for applications working at 125 °C.

7)

The thermal resistance specified assumes the package is

soldered to a PCB. The thermal resistance's value

depends on the PCB's structure. A typical value of 51

°C/W has been obtained with a dual layer board, with the

slug soldered to the heat-sink area of the PCB (see Fig.

22).

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A6250

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Electrical Characteristics

V

INPUT

= 6.0 V, C

L

= 10

µ

F + 100 nF, C

INPUT

= 22

µ

F, T

J

= -40 to +125

°

C, unless otherwise specified

Parameter Symbol Test Conditions Min. Typ. Max. Unit

Supply current in standby mode I

SS

R

EXT

= don’t care, TCL = V

OUTPUT

,

V

IN

= 0 V, I

L

= 100

µ

A 140 340

µ

A

Supply current

1)

I

SS

R

EXT

= 100 k

Ω

, I/P

S

at V

OUTPUT

,

O/P

S

1 M

Ω

to V

OUTPUT

, I

L

= 100

µ

A 175 400

µ

A

Supply current

1)

I

SS

R

EXT

= 100 k

Ω

, I/P

S

at V

OUTPUT

,

V

INPUT

=8.0 V, O/P

S

1 M

Ω

to V

OUTPUT

,

I

L

= 100 mA

1.7

4.2

mA

I

L

= 250 mA 7 15 mA

Output voltage V

OUTPUT

I

L

= 100

µ

A 4.85 5.15 V

Output voltage V

OUTPUT

100

µ

A

≤

I

L

≤

250 mA, 4.85 5.15 V

Output voltage temperature

coefficient

2)

V

th(coeff)

100 ppm/

°

C

Line regulation

3)

V

LINE

6 V

≤

V

INPUT

≤

35 V, I

L

= 1 mA, T

J

= +125

°

C 0.2 0.8 %

Load regulation

3)

V

L

100

µ

A

≤

I

L

≤

100 mA 0.2 0.7 %

Load regulation

3)

V

L

5 mA

≤

I

L

≤

250 mA 0.9 1.45 %

Dropout voltage

4)

V

DROPOUT

I

L

= 100

µ

A 40 170 mV

Dropout voltage

4)

V

DROPOUT

I

L

= 100 mA 160 380

5)

mV

Dropout voltage

4)

V

DROPOUT

I

L

= 250 mA 260 650 mV

Dropout supply current I

SS

V

INPUT

= 4.5 V, I

L

= 100

µ

A,

R

EXT

= 100 k

Ω

, O/P

S

1 M

Ω

to

V

OUTPUT

, I/P

S

at V

OUTPUT

1.2 1.8 mA

Current limit I

Lmax

OUTPUT tied to V

SS

450 mA

OUTPUT noise , 10Hz to 100kHz V

NOISE

200

µ

V rms

4.5

≤

V

OUTPUT

≤

5.5 V, I

L

= 100 µA, C

L

= 10

µ

F + 100 nF, C

INPUT

= 22

µ

F, T

J

= -40 to +125

°

C, unless otherwise specified

RES &

EN

Output Low Voltage V

OL

V

OUTPUT

= 4.5 V, I

OL

= 20 mA 0.4 V

V

OL

V

OUTPUT

= 4.5 V, I

OL

= 8 mA 0.2 0.4 V

V

OL

V

OUTPUT

= 2.0 V, I

OL

= 4 mA 0.2 0.4 V

V

OL

V

OUTPUT

= 1.2 V, I

OL

= 0.5 mA 0.06 0.2 V

EN

Output High Voltage V

OH

V

OUTPUT

= 4.5 V, I

OH

= -1 mA 3.5 4.1 V

V

OH

V

OUTPUT

= 2.0 V, I

OH

= -100

µ

A 1.8 1.9 V

V

OH

V

OUTPUT

= 1.2 V, I

OH

= -30

µ

A 1.0 1.1 V

TCLand V

IN

TCL Input Low Level V

IL

V

SS

0.8 V

TCL Input High Lev el V

IH

2.0 V

OUTPUT

V

Leakage current TCL input I

LI

V

SS

≤

V

TCL

≤

V

OUTPUT

0.05 1

µ

A

V

IN

input resistance R

VIN

100 M

Ω

Comparator reference

6)7)

V

REF

T

J

= +25

°

C 1.474 1.52 1.566 V

V

REF

1.436 1.620 V

V

REF

-40

°

C

≤

T

J

≤

+125

°

C 1.420 1.620 V

Comparator hysteresis

7)

V

HY

2 mV

Table 3

1)

If INPUT is connected to V

SS

, no reverse current will flow from the OUTPUT to th e INPUT, however the supply current specified will be sank

by the OUTPUT to supply the A6250.

2)

The OUTPUT voltage temperature coefficient is defined as the worst case voltage change divided by the total temperature range.

3)

Regulation is measured at constant junction temperature using pulse testing with a low duty cycle. Changes in OUTPUT voltage due to

heating effects are covered in the specification for thermal regulation.

4)

The dropout voltage is defined as the INPUT to OUTPUT differential, measured with the input voltage equal to 5.0 V.

5)

Not

tested

6)

The comparator and the voltage regulator have separate voltage references (see “Block Diagram” Fig. 7).

7)

The comparator reference is the po wer-down reset threshold. The power-on reset t hreshold equals the comparator reference voltage plus the

comparator hysteresis (see Fig. 4).

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A6250

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Timing Characteristics

V

INPUT

= 6.0 V, I

L

= 100

µ

A, C

L

= 10

µ

F + 100 nF, C

INPUT

= 22

µ

F, T

J

= -40 to + 125

°

C, unless otherwise specified

Parameter Symbol Test Conditions Min. Typ. Max. Units

Propagation delays:

TCL to Output Pins T

DIDO

250 500 ns

V

IN

sensitivity T

SEN

1 5 20

µ

s

Logic Transition T imes on all O utput Pins T

TR

Load 10 k

Ω

, 50 pF 30 100 ns

Power-on Reset delay T

POR

R

EXT

= 123 k

Ω

±

1% 90 100 110 ms

Watchdog Time T

WD

R

EXT

= 123 k

Ω

±

1% 90 100 110 ms

Open Windo w Percentage OWP

±

0.2 T

WD

Closed Window Time T

CW

0.8 T

WD

T

CW

R

EXT

= 123 k

Ω

±

1% 72 80 88 ms

Open Windo w Time T

OW

0.4 T

WD

T

OW

R

EXT

= 123 k

Ω

±

1% 36 40 44 ms

Watchdog Reset Pulse T

WDR

T

WD

/40

T

WDR

R

EXT

= 123 k

Ω

±

1% 2.5 ms

T

CL

Input Pulse Width T

TCL

150 ns

Table 4

Timing Waveforms

Watchdog Timeout Period

T

CW

- closed window

Watchdog

timer reset

Condition:

R

EXT

= 123 kΩ

+ OWP

+ 20%

80

100

120

t [ms]

T

WD

= T

POR

- OWP

- 20%

T

OW

- open window

Fig. 3

Voltage Monitoring

Fig. 4

T

SEN

T

SEN

T

SEN

T

SEN

T

POR

T

POR

RES

V

IN

V

REF

V

HY

Conditions:

V

OUTPUT

≥

3 V

No timeout

Fig. 4

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A6250

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Timer Reaction

Fig. 5

Combined Voltage and Timer Reaction

Fig. 6

Block Diagram

RES

EN

TCL

Voltage

Regulator

Voltage

Reference

Voltage

Reference

Current

Controlled

Oscillator

-

+

VREF Comparator Reset

Control

Timer

Enable

Logic

INPUT

VIN

R

OUTPUT

Open drain

output RES

Fig. 7

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A6250

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Pin Description

Pin Name Function

2

EN

Push-pull active low enable o utput

3 RES Open drain active low reset output.

RES must be pulled up to V

OUTPUT

even if unused

4 TCL Watchdog timer clear input signal

5 V

SS

GND terminal

12 INPUT Voltag e reg ulator input

13 OUTPUT Voltag e regulator output

14 R R

EXT

input for RC oscillator tuning

15 V

IN

Voltage comparator input

Table 5

Functional Description

Voltage Regulator

The A6250 has a 5 V

±

2%, 250 mA, low dropout voltage

regulator. The low supply current (typ.155

µ

A) makes the

A6250 particularly suited to automotive systems then remain

energized 24 hours a day. The input voltage range is 2.3 V

to 40 V for operation and the input protection includes both

reverse battery (20 V below ground) and load dump

(positive transients up to 60 V). There is no reverse current

flow from the OUTPUT to the INPUT when the INPUT

equals V

SS

. This feature is important for systems which

need to implement (with capacitance) a minimum power

supply hold-up time in th e event of po wer failure. T o achiev e

good load regulation a 22

µ

F capacitor (or greater) is

needed on the INPUT (see Fig. 8). Tantalum or aluminium

electrolytics are adequat e for the 22

µ

F capacitor; film types

will work but are relatively expensive. Many aluminium

electrolytics have electrolytes that freeze at about –30

°

C,

so tantalums are recommen ded for operation belo w –25

°

C.

The important parameters of the 22

µ

F capacitor are an

effective series resistance of

≤

5

Ω

and a resonant

frequency above 500 kHz.

A 10

µ

F capacitor (or greater) and a 100 nF capacitor are

required on the OUTPUT to prevent oscillations due to

instability. The specification of the 10

µ

F capacitor is as per

the 22

µ

F capacitor on the INPUT (see previous paragraph).

The A6250 will remain stable and in regulation with no

external load a nd the drop out volt age is t ypic ally co nstant a s

the input voltage fall to below its minimum level (see Table

2). These features are especially important in CMOS RAM

keep-alive appl icatio ns.

Care must be taken not to exceed the maximum junction

temperature (+ 125

°

C). The power dissipation within the

A6250 is given by the formula:

P

TOTAL

= (V

INPUT

– V

OUTPUT

) * I

OUTPUT

+ (V

INPUT

) * I

SS

The maximum continuous power dissipation at a given

temperature can be calculated using the formula:

P

MAX

= ( 125

°

C – T

A

) / R

th(j-a)

where R

th(j-a)

is the thermal resistance from the junction to

the ambient and is specified in Table 2. Note the R

th(j-a)

given in Table 2 assumes that the package is soldered to a

PCB. The above formula for maximum power dissipation

assumes a constant load (ie.

≥

100 s). The transient thermal

resistance for a single pulse is much lower than the

continuous value.

V

IN

Monitoring

The power-on reset and the power-down reset are

generated as a response to the external voltage level

applied on the V

IN

input. The external voltage level is

typically obtain ed from a voltage divider

as shown on Fig. 8.

The user uses the external vo ltage divider to set the desire d

threshold level for power-on reset and power-down reset in

his system. The internal comparator reference voltage is

typically 1.52 V.

At power-up the reset output (RES ) is held lo w (see Fig. 4).

After INPUT reaches 3.36 V (and so OUTPUT reaches at

least 3 V) and V

IN

becomes greater than V

REF

, the RES

output is held low for an additional power-on-reset (POR)

delay which is equ al to the watchdog time T

WD

(typically 10 0

ms with an external resistor of 123 k

Ω

connected at R pin).

The POR delay prevents repeated toggling of RES even if

V

IN

and the INPUT voltage drops out and recovers. The

POR delay allows the microprocessor’s crystal oscillator

time to start and stabiliz e and ensures correc t recognition of

the reset signal to the microprocessor.

The RES output goes active low generating the power-

down reset whenev er V

IN

falls belo w V

REF

. The sensitiv ity or

reaction time of the internal c omparator to the vol-tage level

on V

IN

is typically 5

µ

s.

Timer Programming

The on-chip oscillator with an external resistor R

EXT

connected between the R pin and V

SS

(see Fig. 8) allows

the user to adjust the power-on reset (POR) delay,

watchdog time T

WD

and with this also the closed and open

time windows as well as the watchdog reset pulse width

(T

WD

/40).

With R

EXT

= 123 k

Ω

typical values are:

-Power-on reset delay: T

POR

is 100 ms

-Watchdog time: T

WD

is 100 ms

-Closed window: T

CW

is 80 ms

-Open window: T

OW

is 40 ms

-Watchdog reset: T

WDR

is 2.5 ms

Note the current consumption increases as the frequency

increases.

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A6250

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Watchdog Timeout Period Desc r iption

The watchdog timeout period is divided into two parts, a

“closed” window and an “open” window (see Fig. 3) and is

defined by two parameters, T

WD

and the Open Window

Percentage (OWP).

The closed window starts just after the watchdog timer

resets and is defined by T

CW

= T

WD

– OWP(T

WD

).

The open window starts after the closed time window

finishes and lasts till T

WD

+ OWP(T

WD

).The open window

time is defined by T

OW

= 2 x OWP (T

WD

)

26 ms at +25°C

a) (26 - 10% = 23.4 ms) (26 + 10% = 28.6 ms) a)

b) (23.4 - 5% = 22.2 ms) (28.6 + 5% = 30.0 ms) b)

min.: (30.0 - 20% = 24.0 ms) max.: (22.2 + 20% = 26.7 ms)

Typical TCL period of

(24.0 + 26.7) / 2 = 25.4 ms

For example if T

WD

= 100 ms (actual value) and OWP =

±

20% this means the closed window lasts during first the

80 ms (T

CW

= 80 ms = 100ms – 0.2 (100 m s)) and the open

window the next 40 ms (T

OW

= 2 x 0.2 (100 ms) = 40 ms).

The watchdog can be serviced between 80 ms and 120 ms

after the timer reset. However as the time base is

±

10%

accurate, software must use t he following calculation as the

limits for servicing signal TCL during the o pen window:

Related to curves (F ig. 10 to Fig. 20), espec ially Fig. 19 and

Fig. 20, the relation between T

WD

and R

EXT

could easily be

defined. Let us take an example describing the variations

due to production and temperature:

1. Choice, T

WD

= 26 ms.

2. Relat ed to Fig. 20, the coefficient (T

WD

to R

EXT

) is 1.125

where R

EXT

is in k

Ω

and T

WD

in ms.

3. R

EXT

(typ.) = 26 x 1.155 = 30.0 k

Ω

.

4. The ratio between T

WD

= 26 ms and the ( TCL period)

= 25.4 ms is 0.975.

Then the relation over the production and the full

temperature range is,

TCL period = 0.975 x T

WD

0.975 x R

EXT

or

TCL period =

1.155

R x 0.975

EXT

, as typical value.

a) ±10% while PRODUCTION value unknown for the

customer when R

EXT

≠

123 k

Ω

.

b) ±5% while operating TEMPERATURE range

-40

°

C

≤

T

J

≤

+125

°

C.

5. If you fixed a TCL period = 26 ms

⇒

R

EXT

= 0.975

1.155 x 26 = 30.8 k

Ω

.

If during your production the T

WD

time can be measured at

T

J

= + 25

°

C and the

µ

C can adjust the TCL period, then

the TCL period range will be much larger for the full

operating temperature.

T

WD

ver sus V

OUTPUT

at T

J

= +25

°

C

Fig. 8

T

WD

versus R at T

J

= +25

°

C

Fig. 9

10’000

1000

100

10

1 3 4 5

V

OUTPUT

[V]

T

WD

[ms]

6

R

=

10 M

Ω

R = 1 M

Ω

R = 100 k

Ω

R

=

10 k

Ω

R = 1 k

Ω

0.1 110 100 1000 10’000

1

10

100

1000

10’000

T

WD

[ms]

R[k

Ω

]

3 V

4.8 V

5 V

5.2 V

6 V

R

A6250

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T

WD

versus R at T

J

= +25

°

C

Fig. 10

1

10

100

1000

TWD [ms]

0

.1 1 10 100 1000 10’000

R[k

Ω

]

3 V

4.8 V

5 V

5.2 V

6 V

10’000

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A6250

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T

WD

ver sus V

OUTPUT

at T

J

= +85

°

C T

WD

versus R at T

J

= +85

°

C

Fig. 11 Fig. 12

T

WD

ver sus V

OUTPUT

at T

J

= -40

°

C T

WD

versus R at T

J

= -40

°

C

Fig. 13 Fig. 14

0.1 10 100 1000 10’000

1

10

100

1000

10’000

T

WD

[ms]

R[k

Ω

]

1

3 V

4.8 V

5 V

5.2 V

6 V

10’000

1000

100

10

1 3 4 5

V

OUTPUT

[

V

]

T

WD

[ms]

6

R = 10 M

Ω

R = 1 M

Ω

R = 100 k

Ω

R = 10 k

Ω

R = 1 k

Ω

10’000

1000

100

10

1

3 4 5

V

OUTPUT

[

V

]

T

WD

[ms]

6

R = 10 M

Ω

R = 1 M

Ω

R = 100 k

Ω

R = 10 k

Ω

R = 1 k

Ω

0.1 10 100 1000 10’000

1

10

100

1000

1

R[k

Ω

]

0.1

T

WD

[ms]

3 V

4.8 V

5 V

5.2 V

6 V

10'000

R

A6250

10

www.emmicroelectronic.com

T

WD

versus temperature at 5 V T

WD

versus R at 5 V

Fig. 15 Fig. 16

Maximum OUTPUT Current versus INPUT Voltage

Fig. 17

10’000

1000

100

10

1

-40 0 +40

T

J

[

°

C]

T

WD

[ms]

+80

R = 10 M

Ω

-20 +20 +60

R = 1 M

Ω

R = 100 k

Ω

R = 10 k

Ω

R = 1 k

Ω

0.1 10 100 1000 10’000

1

10

100

1000

10’000

T

WD

[ms]

R[k

Ω

]

1

-40 °C

-20 °C

+25 °C

+70 °C

+85 °C

R

A6250

11

www.emmicroelectronic.com

Timer Clearing and RES Action

The watchdog circuit monitors the activity of the processor.

If the user’s software does not send a pulse to the TCL

input within the programmed open window timeout period a

short watchdog RES pulse is generated which is equal to

T

WD

/40 = 2.5 ms typically (see Fig. 5).

With the open window constraint new security is added to

conventional watchdogs by monitoring both software cycle

time and execution. S hould software clear the watchdog too

quickly (incorrect cycle time) or too slowly (incorrect

execution) it will cause the s ystem to be reset. If software is

stuck in a loop which includes the routine to clear the

watchdog then a conventional watchdog would not make a

system reset even though software is malfunctioning; the

A6250 would make a system reset because the watchdog

would be cleared too q uickly.

If no TCL signal is applied before the closed and open

windows expire, RES will start to generate square waves of

period (T

CW

+ T

OW

+ T

WDR

). The watchdog will remain in this

state until the next TCL falling edge appears during an

open window, or until a fresh power-up sequence. The

system enable output,

EN

, can be used to prevent critical

control functions being activated in the event of the system

going into this failure mode (see section “Enable-

EN

Output”).

The RES output must be pulled up to V

OUTPUT

even if the

output is not used by the system (see Fig 8).

Combined Voltage and Timer Action

The combination of voltage and timer actions is illustrated by

the sequence of eve nts shown in Fig. 6. On po wer-up, when

the voltage at V

IN

reaches V

REF

, the power-on-reset, POR,

delay is initialized and holds RES active for the time of the

POR delay. A TCL pulse will have no effect until this

power-on-reset dela y is completed. After the POR del ay has

elapsed, RES goes inactive and the watchdog timer starts

acting. If no TCL pulse occurs, RES goes active low for a

short time T

WDR

after each closed and open window period.

A TCL pulse coming during the open window clears the

watchdog timer. When the TCL pulse occurs too early

(during the closed window), RES goes active and a new

timeout sequence starts. A voltage drop below the V

REF

level

for longer than typically 5

µ

s overrides the timer and

immediately forces RES active and

EN

inactive. Any

further TCL pulse has no effect until the next power-up

sequence has completed.

Enable - EN Output

The system enable output,

EN

,is inactive always when

RES is active and remains in active after a RES pulse until

the watchdog is serviced correctly 3 consecutive times (ie.

the TCL pulse must come in the open window). After three

consecutive services of the watchdog with TCL during the

open window, the

EN

goes active low.

A malfunctioning system would be repeatedly reset by the

watchdog. In a conventional system critical motor controls

could be energized each time reset goes inactive (time

allowed for the system to restart) and in this way the

electrical motors driven by the system could function out of

control. The A6250 prevents the above failure mode by

using the

EN

output to disable the motor controls until

software has successfully cleared the watchdog three times

(ie. the system has correctly re-started after a reset

condition).

Typical Application

Fig. 18

INPUT OUTPUT

A6250

R

VSS

22 µF

+

Regulated voltage

Unregulated voltage

GND

100 kΩ

100 nF

10

µ

FR

1

R

2

Address

decoder

Microprocessor

RES

EN

VIN

TCL

RE

S

EN

100 k

Ω

Motor

Controls

R

A6250

12

www.emmicroelectronic.com

T

WD

Coefficient versus R

EXT

at T

J

= + 25

°

C

Fig. 19

R

EXT

Coefficient versus T

WD

at T

J

= + 25

°

C

Fig. 20

0.96

0.94

0.92

0.90

0.88

0.86

0.84

0.82

0.80

0.78

0.76

TWD Coefficient

10 1000

100

REXT

[

k

Ω

]

1.30

1.28

1.26

1.24

1.22

1.20

1.18

1.16

1.14

1.12

1.10

1.08

1.06

1.04

REXT Coefficient

10 100 1000

TWD [ms]

R

A6250

13

www.emmicroelectronic.com

Package and Ordering Information

Dimensions of PSOP2-16 Package

Fig. 21

Dual Layer PCB

Fig. 22

Ordering Information

When ordering, please sp ecify the complete part numb er.

Part Number Package Delivery Form Package Marking

(first line)

A6250V1PS16B 16-pin PSOP2 Tape & Reel A62500116W

EM Microelectronic-Marin SA (EM) makes no warranty for the use of its products, other than those expressl y contained in the Company's

standard warranty which is detailed in EM's General Terms of Sale located on the Company's web site. EM assumes no responsibility for any

errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice,

and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of EM are

granted in connection with the sale of EM products, expressly or by implications. EM's products are not authorized for use as components in