LTC3300ILXE-2#PBF - LINEAR TECHNOLOGY

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

APPLICATIONS

TYPICAL APPLICATION

FEATURES DESCRIPTION

Addressable High Efficiency

Bidirectional Multicell

Battery Balancer

The LTC

3300-2 is a fault-protected controller IC for

transformer-based bidirectional active balancing of multi-

cell battery stacks. All associated gate drive circuitry,

precision current sensing, fault detection circuitry and a

robust serial interface with built-in watchdog timer are

integrated.

Each LTC3300-2 can balance up to 6 series-connected

battery cells with an input common mode voltage up to

36V. Charge from any selected cell can be transferred at

high efficiency to or from 12 or more adjacent cells. Each

LTC3300-2 has an individually addressable serial interface,

allowing up to 32 LTC3300-2 devices to interface to one

control processor.

Fault protection features include readback capability, cy-

clic redundancy check (CRC) error detection, maximum

on-time volt-second clamps, and overvoltage shutoffs.

The related LTC3300-1 offers a serial interface that allows

the serial ports of multiple LTC3300-1 devices to be daisy-

chained without opto-couplers or isolators.

High Efficiency Bidirectional Balancing

Balancer Efficiency

n Bidirectional Synchronous Flyback Balancing

of Up to 6 Li-Ion or LiFePO4 Cells in Series

n Up to 10A Balancing Current (Set by Externals)

n Integrates Seamlessly with the LTC680x Family of

Multicell Battery Stack Monitors

n Bidirectional Architecture Minimizes Balancing

Time and Power Dissipation

n Up to 92% Charge Transfer Efficiency

n Stackable Architecture Enables >800V Systems

n Uses Simple 2-Winding Transformers

n 1MHz Serial Interface with 4-Bit

CRC Packet Error Checking

n Individually Addressable with 5-Bit Address

n Numerous Fault Protection Features

n 48-Lead Exposed Pad QFN and LQFP Packages

n Electric Vehicles/Plug-in HEVs

n High Power UPS/Grid Energy Storage Systems

n General Purpose Multicell Battery Stacks

L, LT, LTC , LT M , Linear Technology and the Linear logo are registered trademarks and isoSPI

is a trademark of Linear Technology Corporation. All other trademarks are the property of their

respective owners.

SERIAL I/O

+CELL 1

ICHARGE

CHARGE

SUPPLY

CHARGE

SUPPLY

(ICHARGE 1-6)

NEXT CELL BELOW

33002 TA01a

LTC3300-2

ADDRESS n + 1

ADDRESS n

NEXT CELL ABOVE

•

+CELL 6

+CELL 7

+CELL 12

IDISCHARGE

CHARGE

RETURN

CHARGE

RETURN

(IDISCHARGE 1-6)

•

ISOLATOR

NUMBER OF CELLS (SECONDARY SIDE)

CHARGE TRANSFER EFFICIENCY (%)

100

8 10

CHARGE

DISCHARGE

33001 TA01b

DC2064A DEMO BOARD

ICHARGE = IDISCHARGE = 2.5A

VCELL = 3.6V

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

ABSOLUTE MAXIMUM RATINGS

Total Supply Voltage (C6 to V–) ................................. 36V

Input Voltage (Relative to V–)

C1 ........................................................... –0.3V to 6V

I1P ....................................................... –0.3V to 0.3V

I1S, I2S, I3S, I4S, I5S, I6S .................... –0.3V to 0.3V

CSBI, SCKI, SDI ....................................... –0.3V to 6V

VREG, SDO ............................................... –0.3V to 6V

RTONP, RTONS ........... –0.3V to Min[VREG + 0.3V, 6V]

CTRL, BOOST, WDT ....–0.3V to Min[VREG + 0.3V, 6V]

A4, A3, A2, A1, A0 .......–0.3V to Min[VREG + 0.3V, 6V]

(Note 1)

TOP VIEW

V–

UK PACKAGE

48-LEAD (7mm × 7mm) PLASTIC QFN

G6S 1

I6S 2

G5S 3

I5S 4

G4S 5

I4S 6

G3S 7

I3S 8

G2S 9

I2S 10

G1S 11

I1S 12

36 C5

35 G5P

34 I5P

33 C4

32 G4P

31 I4P

30 C3

29 G3P

28 I3P

27 C2

26 G2P

25 I2P

48 VREG

47 A4

46 A3

45 A2

44 A1

43 A0

42 BOOST

41 BOOST–

40 BOOST+

39 C6

38 G6P

37 I6P

RTONS 13

RTONP 14

CTRL 15

CSBI 16

SCKI 17

SDI 18

SDO 19

WDT 20

V– 21

I1P 22

G1P 23

C1 24

TJMAX = 150°C, θJA = 34°C/W, θJC = 3°C/W

EXPOSED PAD (PIN 49) IS V–, MUST BE SOLDERED TO PCB

G6S

I6S

G5S

I5S

G4S

I4S

G3S

I3S

G2S

I2S

G1S

I1S

RTONS

RTONP

CTRL

CSBI

SCKI

SDI

SDO

WDT

V–

I1P

G1P

VREG

BOOST

BOOST–

BOOST+

G6P

I6P

G5P

I5P

G4P

I4P

G3P

I3P

G2P

I2P

TOP VIEW

V–

LXE PACKAGE

48-LEAD (7mm × 7mm) PLASTIC LQFP

TJMAX = 150°C, θJA = 20.46°C/W, θJC = 3.68°C/W

EXPOSED PAD (PIN 49) IS V–, MUST BE SOLDERED TO PCB

PIN CONFIGURATION

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3300IUK-2#PBF LTC3300IUK-2#TRPBF LTC3300UK-2 48-Lead (7mm × 7mm) Plastic QFN –40°C to 125°C

LTC3300HUK-2#PBF LTC3300HUK-2#TRPBF LTC3300UK-2 48-Lead (7mm × 7mm) Plastic QFN –40°C to 150°C

LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3300ILXE-2#PBF LTC3300ILXE-2#PBF LTC3300LXE-2 48-Lead (7mm × 7mm) Plastic eLQFP –40°C to 125°C

LTC3300HLXE-2#PBF LTC3300HLXE-2#PBF LTC3300LXE-2 48-Lead (7mm × 7mm) Plastic eLQFP –40°C to 150°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

Voltage Between Pins

Cn to Cn-1* .............................................. –0.3V to 6V

InP to Cn-1* .......................................... –0.3V to 0.3V

BOOST+ to C6 .......................................... –0.3V to 6V

SDO Current ........................................................... 10mA

G1P, GnP, G1S, GnS, BOOST– Current ............... ±200mA

Operating Junction Temperature Range (Notes 2, 7)

LTC3300I-2 ........................................ –40°C to 125°C

LTC3300H-2 ...................................... –40°C to 150°C

Storage Temperature Range .................. –65°C to 150°C

*n = 2 to 6

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) BOOST+ = 25.2V, C6 = 21.6V, C5 = 18V, C4 = 14.4V,

C3 = 10.8V, C2 = 7.2V, C1 = 3.6V, V– = 0V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

DC Specifications

IQ_SD Supply Current When Not

Balancing (Post Suspend or Pre

First Execute)

Measured at C1, C2, C3, C4, C5

Measured at C6

Measured at BOOST+

µA

IQ_ACTIVE Supply Current When Balancing

(Note 3)

Balancing C1 Only (Note 4 for V–, C2, C6)

Measured at C1

Measured at C2, C3, C4, C5

Measured at C6

Measured at BOOST+

250

560

375

105

840

µA

Balancing C2 Only (Note 4 for C1, C3, C6)

Measured at C1

Measured at C2

Measured at C3, C4, C5

Measured at C6

Measured at BOOST+

–105

–70

250

560

375

105

840

µA

Balancing C3 Only (Note 4 for C2, C4, C6)

Measured at C1, C4, C5

Measured at C2

Measured at C3

Measured at C6

Measured at BOOST+

–105

–70

250

560

105

375

840

µA

Balancing C4 Only (Note 4 for C3, C5, C6)

Measured at C1, C2, C5

Measured at C3

Measured at C4

Measured at C6

Measured at BOOST+

–105

–70

250

560

105

375

840

µA

Balancing C5 Only (Note 4 for C4, C6)

Measured at C1, C2, C3

Measured at C4

Measured at C5

Measured at C6

Measured at BOOST+

–105

–70

250

560

105

375

840

µA

Balancing C6 Only (Note 4 for C5, C6, BOOST+)

Measured at C1, C2, C3, C4

Measured at C5

Measured at C6

Measured at BOOST+ (BOOST = V–)

Measured at BOOST+ (BOOST = VREG)

–105

–70

740

105

1110

µA

VCELL|MIN Minimum Cell Voltage (Rising)

Required for Primary Gate Drive

Cn to Cn – 1 Voltage to Balance Cn, n = 2 to 6

C1 Voltage to Balance C1

Cn + 1 to Cn Voltage to Balance Cn, n = 1 to 5

BOOST+ to C6 Voltage to Balance C6, BOOST = V–

1.8

2.2

VCELL|MIN(HYST) VCELL|MIN Comparator Hysteresis 70 mV

VCELL|MAX Maximum Cell Voltage (Rising)

Before Disabling Balancing

C1, Cn to Cn – 1 Voltage to Balance Any Cell,

n = 2 to 6

l4.7 5 5.3 V

VCELL|MAX(HYST) VCELL|MAX Comparator Hysteresis 0.5 V

VCELL|RECONNECT Maximum Cell Voltage (Falling) to

Re-Enable Balancing

l4.25 V

VREG Regulator Pin Voltage 9V ≤ C6 ≤ 36V, 0mA ≤ ILOAD ≤ 20mA l4.4 4.8 5.2 V

VREG|POR VREG Voltage (Rising) for

Power-On Reset

4.0 V

VREG|MIN Minimum VREG Voltage (Falling)

for Secondary Gate Drive

VREG Voltage to Balance Cn, n = 1 to 6 l3.8 V

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) BOOST+ = 25.2V, C6 = 21.6V, C5 = 18V, C4 = 14.4V,

C3 = 10.8V, C2 = 7.2V, C1 = 3.6V, V– = 0V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

IREG_SC Regulator Pin Short Circuit Current

Limit

VREG = 0V 55 mA

VRTONP RTONP Servo Voltage RRTONP = 20kΩ l1.158 1.2 1.242 V

VRTONS RTONS Servo Voltage RRTONS = 15kΩ l1.158 1.2 1.242 V

IWDT_RISING WDT Pin Current, Balancing RTONS = 15kΩ, WDT = 0.5V l72 80 88 µA

IWDT_FALLING WDT Pin Current as a Percentage

of IWDT_RISING, Secondary OV

RTONS = 15kΩ, WDT = 2V l85 87.5 90 %

VPEAK_P Primary Winding Peak Current

Sense Voltage

I1P

InP to Cn – 1, n = 2 to 6

VPEAK_P Matching (All 6) ±[(Max – Min)/(Max + Min)] • 100% l±1.7 ±5 %

VPEAK_S Secondary Winding Peak Current

Sense Voltage

I1S

InS to Cn – 1, n = 2 to 6, CTRL = 0 Only

VPEAK_S Matching (All 6) ±[(Max – Min)/(Max + Min)] • 100% l±0.5 ±3 %

VZERO_P Primary Winding Zero Current

Sense Voltage (Note 5)

I1P

InP to Cn – 1, n = 2 to 6

–7

–2

VZERO_P Matching (All 6)

Normalized to Mid-Range VPEAK_P

±{[(Max – Min)/2]/(VPEAK_P|MIDRANGE)} • 100%

(Note 6)

l±1.7 ±5 %

VZERO_S Secondary Winding Zero Current

Sense Voltage (Note 5)

I1S

InS to Cn – 1, n = 2 to 6, CTRL = 0 Only

–12

–7

–2

VZERO_S Matching (All 6)

Normalized to Mid-Range VPEAK_S

±{[(Max – Min)/2]/(VPEAK_S|MIDRANGE)} • 100%

(Note 6)

l±0.5 ±3 %

RBOOST_L BOOST– Pin Pull-Down RON Measured at 100mA Into Pin, BOOST = VREG 2.5 Ω

RBOOST_H BOOST– Pin Pull-Up RON Measured at 100mA Out of Pin, BOOST = VREG 4 Ω

TSD Thermal Shutdown Threshold

(Note 7)

Rising Temperature 155 °C

THYS Thermal Shutdown Hysteresis 10 °C

Timing Specifications

tr_P Primary Winding Gate Drive Rise

Time (10% to 90%)

G1P Through G6P, CGATE = 2500pF 35 70 ns

tf_P Primary Winding Gate Drive Fall

Time (90% to 10%)

G1P Through G6P, CGATE = 2500pF 20 40 ns

tr_S Secondary Winding Gate Drive

Rise Time (10% to 90%)

G1S, CGATE = 2500pF

G2S Through G6S, CTRL = 0 Only, CGATE = 2500pF

tf_S Secondary Winding Gate Drive Fall

Time (90% to 10%)

G1S, CGATE = 2500pF

G2S Through G6S, CTRL = 0 Only, CGATE = 2500pF

tONP|MAX Primary Winding Switch Maximum

On-Time

RRTONP = 20kΩ (Measured at G1P-G6P) l6 7.2 8.4 µs

tONP|MAX Matching (All 6) ±[(Max – Min)/(Max + Min)] • 100% l±1 ±4 %

tONS|MAX Secondary Winding Switch

Maximum On-Time

RRTONS = 15kΩ (Measured at G1S-G6S) l1 1.2 1.4 µs

tONS|MAX Matching (All 6) ±[(Max – Min)/(Max + Min)] • 100% l±1 ±4 %

tD LY _START Delayed Start Time After New/

Different Balance Command or

Recovery from Voltage/Temp Fault

2 ms

SPI Port Timing Specifications

t1SDI Valid to SCKI Rising Setup Write Operation l10 ns

t2SDI Valid from SCKI Rising Hold Write Operation l250 ns

t3SCKI Low l400 ns

t4SCKI High l400 ns

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) BOOST+ = 25.2V, C6 = 21.6V, C5 = 18V, C4 = 14.4V,

C3 = 10.8V, C2 = 7.2V, C1 = 3.6V, V– = 0V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

t5CSBI Pulse Width l400 ns

t6SCKI Rising to CSBI Rising l100 ns

t7CSBI Falling to SCKI Rising l100 ns

t8SCKI Falling to SDO Valid Read Operation l250 ns

fCLK Clock Frequency l1 MHz

tWD1 Watchdog Timer Timeout Period WDT Assertion Measured from Last Valid

Command Byte

l0.75 1.5 2.25 second

tWD2 Watchdog Timer Reset Time WDT Negation Measured from Last Valid

Command Byte

l1.5 5 µs

Digital I/O Specifications

VIH Digital Input Voltage High Pins CSBI, SCKI, SDI

Pins CTRL, BOOST

Pins A4, A3, A2, A1, A0

Pin WDT

VREG – 0.5

VIL Digital Input Voltage Low Pins CSBI, SCKI, SDI

Pins CTRL, BOOST

Pins A4, A3, A2, A1, A0

Pin WDT

0.5

0.8

IIH Digital Input Current High Pins CSBI, SCKI, SDI

Pins CTRL, BOOST

Pins A4, A3, A2, A1, A0

Pin WDT, Timed Out

–1

µA

IIL Digital Input Current Low Pins CSBI, SCKI, SDI

Pins CTRL, BOOST

Pins A4, A3, A2, A1, A0

Pin WDT, Not Balancing

–1

µA

VOL Digital Output Voltage Low Pin SDO, Sinking 500µA; Read l0.3 V

IOH Digital Output Current High Pin SDO at 6V l100 nA

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC3300-2 is tested under pulsed load conditions such

that TJ ≈ TA. The LTC3300I-2 is guaranteed over the –40°C to 125°C

operating junction temperature range and the LTC3300H-2 is guaranteed

over the –40°C to 150°C operating junction temperature. High junction

temperatures degrade operating lifetimes; operating lifetime is derated

for junction temperatures greater than 125°C. Note that the maximum

ambient temperature consistent with these specifications is determined by

specific operating conditions in conjunction with board layout, the rated

package thermal impedance and other environmental factors. The junction

temperature (TJ, in °C) is calculated from the ambient temperature

(TA, in °C) and power dissipation (PD, in Watts) according to the formula:

TJ = TA + (PD • θJA)

where θJA (in °C/W) is the package thermal impedance.

Note 3: When balancing more than one cell at a time, the individual cell

supply currents can be calculated from the values given in the table as

follows: First add the appropriate table entries cell by cell for the balancers

that are on. Second, for each additional balancer that is on, subtract 70µA

from the resultant sums for C1, C2, C3, C4, and C5, and 450µA from the

resultant sum for C6. For example, if all six balancers are on, the resultant

current for C1 is [250 – 70 + 70 + 70 + 70 + 70 – 5(70)]µA = 110µA and

for C6 is [560 + 560 + 560 + 560 + 560 + 740 – 5(450)]µA = 1290µA.

Note 4: Dynamic supply current is higher due to gate charge being

delivered at the switching frequency during active balancing. See Gate

Drivers/Gate Drive Comparators and Voltage Regulator in the Operation

section for more information on estimating these currents.

Note 5: The zero current sense voltages given in the table are DC

thresholds. The actual zero current sense voltage seen in application will

be closer to zero due to the slew rate of the winding current and the finite

delay of the current sense comparator.

Note 6: The mid-range value is the average of the minimum and maximum

readings within the group of six.

Note 7: This IC includes overtemperature protection intended to protect

the device during momentary overload conditions. The maximum junction

temperature may be exceeded when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may result in device degradation or failure.

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

TYPICAL PERFORMANCE CHARACTERISTICS

Maximum Cell Voltage to Allow

Balancing vs Temperature VREG Load Regulation VREG Voltage vs Temperature

C6 Supply Current When Not

Balancing vs Temperature

TA = 25°C unless otherwise specified.

Supply Current When Balancing

vs Temperature Normalized to 25°C

Minimum Cell Voltage Required

for Primary Gate Drive vs

Temperature

VREG POR Voltage and Minimum

Secondary Gate Drive vs

Temperature

VREG Short-Circuit Current Limit

vs Temperature VRTONP, VRTONS vs Temperature

TEMPERATURE (°C)

–50

IQ(SD) (µA)

25 75 150

33002 G01

10 –25 0 50 100 125

C6 = 21.6V

TEMPERATURE (°C)

–50

0.94

IQ(ACTIVE)/IQ(ACTIVE AT 25°C)

0.96

0.98

1.00

1.02

0 50 100 150

33002 G02

1.04

1.06

–25 25 75 125

TYP = 740µA

TYP = 560µA

TYP = 250µA

TYP = 70µA

TYP = 60µA

TYP = –70µA

3.6V PER CELL

MATCH CURVE WITH TABLE ENTRY

TEMPERATURE (°C)

–50

1.80

VCELL(MIN) (V)

1.85

1.90

1.95

2.00

0 50 100 150

33002 G03

2.05

2.10

–25 25 75 125

CELL VOLTAGE RISING

CELL VOLTAGE FALLING

TEMPERATURE (°C)

–50

4.2

VCELL(MAX) (V)

4.3

4.5

4.6

4.7

5.2

4.9

050 75

LT33002 G04

4.4

5.0

5.1

4.8

–25 25 100 125 150

CELL VOLTAGE RISING

CELL VOLTAGE FALLING

IVREG (mA)

VREG (V)

4.8

4.9

5.0

33002 G05

4.7

4.6

4.5 5 10 15 20 25 30 35 45 50

TA = 25°C

C6 = 36V

C6 = 9V

TEMPERATURE (°C)

–50

4.60

VREG (V)

4.61

4.63

4.64

4.65

4.70

4.67

050 75

33002 G06

4.62

4.68

4.69

4.66

–25 25 100 125 150

IVREG = 10mA

C6 = 36V

C6 = 9V

TEMPERATURE (°C)

–50

VREG (V)

4.000

4.050

150

33002 G07

3.950

3.900 050 100

–25 25 75 125

4.100

3.975

4.025

3.925

4.075

C6 = 21.6V

VREG RISING (POR)

VREG FALLING

(MIN SEC. GATE DRIVE)

TEMPERATURE (°C)

–50

IVREG (mA)

050 75

33002 G08

–25 25 100 125 150

C6 = 21.6V

TEMPERATURE (°C)

–50

1.164

VRTONP, VRTONS (V)

1.176

1.188

1.200

1.212

0 50 100 150

33002 G09

1.224

1.236

–25 25 75 125

VRTONP

VRTONS

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

Peak Current Sense Threshold

vs Temperature

Zero Current Sense Threshold

vs Temperature

Primary Winding Switch Maximum

On-Time vs Temperature

Secondary Winding Switch

Maximum On-Time vs Temperature

Maximum On-Time

vs RTONP, RTONS

Watchdog Timer Timeout Period

vs Temperature

VRTONP, VRTONS

vs External Resistance WDT Pin Current vs Temperature WDT Pin Current vs RTONS

RTONP, RTONS RESISTANCE (kΩ)

1.164

VRTONP, VRTONS (V)

1.176

1.188

1.200

1.212

1.236

10 100

33002 G10

1.224

VRTONS VRTONP

TA = 25°C

TEMPERATURE (°C)

–50

IWDT (µA)

–25 0 25 50

33002 G11

75 100 125 150

RTONS = 15k

BALANCING

WDT = 0.5V

SECONDARY OV

WDT = 2V

RTONS (kΩ)

IWDT (µA)

120

160

15 25 35 45

33002 G12

200

240

10 20 30 40

TA = 25°C

BALANCING

WDT = 0.5V

SECONDARY OV

WDT = 2V

TEMPERATURE (°C)

–50

VPEAK_P, VPEAK_S (mV)

25 75 150

33002 G13

45 –25 0 50 100 125

VCELL = 3.6V

RANDOM CELL SELECTED

PRIMARY

SECONDARY

TEMPERATURE (°C)

–50

–10.0

VZERO_P, VZERO_S (mV)

–7.5

–5.0

–2.5

0 50 100 150

33002 G14

2.5

5.0

–25 25 75 125

VCELL = 3.6V

RANDOM CELL SELECTED

PRIMARY

SECONDARY

TEMPERATURE (°C)

–50

6.0

tONP(MAX) (µs)

6.4

6.8

7.2

7.6

0 50 100 150

33002 G15

8.0

8.4

–25 25 75 125

RTONP = 20k

VCELL = 3.6V

TEMPERATURE (°C)

–50

1.0

tONS(MAX) (µs)

1.1

1.2

1.3

1.4

–25 0 25 50

33002 G16

75 100 125 150

RTONS = 15k

RTONP, RTONS (kΩ)

tONP(MAX),tONS(MAX) (µs)

15 25 30

33002 G17

10 20 35 40 45

TA = 25°C

PRIMARY

SECONDARY

TEMPERATURE (°C)

–50

1.35

tWD1 (SECONDS)

1.40

1.45

1.50

1.55

0 50 100 150

33002 G18

1.60

1.65

–25 25 75 125

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C unless otherwise specified.

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

Balance Current vs Cell Voltage

Protection for Broken Connection

to Cell While Charging

Protection for Broken Connection

to Secondary Stack While

Discharging

Typical Charge Waveforms Typical Discharge Waveforms

Changing Balancer Direction

“On the Fly”

Balancer Efficiency

vs Cell Voltage

VOLTAGE PER CELL (V)

2.8

CHARGE TRANSFER EFFICIENCY (%)

3.0 3.2 3.4 3.6

33002 G19

3.8 4.0 4.2

DC2064A DEMO BOARD

ICHARGE = IDISCHARGE = 2.5A

FOR 12-CELL STACK ONLY

DISCHARGE, 12-CELL STACK

DISCHARGE, 6-CELL STACK

CHARGE, 6-CELL STACK

CHARGE, 12-CELL STACK

VOLTAGE PER CELL (V)

2.8

BALANCE CURRENT (A)

2.5

2.6

2.7

3.4 3.8

33002 G20

2.4

2.3

3.0 3.2 3.6 4.0 4.2

2.2

2.1

DC2064A DEMO BOARD

ICHARGE = IDISCHARGE = 2.5A

FOR 12-CELL STACK ONLY

CHARGE, 12-CELL STACK

CHARGE, 6-CELL STACK

DISCHARGE, 12-CELL STACK

DISCHARGE, 6-CELL STACK

I1S

50mV/DIV

I1P

50mV/DIV

SECONDARY

DRAIN

50V/DIV

PRIMARY

DRAIN

50V/DIV

2µs/DIV

DC2064A DEMO BOARD

ICHARGE = 2.5A

T = 2

S = 12

33002 G21

I1P

50mV/DIV

I1S

50mV/DIV

SECONDARY

DRAIN

50V/DIV

PRIMARY

DRAIN

50V/DIV 2µs/DIV

DC2064A DEMO BOARD

IDISCHARGE = 2.5A

T = 2

S = 12

33002 G22

C1 PIN

1V/DIV

G1P

2V/DIV

50µs/DIV 33002 G23

3.6V

~5.2V

CONNECTION TO

C1 BROKEN

BALANCING

SHUTS OFF

SECONDARY

STACK VOLTAGE

10V/DIV

G1P

2V/DIV

500µs/DIV 33002 G24

43.2V

~66V

CONNECTION TO

STACK BROKEN

BALANCING

SHUTS OFF

SCKI

5V/DIV

I1P

50mV/DIV

G1P

2V/DIV

20µs/DIV 33002 G25

2ms

CHARGING

DISCHARGING

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C unless otherwise specified.

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

PIN FUNCTIONS

Note: The convention adopted in this data sheet is to refer

to the transformer winding paralleling an individual battery

cell as the primary and the transformer winding paralleling

multiple series-stacked cells as the secondary, regardless

of the direction of energy transfer.

G6S, G5S, G4S, G3S, G2S, G1S (Pins 1, 3, 5, 7, 9,

11): G1S through G6S are gate driver outputs for driving

external NMOS transistors connected in series with the

secondary windings of transformers whose primaries are

connected in parallel with battery cells 1 through 6. For

the minimum part count balancing application employing

a single transformer (CTRL = VREG), G2S through G6S

are no connects.

I6S, I5S, I4S, I3S, I2S, I1S (Pins 2, 4, 6, 8, 10, 12): I1S

through I6S are current sense inputs for measuring sec-

ondary winding current in transformers whose primaries

are connected in parallel with battery cells 1 through 6.

For the minimum part count balancing application employ-

ing a single transformer (CTRL = VREG), I2S through I6S

should be tied to V–.

RTONS (Pin 13): Secondary Winding Max tON Setting

Resistor. The RTONS pin servos to 1.2V. A resistor to

V– programs the maximum on-time for all external NMOS

transistors connected in series with secondary windings.

This protects against a short-circuited current sense re-

sistor in any secondary winding. To defeat this function,

connect RTONS to VREG. The secondary winding OVP

threshold (see WDT pin) is also slaved to the value of the

RTONS resistor.

RTONP (Pin 14): Primary Winding Max tON Setting

Resistor. The RTONP pin servos to 1.2V. A resistor to

V–programs the maximum on-time for all external NMOS

transistors connected in series with primary windings. This

protects against a short-circuited current sense resistor

in any primary winding. To defeat this function, connect

RTONP to VREG.

CTRL: (Pin 15): Control Input. The CTRL pin configures

the LTC3300-2 for the minimum part count application

employing a single transformer if CTRL is tied to VREG or

for the multiple transformer application if CTRL is tied to

V–. This pin must be tied to either VREG or V–.

CSBI (Pin 16): Chip Select (Active Low) Input. The CSBI

pin interfaces to a rail-to-rail output logic gate. See Serial

Port in the Operation section.

SCKI (Pin 17): Serial Clock Input. The SCKI pin interfaces

to a rail-to-rail output logic gate. See Serial Port in the

Operation section.

SDI (Pin 18): Serial Data Input. When writing data to the

LTC3300-2, the SDI pin interfaces to a rail-to-rail output

logic gate. See Serial Port in the Operation section.

SDO (Pin 19): Serial Data Output. When reading data

from the LTC3300-2, the SDO pin is an NMOS open-drain

output. See Serial Port in the Operation section.

WDT (Pin 20): Watchdog Timer Output (Active High). At

initial power-up and when not attempting to execute a valid

balance command, the WDT pin is high impedance and will

be pulled high (internally clamped to ~5.6V) if an external

pull-up resistor is present. While balancing (or attempt-

ing to balance but not able to due to voltage/temperature

faults)

and during normal communication activity, the WDT

pin is pulled low by a precision current source slaved to

the RTONS resistor. However, if no valid command byte is

written for 1.5 seconds (typical), the WDT output will go

back high. When WDT is high, all balancers are off. The

watchdog timer function can be disabled by connecting

WDT to V–. The secondary winding OVP function can also

be implemented using this pin (See Operation section).

V– (Pin 21, Exposed Pad Pin 49): Connect V– to the most

negative potential in the series of cells. The exposed pad

should be connected to a continuous (ground) plane biased

at V– on the second layer of the printed circuit board by

several vias directly under the LTC3300-2.

I1P, I2P, I3P, I4P, I5P, I6P (Pins 22, 25, 28, 31, 34, 37):

I1P through I6P are current sense inputs for measuring

primary winding current in transformers connected in

parallel with battery cells 1 through 6.

G1P, G2P, G3P, G4P, G5P, G6P (Pins 23, 26, 29, 32, 35,

38): G1P through G6P are gate driver outputs for driving

external NMOS transistors connected in series with the

primary windings of transformers connected in parallel

with battery cells 1 through 6.

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

PIN FUNCTIONS

C1, C2, C3, C4, C5, C6 (Pins 24, 27, 30, 33, 36, 39):

C1 through C6 connect to the positive terminals of bat-

tery cells 1 through 6. Connect the negative terminal of

battery cell 1 to V–.

BOOST+ (Pin 40): Boost+ Pin. Connects to the anode of

the external flying capacitor used for generating sufficient

gate drive necessary for balancing the topmost battery cell

in a given LTC3300-2 sub-stack. A Schottky diode from

C6 to BOOST+ is needed as well. Alternately, the BOOST+

pin can connect to one cell up in the above sub-stack (if

present). This pin is effectively C7. (Note: “Sub-stack” refers

to the 3-6 battery cells connected locally to an individual

LTC3300-2 as part of a larger stack.)

BOOST– (Pin 41): Boost– Pin. Connects to the cathode of

the external flying capacitor used for generating sufficient

gate drive necessary for balancing the topmost battery

cell in a given LTC3300-2 sub-stack. Alternately, if the

BOOST+ pin connects to the next higher cell in the above

sub-stack (if present), this pin is a no connect.

BOOST (Pin 42): Enable Boost Pin. Connect BOOST to VREG

to enable the boosted gate drive needed for balancing the

top cell in a given LTC3300-2 sub-stack. If the BOOST+ pin

can be connected to the next cell up in the stack (i.e., C1

of the next LTC3300-2 in the stack), then BOOST should

be tied to V– and BOOST– no connected. This pin must

be tied to either VREG or V–.

A0, A1, A2, A3, A4 (Pins 43, 44, 45, 46, 47): Address

Inputs. The state of the address pins (VREG = 1, V– = 0)

determines the LTC3300-2 address. These pins must be

tied to either VREG or V–. See Serial Port in the Operation

section.

VREG (Pin 48): Linear Voltage Regulator Output. This 4.8V

output should be bypassed with a 1µF or larger capacitor

to V–. The VREG pin is capable of supplying up to 40mA

to internal and external loads. The VREG pin does not sink

current.

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

BLOCK DIAGRAM

–

BOOST+

BOOST

GATE DRIVE

GENERATOR

6-CELL

SYNCHRONOUS

FLYBACK

CONTROLLER

BALANCER

DATA

STATUS

50mV/0

0/50mV

VREG

V–

–

BOOST

BOOST–

VREG

C6 40mA

MAX

V–POR

4.8V 42

G6P 38

I6P 37

I6S 2

G6S

PINS 3 TO 10,

25 TO 36

BALANCER

CONTROLLER

–

V–

50mV/0

0/50mV

VREG

V–

–

G1P 23

I1P 22

I1S 12

G1S 11

BALANCER

CONTROLLER

ACTIVE

MAX ON-TIME

VOLT-SEC

CLAMPS

THERMAL

SHUTDOWN

BOOST+

V–RTONS

CTRL

V–

WDT

16 CSBI

17 SCKI

18 SDI

19 SDO

43 A0

45 A2

RESET

RTONP

33002 BD

V–

5.6V

1.2V

RTONS

V–

EXPOSED

PAD

LEVEL-SHIFTING

SERIAL

INTERFACE

VREG

VOLTAGE

REGULATOR

CRC/RCRC

PACKET ERROR

CHECKING

WATCHDOG

TIMER

5ADDRESS

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

TIMING DIAGRAM

t6t7

SCKI

SDI

CSBI

SDO

33002 TD

Timing Diagram of the Serial Interface

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

OPERATION

Battery Management System (BMS)

The LTC3300-2 multicell battery cell balancer is a key

component in a high performance battery management

system (BMS) for series-connected Li-Ion cells. It is de-

signed to operate in conjunction with a monitor, a charger,

and a microprocessor or microcontroller (see Figure 1).

The function of the balancer is to efficiently transfer charge

to/from a given out-of-balance cell in the stack from/to

a larger group of neighboring cells (which includes that

individual cell) in order to bring that cell into voltage or

capacity balance with its neighboring cells. Ideally, this

charge would always be transferred directly from/to the

entire stack, but this is impractical for voltage reasons

when the number of cells in the overall stack is large. The

LTC3300-2 is designed to interface to a group of up to 6

series cells, so the number of LTC3300-2 ICs required to

balance a series stack of N cells is N/6 rounded up to the

nearest integer. Since the LTC3300-2 address is 5 bits,

the maximum N can be is 192 cells. For connecting an

individual LTC3300-2 in the stack to fewer than 6 cells,

refer to the Applications Information section.

Because the balancing function entails switching large

(multiampere) currents between cells, precision voltage

monitoring in the BMS is better served by a dedicated

monitor component such as the LTC6803-2 or one of its

family of parts. The LTC6803-2 provides for high precision

A/D monitoring of up to 12 series cells. The only voltage

monitoring provided by the LTC3300-2 is a coarse “out-

of-range” overvoltage and undervoltage cell balancing

disqualification, which provides a safety shutoff in the

event Kelvin sensing to the monitor component is lost.

In the process of bringing the cells into balance, the over-

all stack is slightly discharged. The charger component

provides a means for net charging of the entire stack from

an alternate power source.

The last component in the BMS is a microprocessor/

microcontroller which communicates directly with the

balancer, monitor, and charger to receive voltage, cur-

rent, and temperature information and to implement a

balancing algorithm.

There is no single balancing algorithm optimal for all

situations. For example, during net charging of the overall

stack, it may be desirable to discharge the highest voltage

cells first to avoid reaching terminal charge on any cell

before the entire stack is fully charged. Similarly, during

net discharging of the overall stack, it may be desirable

to charge the lowest voltage cells first to keep them from

reaching a critically low level. Other algorithms may

prioritize fastest time to overall balance. The LTC3300-2

implements no algorithm for balancing the stack. Instead it

provides maximum flexibility by imposing no limitation on

the algorithm implemented as all individual cell balancers

can operate simultaneously and bidirectionally.

Unidirectional Versus Bidirectional Balancing

Most balancers in use today employ a unidirectional (dis-

charge only) approach. The simplest of these operate by

switching in a resistor across the highest voltage cell(s)

in the stack (passive balancing). No charge is recovered

in this approach -instead it is dissipated as heat in the

resistive element. This can be improved by employing an

energy storage element (inductive or capacitive) to transfer

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

CELL N

CELL N – 1

CELL N – 2

CELL N – 3

CELL N – 4

CELL N – 5

CELL N – 6

CELL N – 7

CELL N – 8

CELL N – 9

CELL N – 10

CELL N – 11

CELL 12

CELL 11

CELL 10

CELL 9

CELL 8

CELL 7

CELL 6

CELL 5

CELL 4

CELL 3

CELL 2

CELL 1

ICHARGE

SERIAL COMMUNICATION BUS

V–

C6 C11 ILOAD

C10

C1 V–

C12

LTC3300-2

BALANCER

LTC6803-2

MONITOR

TOP OF STACK

CHARGER

V–

LTC3300-2

BALANCER

V–

•

V–

C6 C11

C10

33002 F01

V–

C12

LTC3300-2

BALANCER

LTC6803-2

MONITOR

LTC3300-2

BALANCER

V–

µP/µC

VCC

VEE

DIGITAL

ISOLATOR

DIGITAL

ISOLATOR

DIGITAL

ISOLATOR

DIGITAL

ISOLATOR

Figure 1. LTC3300-2/LTC6803-2 Typical Battery Management System (BMS)

OPERATION

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

OPERATION

charge from the highest voltage cell(s) in the stack to other

lower voltage cells in the stack (active balancing). This

can be very efficient (in terms of charge recovery) for the

case where only a few cells in the overall stack are high,

but will be very inefficient (and time consuming) for the

case where only a few cells in the overall stack are low. A

bidirectional active balancing approach, such as employed

by the LTC3300-2, is needed to achieve minimum balanc-

ing time and maximum charge recovery for all common

cell capacity errors.

VCC

ICHARGE

ISECONDARY

IPRIMARY

VPRIMARY

VSECONDARY

VTOP_OF_STACK

LPRI

10µH

G1P

I1P

RSNS_SEC

25mΩ

RSNS_PRI

25mΩ

G1S

I1S

ILOAD

(48V)

(4V)

T: 1•

•

5µs

Single-Cell Discharge Cycle for Cell 1 Single-Cell Charge Cycle for Cell 1

IPEAK_PRI = 2A

(I1P = 50mV)

IPRIMARY

5µs

–IPRIMARY

~417ns

–ISECONDARY

52V

52.05V

VPRIMARY

50mV

50mV 48V

48V

52V

VSECONDARY

~417ns

IPEAK_SEC = 2A

(I1S = 50mV)

ISECONDARY

33002 F02

52V 51.95V

VPRIMARY

50mV

48V

50mV

50mV 52V

48V

VSECONDARY

CELL 1

CELL 2

CELL 12

CELL 13

CELL N

Figure 2. Synchronous Flyback Balancing Example with T = 1, S = 12

Synchronous Flyback Balancer

The balancing architecture implemented by the LTC3300-2

is bidirectional synchronous flyback. Each LTC3300-2

contains six independent synchronous flyback controllers

that are capable of directly charging or discharging an

individual cell. Balance current is scalable with external

components. Each balancer operates independently of

the others and provides a means for bidirectional charge

transfer between an individual cell and a larger group of

adjacent cells. Refer to Figure 2.

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

OPERATION

Cell Discharging (Synchronous)

When discharging is enabled for a given cell, the primary

side switch is turned on and current ramps in the primary

winding of the transformer until the programmed peak

current (IPEAK_PRI) is detected at the InP pin. The primary

side switch is then turned off, and the stored energy in

the transformer is transferred to the secondary-side cells

causing current to flow in the secondary winding of the

transformer. The secondary-side synchronous switch

is turned on to minimize power loss during the transfer

period until the secondary current drops to zero (detected

at InS). Once the secondary current reaches zero, the

secondary switch turns off and the primary-side switch is

turned back on thus repeating the cycle. In this manner,

charge is transferred from the cell being discharged to

all of the cells connected between the top and bottom of

the secondary side—thereby charging the adjacent cells.

In the example of Figure 2, the secondary-side connects

across 12 cells including the cell being discharged.

IPEAK_PRI is programmed using the following equation:

IPEAK _PRI =

50mV

RSNS_PRI

Cell discharge current (primary side) and secondary-side

charge recovery current are determined to first order by

the following equations:

IDISCHARGE =

PEAK _PRI

S+T

⎛

⎝

⎜⎞

⎠

⎟

ISECONDARY =IPEAK _PRI

S+T

⎛

⎝

⎜⎞

⎠

⎟ηDISCHARG

where S is the number of secondary-side cells, 1:T is the

transformer turns ratio from primary to secondary, and

ηDISCHARGE is the transfer efficiency from primary cell

discharge to the secondary side stack.

Cell Charging

When charging is enabled for a given cell, the secondary-

side switch for the enabled cell is turned on and current flows

from the secondary-side cells through the transformer.

Once IPEAK_SEC is reached in the secondary side (detected

at the InS pin), the secondary switch is turned off and

current then flows in the primary side thus charging the

selected cell from the entire stack of secondary cells. As

with the discharging case, the primary-side synchronous

switch is turned on to minimize power loss during the cell

charging phase. Once the primary current drops to zero,

the primary switch is turned off and the secondary-side

switch is turned back on thus repeating the cycle.

IPEAK_SEC is programmed using the following equation:

IPEAK _SEC =

50mV

RSNS_SEC

Cell charge current and corresponding secondary-side

discharge current are determined to first order by the

following equations:

ICHARGE =

PEAK _ SEC

S+T

⎛

⎝

⎜⎞

⎠

⎟ηCHARGE

ISECONDARY =IPEAK _SEC

S+T

⎛

⎝

⎜⎞

⎠

⎟

where S is the number of secondary cells in the stack, 1:T

is the transformer turns ratio from primary to secondary,

and ηCHARGE is the transfer efficiency from secondary-side

stack discharge to the primary-side cell.

Each balancer’s charge transfer “frequency” and duty

factor depend on a number of factors including IPEAK_PRI,

IPEAK_SEC, transformer winding inductances, turns ratio,

cell voltage and the number of secondary-side cells.

The frequency of switching seen at the gate driver outputs

is given by:

fDISCHARGE =

S+T•

CELL

LPRI •IPEAK _PRI

fCHARGE =S

S+T•VCELL

LPRI •IPEAK _SEC • T

where LPRI is the primary winding inductance.

Figure 3 shows a fully populated LTC3300-2 application

employing all six balancers.

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

OPERATION

Figure 3. LTC3300-2 6-Cell Active Balancer Module Showing Power Connections for the Multi-Transformer Application (CTRL = V–)

1:1

•

25mΩ

10µH

CELL 6

UP TO

CELL 12

CELL 5

CELL 2

CELL 1

10µH

0.1µF

10µF

G6P

I6P

G6S

I6S

G5P

I5P

G5S

I5S

LTC3300-2

G2P

I2P

G2S

I2S

G1P

I1P

G1SVREG

BOOST I1S

RTONSRTONP

BOOST+

6.8Ω

BOOST–

CTRL V–

25mΩ

1:1

25mΩ

10µH10µH

25mΩ

1:1

25mΩ

10µH10µH

25mΩ

1:1

25mΩ

10µH10µH

25mΩ

6.98k

33002 F03

22.6k10µF

•

10µF

•

10µF

•

10µF

SERIAL

COMMUNICATION

PINS

CSBI

SCKI

SDI

SDO

WDT

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

Balancing High Voltage Battery Stacks

Balancing series connected batteries which contain >>12

cells in series requires interleaving of the transformer sec-

ondary connections in order to achieve full stack balancing

while limiting the breakdown voltage requirements of the

primary- and secondary-side power FETs. Figure 4 shows

typical interleaved transformer connections for a multicell

battery stack in the generic sense, and Figure 5 for the

specific case of an 18-cell stack. In these examples, the

secondary side of each transformer is connected to the

top of the cell that is 12 positions higher in the stack than

the bottom of the lowest voltage cell in each LTC3300-2

sub-stack. For the top most LTC3300-2 in the stack, it is

not possible to connect the secondary side of the trans-

former across 12 cells. Instead, it is connected to the top

of the stack, or effectively across only 6 cells. Interleaving

in this fashion allows charge to transfer between 6-cell

sub-stacks throughout the entire battery stack.

Max On-Time Volt-Sec Clamps

The LTC3300-2 contains programmable fault protection

clamps which limit the amount of time that current is

allowed to ramp in either the primary or secondary wind-

ings in the event of a shorted sense resistor. Maximum

on time for all primary connections (active during cell

discharging) and all secondary connections (active during

cell charging) is individually programmable by connecting

resistors from the RTONP and RTONS pins to V– according

to the following equations:

tON(MAX)|PRIMARY =7.2µs

TONP

20kΩ

tON(MAX)|SECONDARY =1.2µsRTONS

15kΩ

For more information on selecting the appropriate

maximum on-times, refer to the Applications Information

section.

To defeat this function, short the appropriate RTON pin(s)

to VREG.

OPERATION

Figure 4. Diagram of Power Transfer Interleaving Through the

Stack, Transformer Connections for High Voltage Stacks

•

LTC3300-2

POWER STAGES

LTC3300-2

POWER STAGES

FROM CELL N-12

SECONDARY

TO CELL 24

PRI SEC

•

LTC3300-2

POWER STAGES

•

SEC PRI

•

CELL 18

CELL 13

CELL 6

CELL 7

CELL 12

CELL N-6

CELL N

CELL 1

CELL 2

CELL 3

CELL 4

CELL 5

33002 F04

LTC3300-2

POWER STAGES

PRI

TOP

SEC

•

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

OPERATION

Figure 5. 18-Cell Active Balancer Showing Power Connections, Interleaved

Transformer Secondaries and BOOST+ Rail Generation Up the Stack

1:1

10µH

TO TRANSFORMER

SECONDARIES OF

BALANCERS 14 TO 18

10µH

CELL 18

25mΩ

G1P

I1P

G1S

I1S

VREG

V–

LTC3300-2

BOOST

BOOST+

BOOST–

0.1µF 6.8Ω

1:1

10µH

TO TRANSFORMER

SECONDARIES OF

BALANCERS 8 TO 12

10µH

25mΩ

G1P

I1P

G1S

I1S

V–

LTC3300-2

BOOST

BOOST+

1:1

10µH

TO TRANSFORMER

SECONDARIES OF

BALANCERS 2 TO 6

10µH

25mΩ

33002 F05

G1P

I1P

G1S

I1S

V–

LTC3300-2

BOOST

BOOST+

CELL 13

CELL 12

CELL 7

CELL 6

CELL 1

•

10µF

•

10µF

•

10µF

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

OPERATION

Gate Drivers/Gate Drive Comparators

All secondary-side gate drivers (G1S through G6S) are

powered from the VREG output, pulling up to 4.8V when

on and pulling down to V– when off. All primary-side

gate drivers (G1P through G6P) are powered from their

respective cell voltage and the next cell voltage higher in

the stack (see Table 1). An individual cell balancer will only

be enabled if its corresponding cell voltage is greater than

2V and the cell voltage of the next higher cell in the stack

is also greater than 2V. For the G6P gate driver output,

the next higher cell in the stack is C1 of the next higher

LTC3300-2 in the stack (if present) and is only used if the

boosted gate drive is disabled (by connecting BOOST =

V–). If the boosted gate drive is enabled (by connecting

BOOST = VREG), only the C6 cell voltage is looked at to

enable balancing of Cell 6. In the case of the topmost

LTC3300-2 in the stack, the boosted gate drive must be

enabled. The boosted gate drive requires an external diode

from C6 to BOOST+ and a boost capacitor from BOOST+ to

BOOST–. For information on selecting these components,

refer to the Applications Information section. Also note

that the dynamic supply current referred to in Note 4 of

the Electrical Characteristics table adds to the terminal

currents of the pins indicated in the Voltage When Off and

Voltage When On columns of Table 1.

The gate drive comparators have a DC hysteresis of 70mV.

For improved noise immunity, the inputs are internally

low pass filtered and the outputs are filtered so as to

not transition unless the internal comparator state is

unchanged for 3µs to 6µs (typical). If insufficient gate drive

is detected while active balancing is in progress (perhaps,

for example, if the stack is under heavy load), the affected

balancer(s) and only the affected balancer(s) will shut off.

The balance command remains stored in memory, and

active balancing will resume where it left off if sufficient

gate drive is subsequently restored. This can happen if,

for example, the stack is being charged.

Cell Overvoltage Comparators

In addition to sufficient gate drive being required to en-

able balancing, there are additional comparators which

disable all active balancing if any of the six individual cell

voltages is greater than 5V. These comparators have a

DC hysteresis of 500mV. For improved noise immunity,

the inputs are internally low pass filtered and the outputs

are filtered so as to not transition unless the internal

comparator state is unchanged for 3µs to 6µs (typical).

If any cell voltage goes overvoltage while active balanc-

ing is in progress, all active balancers will shut off. The

balance command remains stored in memory, and active

balancing will resume where if left off if the cell voltage

subsequently comes back in range. These comparators

will protect the LTC3300-2 if a connection to a battery is

lost while balancing and the cell voltage is still increasing

as a result of that balancing.

Voltage Regulator

A linear voltage regulator powered from C6 creates a

4.8V rail at the VREG pin which is used for powering

certain internal circuitry of the LTC3300-2 including all 6

secondary gate drivers. The VREG output can also be used

for powering external loads, provided that the total DC

loading of the regulator does not exceed 40mA at which

point current limit is imposed to limit on-chip power dis-

Table 1

DRIVER OUTPUT VOLTAGE WHEN OFF VOLTAGE WHEN ON GATE DRIVE REQUIRED TO ENABLE BALANCING

G1P V- C2 (C2 – C1) ≥ 2V and (C1 – V–) ≥2V

G2P C1 C3 (C3 – C2) ≥ 2V and (C2 – C1) ≥2V

G3P C2 C4 (C4 – C3) ≥ 2V and (C3 – C2) ≥2V

G4P C3 C5 (C5 – C4) ≥ 2V and (C4 – C3) ≥2V

G5P C4 C6 (C6 – C5) ≥ 2V and (C5 – C4) ≥2V

G6P C5 If BOOST = VREG: BOOST+ (Generated) (C6 – C5) ≥ 2V

If BOOST = V–: BOOST+ = C7* (C7* – C6) ≥ 2V and (C6 – C5) ≥ 2V

*C7 is equal to C1 of the next higher LTC3300-2 in the stack if this connection is used.

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

sipation. The internal component of the DC load current

is dominated by the average gate driver current(s) (G1S

through G6S), each approximated by C • V • f, where C

is the gate capacitance of the external NMOS transistor,

V = VREG = 4.8V, and f is the frequency that the gate

driver output is running at. FET manufacturers usually

specify the C • V product as Qg (gate charge) measured

in coulombs at a given gate drive voltage. The frequency,

f, is dependent on many terms, primarily the voltage of

each individual cell, the number of cells in the secondary

stack, the programmed peak balancing current, and the

transformer primary and secondary winding inductances.

In a typical application, the C • V • f current loading the

VREG output is expected to be low single-digit milliamperes

per driver. Note that the VREG loading current is ultimately

delivered from the C6 pin. For applications involving very

large balance currents and/or employing external NMOS

transistors with very large gate capacitance, the VREG

output may need to source more than 40mA average. For

information on how to design for these situations, refer

to the Applications Information section.

One additional function slaved to the VREG output is

the power-on reset (POR). During initial power-up and

subsequently if the VREG pin voltage ever falls below ap-

proximately 4V (e.g., due to overloading), the serial port

is cleared to the default power-up state with no balancers

active. This feature thus guarantees that the minimum gate

drive provided to the external secondary side FETs is also

4V. For a 10µF capacitor loading the output at initial power-

up, the output reaches regulation in approximately 1ms.

Thermal Shutdown

The LTC3300-2 has an overtemperature protection circuit

which shuts down all active balancing if the internal silicon

die temperature rises to approximately 155°C. When in

thermal shutdown, all serial communication remains active

and the cell balancer status (which contains temperature

information) can be read back. The balance command

which had been being executed remains stored in memory.

This function has 10°C of hysteresis so that when the die

temperature subsequently falls to approximately 145°C,

active balancing will resume with the previously execut-

ing command.

Watchdog Timer Circuit

The watchdog timer circuit provides a means of shutting

down all active balancing in the event that communication

to the LTC3300-2 is lost. The watchdog timer initiates

when a balance command begins executing and is reset

to zero every time a valid 8-bit command byte (see Serial

Port Operation) is written. The valid command byte can

be an execute, a write, or a read (command or status).

“Partial” reads and writes are considered valid, i.e., it is

only necessary that the first 8 bits have to be written and

contain the correct address.

Referring to Figure 6a, at initial power-up and when not

balancing, the WDT pin is high impedance and will be

pulled high (internally clamped to ~5.6V) if an external

pull-up resistor is present. While balancing and during

normal communication activity, the WDT pin is pulled

low by a precision current source equal to 1.2V/RTONS.

(Note: if the secondary volt-second clamp is defeated

by connecting RTONS to VREG, the watchdog function is

also defeated.) If no valid command byte is written for

1.5 seconds (typical), the WDT output will go back high.

When WDT is high, all balancers will be shut down but

the previously executing balance command still remains

in memory. From this timed-out state, a subsequent valid

command byte will reset the timer, but the balancers will

only restart if an execute command is written. To defeat

the watchdog function, simply connect the WDT pin to V–.

Pause/Resume Balancing (via WDT Pin)

The WDT output pin doubles as a logic input (TTL levels)

which can be driven by an external logic gate as shown in

Figure 6b (no watchdog), or by a PMOS/three-state logic

gate as shown in Figure 6c (with watchdog) to pause and

resume balancing in progress. The external pull-up must

have sufficient drive capability to override the current source

to ground at the WDT pin (= 1.2V/RTONS). Provided that

the internal watchdog timer has not independently timed

out, externally pulling the WDT pin high will immediately

pause balancing, and it will resume where it left off when

the pin is released.

OPERATION

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

OPERATION

ACTIVE 5.6V

LTC3300-2

VREG

WDT

RTONS

33002 F06a

V–

1.2V

RTONS

RWDT

ACTIVE 5.6V

LTC3300-2VTH = 1.4V

VREG

WDT

RTONS

PAUSE/

RESUME

33002 F06b

1.2V

RTONS

ACTIVE 5.6V

VREG

TO TRANSFORMER

SECONDARY WINDINGS

LTC3300-2

WDT

RTONS

VREG

PAUSE/

RESUME

EITHER/OR

PAUSE/

RESUME

33002 F06c

1.2V

RTONS

RSEC_OVP

(6a) Watchdog Timer Only (WDT = V– to Defeat) (6b) Pause/Resume Balancing Only

(6c) Watchdog Timer with Pause/Resume Balancing and Secondary Winding OVP Protection

Figure 6. WDT Pin Connection Options

Secondary Winding OVP Function (via WDT pin)

The precision current source pull-down on the WDT pin

during balancing can be used to construct an accurate

secondary winding OVP protection circuit as shown in

Figure 6c. A second external resistor, scaled to RTONS

and connected to the transformer secondary winding, is

used to set the comparator threshold. An NMOS cascode

device (with gate tied to VREG) is also needed to protect

the WDT pin from high voltage. The secondary winding

OVP thresholds are given by:

VSEC|OVP(RISING) = 1.4V + 1.2V • (RSEC_OVP/RTONS)

VSEC|OVP(FALLING) = 1.4V + 1.05V • (RSEC_OVP/RTONS)

This comparator will protect the LTC3300-2 application

circuit if the secondary winding connection to the battery

stack is lost while balancing and the secondary winding

voltage is still increasing as a result of that balancing. The

balance command remains stored in memory, and active

balancing will resume where it left off if the stack voltage

subsequently falls to a safer level.

Single Transformer Application (CTRL = VREG)

Figure 7 shows a fully populated LTC3300-2 application

employing all six balancers with a single shared custom

transformer. In this application, the transformer has six

primary windings coupled to a single secondary winding.

Only one balancer can be active at a given time as all six

share the secondary gate driver G1S and secondary current

sense input I1S. The unused gate driver outputs G2S-G6S

must be left floating and the unused current sense inputs

I2S-I6S should be connected to V–. Any balance command

which attempts to operate more than one balancer at a time

will be ignored. This application represents the minimum

component count active balancer achievable.

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

OPERATION

Figure 7. LTC3300-2 6-Cell Active Balancer Module Showing Power Connections for the Single Transformer Application (CTRL = VREG)

10µH

EACH

1:1 •

UP TO CELL 12

•

25mΩ

CELL 6

10µH

25mΩ

CELL 5

10µH

•

25mΩ

CELL 4

25mΩ

CELL 3

25mΩ

CELL 2

25mΩ

CELL 1

33002 F07

6.98k

+25mΩ

22.6k10µF

BOOST+

G6P

I6P

G5P

I5P

G4P

I4P

G3P

I3P

G2P

LTC3300-2

I2P

G1P

G1S

I1S

G2S-G6S

I2S-I6S

V–

CTRL

BOOST

VREG

10µF

I1P

BOOST–

RTONSRTONP

0.1µF 6.8Ω

SERIAL

COMMUNICATION

PINS

10µF

CSBI

SCKI

SDI

SDO

WDT

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

CSBI

SCKI

SDI MSB (CMD) LSB (CMD)

33002 F08

CSBI

SCKI

SDI MSB (CMD) LSB (CMD) LSB (DATA)

MSB (DATA)

(8a) Transmission Format (Write)

(8b) Transmission Format (Read)

LSB (DATA)

MSB (DATA)SDO

Figure 8.

OPERATION

SERIAL PORT OPERATION

Overview

The LTC3300-2 has an SPI bus compatible serial port.

Devices can be connected in parallel, using digital isolators.

Multiple devices are uniquely identified by a part address

determined by the A0 to A4 pins.

Physical Layer

On the LTC3300-2, four pins comprise the serial interface:

CSBI, SCKI, SDI and SDO. The SDO and SDI pins may

be tied together, if desired, to form a single bidirectional

port. Five address pins (A0 to A4) set the part address.

All serial communication related pins are voltage mode

with voltage levels referenced to the VREG and V– supplies.

Data Link Layer

Clock Phase and Polarity:

The LTC3300-2 SPI-compatible

interface is configured to operate in a system using

CPHA = 1 and CPOL = 1. Consequently, data on SDI must

be stable during the rising edge of SCKI.

Data Transfers:

Every byte consists of 8 bits. Bytes are

transferred with the most significant bit (MSB) first. On a

write, the data value on SDI is latched into the device on

the rising edge of SCKI (Figure 8a). Similarly, on a read,

the data value on SDO is valid during the rising edge of

SCKI and transitions on the falling edge of SCKI (Figure 8b).

CSBI must remain low for the entire duration of a com-

mand sequence, including between a command byte and

subsequent data. On a write command, data is latched in

on the rising edge of CSBI.

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

OPERATION

Command Byte

All communication to the LTC3300-2 takes place with CSBI

logic low. The first 8 clocked in data bits after a high-to-

low transition on CSBI represent the command byte. The

8-bit command byte is written MSB first per Table 2. The

first 5 bits must match the fixed pin-strapped address

[A4 A3 A2 A1 A0] for the individual device, or all sub-

sequent data will be ignored until CSBI transitions high

and then low again. The 6th and 7th bits program one of

four commands as shown in Table 3. The 8th bit in the

command byte must be set such that the entire 8-bit com-

mand byte has even parity. If the parity is incorrect, the

current balance command being executed (from the last

previously successful write) is terminated immediately and

all subsequent (write) data is ignored until CSBI transi-

tions high and then low again. Incorrect parity takes this

action whether or not the address matches. This thereby

provides a fast means to immediately terminate balancing-

in-progress by intentionally writing a command byte with

incorrect parity.

Table 2. Command Byte Bit Mapping

(Defaults to 0x00 in Reset State)

(MSB)

A3 A2 A1 A0 CMDA CMDB Parity Bit

(LSB)

Table 3. Command Bits

CMDA CMDB COMMUNICATION ACTION

0 0 Write Balance Command (without Executing)

0 1 Readback Balance Command

1 0 Read Balance Status

1 1 Execute Balance Command

Write Balance Command

If the command bits program Write Balance Command,

all subsequent write data must be exactly 16 bits (before

CSBI transitions high) or it will be ignored. The internal

command holding register will be cleared which can be

verified on readback. The current balance command being

executed (from the last previously successful write) will

continue, but all active balancing will be turned off if an

Execute Balance Command is subsequently written. Only

the individual LTC3300-2 in the stack with the matching

address will load in the write data. The 16-bit write balance

command is written MSB first per Table 4.

The first 12 bits of the 16-bit balance command are used

to indicate which balancer (or balancers) is active and in

which direction (charge or discharge). Each of the 6 cell

balancers is controlled by 2 bits of this data per Table 5.

The balancing algorithm for a given cell is:

Charge Cell n: Ramp up to IPEAK in secondary winding,

ramp down to IZERO in primary winding. Repeat.

Discharge Cell n (Synchronous): Ramp up to Ipeak in

primary winding, ramp down to IZERO in secondary

winding. Repeat.

Table 5. Cell Balancer Control Bits

DnA DnB BALANCING ACTION (n = 1 to 6)

0 0 None

0 1 Discharge Cell n (Nonsynchronous)

1 0 Discharge Cell n (Synchronous)

1 1 Charge Cell n

Table 4. Write Balance Command Data Bit Mapping (Defaults to 0x000F in Reset State)

D1A

(MSB)

D1B D2A D2B D3A D3B D4A D4B D5A D5B D6A D6B CRC[3] CRC[2] CRC[1] CRC[0]

(LSB)

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

OPERATION

For nonsynchronous discharging of cell n, both the sec-

ondary winding gate drive and (zero) current sense amp

are disabled. The secondary current will conduct either

through the body diode of the secondary switch (if pres-

ent) or through a substitute Schottky diode. The primary

will only turn on again after the secondary winding Volt-

sec clamp times out. In a bidirectional application with a

secondary switch, it may be possible to achieve slightly

higher discharge efficiency by opting for nonsynchronous

discharge mode (if the gate charge savings exceed the

added diode drop losses) but the balancing current will be

less predictable because the secondary winding Volt-sec

clamp must be set longer than the expected time for the

current to hit zero in order to guarantee no current rever-

sal. In the case where a Schottky diode replaces the sec-

ondary switch, it is possible to build a undirectional

discharge-only balancing application charging an isolated

auxiliary cell as shown in Figure 16 in the Typical Applica-

tions section.

In the CTRL = 1 application of Figure 7 employing a single

transformer which can only balance one cell at a time,

any command requesting simultaneous balancing of more

than one cell will be ignored. All active balancing will be

turned off if an Execute Balance Command is subse-

quently written.

The last 4 bits of the 16-bit balance command are used

for packet error checking (PEC). The 16 bits of write data

(12-bit message plus 4-bit CRC) are input to a cyclic re-

dundancy check (CRC) block employing the International

Telecommunication Union CRC-4 standard characteristic

polynomial:

x4 + x + 1

In the write data, the 4-bit CRC appended to the message

must be selected such that the remainder of the CRC divi-

sion is zero. Note that the CRC bits in the Write Balance

Command are inverted. This was done so that an “all zeros”

command is invalid. The LTC3300-2 will ignore the write

data if the remainder is not zero and the internal command

holding register will be cleared which can be verified on

readback. The current balance command being executed

(from the last previously successful write) will continue,

but all active balancing will be turned off if an Execute Bal-

ance Command is subsequently written. For information

on how to calculate the CRC including an example, refer

to the Applications Information section.

Readback Balance Command

The bit mapping for Readback Balance Command is identi-

cal to that for Write Balance Command. If the command

bits program Readback Balance Command, the 16 bits of

previously written data (latched in 12-bit message plus

newly calculated 4-bit CRC) are shifted out in the same

order bitwise (MSB first) per Table 4. Only the individ-

ual LTC3300-2 in the stack with the matching address

will send out the read data. This command allows for

microprocessor verification of written commands before

executing. Note that the CRC bits in the Readback Balance

Command are also inverted. This was done so that an “all

zeros” readback is invalid.

Read Balance Status

If the command bits program Read Balance Status, 16 bits

of status data (12 bits of data plus associated 4-bit CRC)

are shifted out MSB first per Table 6. Similar to a Readback

Balance Command, the last 4 bits in each 16-bit balance

status are used for error detection. The first 12 bits of

the status are input to a cyclic redundancy check (CRC)

block employing the same characteristic polynomial used

for write commands. The LTC3300-2 will calculate and

append the appropriate 4-bit CRC to the outgoing 12-bit

message which can then be used for microprocessor er-

Table 6. Read Balance Status Data Bit Mapping (defaults to 0x000F in Reset State)

Gate

Drive 1

(MSB)

Gate

Drive 2

Gate

Drive 3

Gate

Drive 4

Gate

Drive 5

Gate

Drive 6

Cells

Not OV

Sec

Not OV

Temp

00 0 CRC[3] CRC[2] CRC[1] CRC[0]

(LSB)

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

OPERATION

ror checking. Only the individual LTC3300-2 in the stack

with the matching address will send out the status data.

Note that the CRC bits in the Read Balance Status are

inverted. This was done so that an “all zeros” readback

is invalid.

The first 6 bits of the read balance status indicate if there

is sufficient gate drive for each of the 6 balancers. These

bits correspond to the right-most column in Table 1, but

can only be logic high for a given balancer following an

execute command involving that same balancer. If a bal-

ancer is not active, its Gate Drive OK bit will be logic low.

The 7th, 8th, and 9th bits in the read balance status indicate

that all 6 cells are not overvoltage, that the transformer

secondary is not overvoltage, and that the LTC3300-2 die

is not overtemperature, respectively. These 3 bits can only

be logic high following an execute command involving at

least one balancer. The 10th, 11th, and 12th bits in the

read balance status are currently not used and will always

be logic zero. As an example, if balancers 1 and 4 are both

active with no voltage or temperature faults, the 12-bit

read balance status should be 100100111000.

Execute Balance Command

If the command bits program Execute Balance Command,

the last successfully written and latched in balance com-

mand will be executed immediately. All subsequent (write)

data will be ignored until CSBI transitions high and then

low again.

Pause/Resume Balancing (via SPI Port)

The LTC3300-2 provides a simple means to interrupt bal-

ancing in progress (stack wide) and then restart without

having to rewrite the previous balance command to all

LTC3300-2 ICs in the stack. To pause balancing, simply

write an 8-bit Execute Balance Command with incorrect

parity. To resume balancing, simply write an Execute Bal-

ance Command with the correct parity to each different

address. This feature is useful if precision cell voltage

measurements want to be performed during balancing

with the stack “quiet.” Immediate pausing of balancing

in progress will occur for any 8-bit Command Byte with

incorrect parity.

The restart time is typically 2ms which is the same as the

delayed start time after a new or different balance command

(tDLY_START). It is measured from the 8th rising SCKI edge

until the balancer turns on and is illustrated in G25 in the

Typical Performance Characteristics section.

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

APPLICATIONS INFORMATION

External Sense Resistor Selection

The external current sense resistors for both primary

and secondary windings set the peak balancing current

according to the following formulas:

RSENSE|PRIMARY =

50mV

IPEAK _PRI

RSENSE|SECONDARY =50mV

IPEAK _SEC

Balancer Synchronization

Due to the stacked configuration of the individual synchro-

nous flyback power circuits and the interleaved nature of

the gate drivers, it is possible at higher balance currents

for adjacent and/or penadjacent balancers within a group

of six to sync up. The synchronization will typically be to

the highest frequency of any active individual balancer and

can result in a slightly lower balance current in the other

affected balancer(s). This error will typically be very small

provided that the individual cells are not significantly out

of balance voltage-wise and due to the matched IPEAK/

IZERO’s and matched power circuits. Balancer synchro-

nization can be reduced by lowpass filtering the primary

and/or secondary current sense signals with a simple RC

network as shown in Figure 9. A good starting point for

the RC time constant is one-tenth of the on-time of the

associated switch (primary or secondary). In the case

of IPEAK sensing, phase lag associated with the lowpass

filter will result in a slightly lower voltage seen by the

LTC3300-2 compared to the true sense resistor voltage.

This error can be compensated for by selecting the R value

to add back this same drop using the typical current value

of 20µA out of the LTC3300-2 current sense pins at the

comparator trip point.

Setting Appropriate Max On-Times

The primary and secondary winding volt-second clamps

are intended to be used as a current runaway protection

feature and not as a substitute means of current control

replacing the sense resistors. In order to not interfere with

normal IPEAK/IZERO operation, the maximum on times must

be set longer than the time required to ramp to IPEAK (or

IZERO) for the minimum cell voltage seen in the application:

tON(MAX)|PRIMARY > LPRI • IPEAK_PRI/VCELL(MIN)

tON(MAX)|SECONDARY > LPRI • IPEAK_SEC • T/(S • VCELL(MIN))

These can be further increased by 20% to account for

manufacturing tolerance in the transformer winding

inductance and by 10% to account for IPEAK variation.

External FET Selection

In addition to being rated to handle the peak balancing

current, external NMOS transistors for both primary and

secondary windings must be rated with a drain-to-source

breakdown such that for the primary MOSFET:

VDS(BREAKDOWN)|MIN >VCELL +

STACK

DIODE

=VCELL 1+S

⎛

⎝

⎜⎞

⎠

⎟+VDIODE

and for the secondary MOSFET:

VDS(BREAKDOWN)|MIN >VSTACK +T VCELL +VDIODE

( )

=VCELL S+T

( )

+T VDIODE

where S is the number of cells in the secondary winding

stack and 1:T is the transformer turns ratio from primary

to secondary. For example, if there are 12 Li-Ion cells in

the secondary stack and using a turns ratio of 1:2, the

primary FETs would have to be rated for greater than 4.2V

(1 + 6) + 0.5 = 29.9V and the secondary FETs would have

to be rated for greater than 4.2V (12 + 2) + 2V = 60.8V.

LTC3300-2

n = 2 TO 6

20µA R

SNS

33002 F09

G1P/GnP/G1S/GnS

I1P/InP/I1S/InS

–

/Cn – 1/V

–

Figure 9. Using an RC Network to Filter

Current Sense Inputs to the LT C 3300-2

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

APPLICATIONS INFORMATION

Good design practice recommends increasing this voltage

rating by at least 20% to account for higher voltages present

due to leakage inductance ringing. See Table 7 for a list of

FETs that are recommended for use with the LTC3300-2.

Table 7

PART NUMBER MANUFACTURER IDS(MAX) VDS(MAX)

SiR882DP Vishay 60A 100V

SiS892DN Vishay 25A 100V

IPD70N10S3-12 Infineon 70A 100V

IPB35N10S3L-26 Infineon 35A 100V

RJK1051DPB Renesas 60A 100V

RJK1054DPB Renesas 92A 100V

Transformer Selection

The LTC3300-2 is optimized to work with simple 2-wind-

ing transformers with a primary winding inductance of

between 1 and 20 microhenries, a 1:2 turns ratio (primary

to secondary), and the secondary winding paralleling up

to 12 cells. If a larger number of cells in the secondary

stack is desired for more efficient balancing, a transformer

with a higher turns ratio can be selected. For example, a

1:10 transformer would be optimized for up to 60 cells in

the secondary stack. In this case the external FETs would

need to be rated for a higher voltage (see above). In all

cases the saturation current of the transformer must be

selected to be higher than the peak currents seen in the

application.

See Table 8 for a list of transformers that are recommended

for use with the LTC3300-2.

Table 8

PART NUMBER MANUFACTURER

TURNS

RATIO*

PRIMARY

INDUCTANCE ISAT

750312504 (SMT) Würth Electronics 1:1 3.5µH 10A

750312677 (THT) Würth Electronics 1:1 3.5µH 10A

MA5421-AL Coilcraft 1:1 3.4µH 10A

CTX02-18892-R Coiltronics 1:1 3.4µH 10A

XF0036-EP13S XFMRS Inc 1:1 3µH 10A

LOO-3218 BH Electronics 1:1 3.4µH 10A

DHCP-X79-1001 TOKO 1:1 3.4µH 10A

C128057LF GCI 1:1 3.4µH 10A

T10857-1 Inter Tech 1:1 3.4µH 10A

*All transformers listed in the table are 8-pin components and can be

configured with turns ratios of 1:1, 1:2, 2:1, or 2:2.

Snubber Design

Careful attention must be paid to any transient ringing

seen at the drain voltages of the primary and secondary

winding FETs in application. The peak of the ringing should

not approach and must not exceed the breakdown voltage

rating of the FETs chosen. Minimizing leakage inductance

present in the application and utilizing good board layout

techniques can help mitigate the amount of ringing. In

some applications, it may be necessary to place a series

resistor + capacitor snubber network in parallel with each

winding of the transformer. This network will typically

lower efficiency by a few percent, but will keep the FETs

in a safer operating region. Determining values for R and

C usually requires some trial-and-error optimization in the

application. For the transformers shown in Table 8, good

starting point values for the snubber network are 330Ω

in series with 100pF.

Boosted Gate Drive Component Selection

(BOOST = VREG)

The external boost capacitor connected from BOOST+ to

BOOST– supplies the gate drive voltage required for turning

on the external NMOS connected to G6P. This capacitor

is charged through the external Schottky diode from C6

to BOOST+ when the NMOS is off (G6P = BOOST– = C5).

When the NMOS is to be turned on, the BOOST– driver

switches the lower plate of the capacitor from C5 to C6,

and the BOOST+ voltage common modes up to one cell

voltage higher than C6. When the NMOS turns off again,

the BOOST– driver switches the lower plate of the capaci-

tor back to C5 so that the boost capacitor is refreshed.

A good rule of thumb is to make the value of the boost

capacitor 100 times that of the input capacitance of the

NMOS at G6P. For most applications, a 0.1µF/10V capacitor

will suffice. The reverse breakdown of the Schottky diode

must only be greater than 6V. To prevent an excessive and

potentially damaging surge current from flowing in the

boosted gate drive components during initial connection of

the battery voltages to the LTC3300-2, it is recommended

to place a 6.8Ω resistor in series with the Schottky diode

as shown in Figure 3. The surge current must be limited

to 1A to avoid potential damage.

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

APPLICATIONS INFORMATION

Sizing the Cell Bypass Caps for Broken Connection

Protection

If a single connection to the battery stack is lost while bal-

ancing, the differential cell voltages seen by the LTC3300-2

power circuit on each side of the break can increase or

decrease depending on whether charging or discharging

and where the actual break occurred. The worst-case

scenario is when the balancers on each side of the break

are both active and balancing in opposite directions. In

this scenario, the differential cell voltage will increase

rapidly on one side of the break and decrease rapidly

on the other. The cell overvoltage comparators working

in conjunction with appropriately-sized differential cell

bypass capacitors protect the LTC3300-2 and its asso-

ciated power components by shutting off all balancing

before any local differential cell voltage reaches its abso-

lute maximum rating. The comparator threshold (rising)

is 5V, and it takes 3µs to 6μs for the balancing to stop,

during which the bypass capacitor must prevent the dif-

ferential cell voltage from increasing past 6V. Therefore,

the minimum differential bypass capacitor value for full

broken connection protection is:

CBYPASS(MIN) =ICHARGE +IDISCHARGE

( )

•6µs

6V – 5V

If ICHARGE and IDISCHARGE are set nominally equal, then

approximately 12µF of real capacitance per amp of balance

current is required.

Protection from a broken connection to a cluster of sec-

ondary windings is provided local to each LTC3300-2 in

the stack by the secondary winding OVP function (via

WDT pin) described in the Operation section. However,

because of the interleaving of the transformer windings

up the stack, it is possible for a remote LTC3300-2 to still

act on the cell voltage seen locally by another LTC3300-2

at the point of the break which has shut itself off. For this

reason, each cluster of secondary windings must have

a dedicated connection to the stack separate from the

individual cell connection that it connects to.

Using the LTC3300-2 with Fewer Than 6 Cells

To balance a series stack of N cells, the required number

of LTC3300-2 ICs is N/6 rounded up to the nearest integer.

Since the LTC3300-2 address is 5 bits, the maximum N can

be is 192 cells. Additionally, each LTC3300-2 in the stack

must interface to a minimum of 3 cells (must include C4,

C5, and C6). Thus, any stack of between 3 and 192 cells

can be balanced using an appropriate stack of LTC3300-2

ICs. Unused cell inputs (C1, C1 + C2, or C1 + C2 + C3) in a

given LTC3300-2 sub-stack should be shorted to V– (see

Figure 10). However, in all configurations, the write data

remains at 16 bits. The LTC3300-2 will not act on the cell

balancing bits for the unused cell(s) but these bits are still

included in the CRC calculation.

Figure 10. Battery Stack Connections for 5, 4 or 3 Cells

+CELL n + 4

•

+CELL n + 3

+CELL n + 2

+CELL n + 1

+CELL n

LTC3300-2

(10a) Sub-Stack Using Only 5 Cells (10b) Sub-Stack Using Only 4 Cells (10c) Sub-Stack Using Only 3 Cells

V–

•

CELL n + 3

CELL n + 2

CELL n + 1

CELL n

LTC3300-2

V–

•

CELL n + 2

CELL n + 1

CELL n

33002 F10

LTC3300-2

V–

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

APPLICATIONS INFORMATION

Figure 11. Adding External Buck DC/DC for >40mA VREG Drive

4.8V

LINEAR

VOLTAGE

REGULATOR

VREG

COUT

RFB2

V–

LTC3300-2

IOUT > 40mA

RFB1

CIN

33002 F11

GND

VIN

BUCK

DC/DC

Supplementary Voltage Regulator Drive (>40mA)

The 4.8V linear voltage regulator internal to the LTC3300-2

is capable of providing 40mA at the VREG pin. If additional

current capability is required, the VREG pin can be back-

driven by an external low cost 5V buck DC/DC regulator

powered from C6 as shown in Figure 11. The internal

regulator of the LTC3300-2 has very limited sink current

capability and will not fight the higher forced voltage.

Fault Protection

Care should always be taken when using high energy

sources such as batteries. There are numerous ways

that systems can be misconfigured when considering

the assembly and service procedures that might affect a

battery system during its useful lifespan. Table 9 shows

the various situations that should be considered when

planning protection circuitry. The first four scenarios

are to be anticipated during production and appropriate

protection is included within the LTC3300-2 device itself.

Table 9. LTC3300-2 Failure Mechanism Effect Analysis

SCENARIO EFFECT DESIGN MITIGATION

Top cell (C6) input connection loss to LTC3300-2. Power will come from highest connected cell

input or via data port fault current.

Clamp diodes at each pin to C6 and V– (within IC)

provide alternate power path. Diode conduction at

data ports will impair communication with higher

potential units.

Bottom cell (V–) input connection loss to

LTC3300-2.

Power will come from lowest connected cell

input or via data port fault current.

Clamp diodes at each pin to C6 and V– (within IC)

provide alternate power path. Diode conduction at

data ports will impair communication with higher

potential units.

Random cell (C1-C5) input connection loss to

LTC3300-2.

Power-up sequence at IC inputs/differential

input voltage overstress.

Clamp diodes at each pin to C6 and V– (within IC)

provide alternate power path. Zener diodes across

each cell voltage input pair (within IC) limit stress.

Disconnection of a harness between a sub-stack

of battery cells and the LTC3300-2 (in a system of

stacked groups).

Loss of all supply connections to the IC. Clamp diodes at each pin to C6 and V– (within

IC) provide alternate power path if there are other

devices (which can supply power) connected to

the LTC3300-2.

Secondary winding connection loss to battery

stack.

Secondary winding power FET could be

subjected to a higher voltage as bypass

capacitor charges up.

WDT pin implements a secondary winding OVP

circuit which will detect overvoltage and terminate

balancing.

Shorted primary winding sense resistor. Primary winding peak current cannot be

detected to shut off primary switch.

Maximum ON-time set by RTONP resistor will shut

off primary switch if peak current detect doesn’t

occur.

Shorted secondary winding sense resistor. Secondary winding peak current cannot be

detected to shut off secondary switch.

Maximum ON-time set by RTONS resistor will

shut off secondary switch if peak current detect

doesn’t occur.

Data error (noise margin induced or otherwise)

occurs during a write command.

Incoming checksum will not agree with the

incoming message when read in by any

individual LTC3300-2 in the stack.

Since the CRC remainder will not be zero, the

LTC3300-2 will not execute the write command,

even if an execute command is given. All

balancers with nonzero remainders will be off.

Data error (noise margin induced or otherwise)

occurs during a read command.

Outgoing checksum (calculated by the

LTC3300-2) will not agree with the

outgoing message when read in by the host

microprocessor.

Since the CRC remainder (calculated by the

host) will not be zero, the data cannot be trusted.

All balancers will remain in the state of the last

previously successful write.

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

APPLICATIONS INFORMATION

Internal Protection Diodes

Each pin of the LTC3300-2 has protection diodes to help

prevent damage to the internal device structures caused

by external application of voltages beyond the supply rails

as shown in Figure 12. The diodes shown are conventional

silicon diodes with a forward breakdown voltage of 0.5V.

The unlabeled Zener diode structures have a reverse-

breakdown characteristic which initially breaks down at

9V then snaps back to a 7V clamping potential. The Zener

diodes labeled ZCLAMP are higher voltage devices with an

initial reverse breakdown of 25V snapping back to 22V.

The forward voltage drop of all Zeners is 0.5V.

The internal protection diodes shown in Figure 12 are

power devices which are intended to protect against

limited-power transient voltage excursions. Given that

these voltages exceed the absolute maximum ratings of

the LTC3300-2, any sustained operation at these voltage

levels will damage the IC.

Initial Battery Connection to LTC3300-2

In addition to the above-mentioned internal protection

diodes, there are additional lower voltage/lower current

diodes across each of the six differential cell inputs (not

shown in Figure 12) which protect the LTC3300-2 during

initial installation of the battery voltages in the application.

These diodes have a breakdown voltage of 5.3V with 20kΩ

of series resistance and keep the differential cell voltages

below their absolute maximum rating during power-up

when the cell terminal currents are zero to tens of mi-

croamps. This allows the six batteries to be connected in

any random sequence without fear of an unconnected cell

input pin overvoltaging due to leakage currents acting on

its high impedance input. Differential cell-to-cell bypass

capacitors used in the application must be of the same

nominal value for full random sequence protection.

Analysis of Stack Terminal Currents in Shutdown

As given in the Electrical Characteristics table, the quiescent

current of the LTC3300-2 when not balancing is 14μA at

the C6 pin and zero at the C1 through C5 pins. All of this

14μA shows up at the V– pin of the LTC3300-2. To the

extent that the 14μA currents match perfectly chip-to-chip

in a long series stack, the resultant stack terminal currents

in shutdown are as follows: 14μA out of the top of stack

node and 14μA into the bottom of stack node. All other

intermediate node currents are zero.

Differences Between LTC3300-2 and LTC3300-1

The LTC3300-1 employs an SPI-compatible serial interface

in which each IC in the stack communicates bidirectionally

to the ICs of the same type above and below it via currents.

There is no limit to the stack height. Large common mode

voltage differences are handled by each LTC3300-1. The

microprocessor in the BMS system communicates ONLY

with the bottom IC in the stack and subsequently all of

the ICs use the same fixed internal address.

The LTC3300-2 employs an SPI-compatible serial interface

in which each IC has a unique 5-bit pin-strapped address.

The microprocessor in the BMS system communicates

directly with every IC in the stack with common mode

voltage differences handled by digital isolators or opto-

couplers. Because of the 5-bit address, the stack height is

limited to 32 LTC3300-2 ICs or 192 cells (~800V).

There are 5 pins which have a different assignment, all of

them serial interface related.

See Table 10 for a summary of differences between

LTC3300-1 and LTC3300-2

Table 10. LTC3300-1 vs LTC3300-2 Differences

LTC3300-1 LTC3300-2

High Side Current Mode SPI Pins CSBO, SCKO,

SDOI

None

“Where Am I in The Stack?” Pins VMODE, TOS None*

SPI Address 10101 (Fixed) A4A3A2A1A0

(Pin Strapped)

Maximum Height of Battery Stack Unlimited 32 × 6 = 192 Cells

GND (V–) Pin Current in

Shutdown/Suspend

23.5µA 14µA

*LTC3300-2 has VMODE = TOS = 1 fixed internally. Each IC in the stack

thinks it is both top-of-stack and bottom-of-stack. Consequently, opto-

couplers or digital isolators are needed to communicate between the µP

and each IC.

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

Figure 12. Internal Protection Diodes

APPLICATIONS INFORMATION

VREG

WDT

SDO

SDI

SCKI

CSBI

LTC3300-2

44 A1

45 A2

46 A3

43 A0

40 BOOST+

41 BOOST–

38 G6P

37 I6P

39 C6

BOOST

CTRL

RTONP

RTONS

G6S

I6S

G5S

I5S

G4S

I4S

G3S

I3S

G2S

ZCLAMP

I2S

G1S

I1S

33002 F12

35 G5P

34 I5P

32 G4P

31 I4P

29 G3P

28 I3P

26 G2P

25 I2P

23 G1P

22 I1P

4Ω

EXPOSED PAD

V–

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

APPLICATIONS INFORMATION

How to Calculate the CRC

One simple method of computing an n-bit CRC is to perform

arithmetic modulo-2 division of the n+1 bit characteristic

polynomial into the m bit message appended with n ze-

ros (m+n bits). Arithmetic modulo-2 division resembles

normal long division absent borrows and carries. At each

intermediate step of the long division, if the leading bit

of the dividend is a 1, a 1 is entered in the quotient and

the dividend is exclusive-ORed bitwise with the divisor.

If the leading bit of the dividend is a 0, a 0 is entered in

the quotient and the dividend is exclusive-ORed bitwise

with n zeros. This process is repeated m times. At the end

of the long division, the quotient is disregarded and the

n-bit remainder is the CRC. This will be more clear in the

example to follow.

For the CRC implementation in the LTC3300-2, n = 4 and

m = 12. The characteristic polynomial employed is x4 + x

+ 1, which is shorthand for 1x4 + 0x3 + 0x2 + 1x1 + 1x0,

resulting in 10011 for the divisor. The message is the first

12 bits of the balance command. Suppose for example the

desired balance command calls for simultaneous charging

of Cell 1 and synchronous discharging of Cell4. The 12-bit

message (MSB first) will be 110000010000. Appending

4 zeros results in 1100000100000000 for the dividend.

The long division is shown in Figure 13a with a resultant

CRC of 1101. Note that the CRC bits in the write balance

command are inverted. Thus the correct 16-bit balance

command is 1100000100000010. Figure13b shows the

same long division procedure being used to check the

CRC of data (command or status) read back from the

LTC3300-2. In this scenario, the remainder after the long

division must be zero (0000) for the data to be valid. Note

that the readback CRC bits must be inverted in the dividend

before performing the division.

An alternate method to calculate the CRC is shown in

Figure 14 in which the balance command bits are input to

a combinational logic circuit comprised solely of 2-input

exclusive-OR gates. This “brute force” implementation is

easily replicated in a few lines of C code.

Figure 13. (a) Long Division Example to Calculate CRC for Writes.

(b) Long Division Example to Check CRC for Reads

1 1 0 1 0 1 1 0 1 0 1 1

1 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0

1 0 0 1 1

1 0 1 1 0

1 0 0 1 1

0 1 0 1 0

0 0 0 0 0

1 0 1 0 1

1 0 0 1 1

0 1 1 0 0

0 0 0 0 0

1 1 0 0 0

1 0 0 1 1

1 0 1 1 0

1 0 0 1 1

0 1 0 1 0

0 0 0 0 0

1 0 1 0 0

1 0 0 1 1

0 1 1 1 0

0 0 0 0 0

1 1 1 0 0

1 0 0 1 1

1 1 1 1 0

1 0 0 1 1

REMAINDER = 1 1 0 1 = 4-BIT CRC

1 1 0 1 0 1 1 0 1 0 1 1

1 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 1

1 0 0 1 1

1 0 1 1 0

1 0 0 1 1

0 1 0 1 0

0 0 0 0 0

1 0 1 0 1

1 0 0 1 1

0 1 1 0 0

0 0 0 0 0

1 1 0 0 0

1 0 0 1 1

1 0 1 1 0

1 0 0 1 1

0 1 0 1 0

0 0 0 0 0

1 0 1 0 1

1 0 0 1 1

0 1 1 0 1

0 0 0 0 0

1 1 0 1 0

1 0 0 1 1

REMAINDER = 0

33002 F13

0 0 1 0 = 4-BIT CRC INVERTED

READBACK = 1100000100000010

DIVIDEND = 1100000100001101

(b)(a)

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

APPLICATIONS INFORMATION

Serial Communication Using the LTC6803 and LTC6804

The LTC3300-2 is compatible with and convenient to

use with all LTC monitor chips, such as the LTC6803 and

LTC6804. Figure 17 in the Typical Applications section

shows the serial communications connections for a joint

LTC3300-2/LTC6803-2 BMS using a common micropro-

cessor SPI port. The SCKI, SDI, and SDO lines of the low-

ermost LTC3300-2 and LTC6803-2 are tied together. The

CSBI lines, however, must be separated to prevent talking

to both ICs at the same time. This is easily accomplished

by using one of the GPIO outputs from the LTC6803-2

to gate and invert the CSBI line to the LTC3300-2. In this

setup, communicating to the LTC6803-2 is no different

than without the LTC3300-2, as the GPIO1 output bit is

normally high. To talk to the LTC3300-2, written commands

must be “bookended” with a GPIO1 negation write to the

LTC6803-2 prior to talking to the LTC3300-2 and with

a GPIO1 assertion write after talking to the LTC3300-2.

Communication to all non-ground referred LTC3300-2 and

LTC6803-2 ICs is done through digital isolators.

The Typical Application shown on the back page of this

data sheet shows the serial communication connections

for a joint LTC3300-2/LTC6804-2 BMS. Each stacked

12-cell module contains two LTC3300-2 ICs and a single

LTC6804-2 monitor IC. . The LTC6804-2 in the module

is configured to provide an effective SPI port output at its

GPIO3, GPIO4, and GPIO5 pins which connect directly to

the low side communication pins (CSBI, SDI=SDO, SCKI)

of the lower LTC3300-2. The upper LTC3300-2 in each

module receives its serial communication via a digital

isolator from the lower LTC3300-2. Communication to

the lowermost LTC6804-2 and between monitor chips is

done via the LTC6820 and the isoSPI™ interface. In this

application, unused battery cells can be shorted from

the bottom of any module (i.e., outside the module, not

on the module board) as shown without any decrease in

monitor accuracy.

Figure 14. Combinational Logic Circuit Implementation of the CRC Calculator

CRC [3]

CRC [2]

CRC [1]

CRC [0]

33002 F14

D6B

“Ø”

D5B

D3B

D1B

D2A

D5A

D3A

D1A

D4B

D2B

D4A

D6A

CRC [2]

CRC [1]

CRC [0]

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

PCB Layout Considerations

The LTC3300-2 is capable of operation with as much as

40V between BOOST+ and V–. Care should be taken on

the PCB layout to maintain physical separation of traces

at different potentials. The pinout of the LTC3300-2 was

chosen to facilitate this physical separation. There is no

more than 8.4V between any two adjacent pins with the

exception of one instance (BOOST to BOOST–). In this

instance, the BOOST pin is pin-strapped in the applica-

tion to V– or VREG and does not need to route far from

the LTC3300-2. The package body is used to separate

the highest voltage (e.g., 25.2V) from the lowest voltage

(0V). As an example, Figure15 shows the DC voltage on

each pin with respect to V– when six 4.2V battery cells

are connected to the LTC3300-2.

Additional “good practice” layout considerations are as

follows:

1. The VREG pin should be bypassed to the exposed pad

and to V–, each with 1µF or larger capacitors as close

to the LTC3300-2 as possible.

APPLICATIONS INFORMATION

2. The differential cell inputs (C6 to C5, C5 to C4, …, C1 to

exposed pad) should be bypassed with a 1µF or larger

capacitor as close to the LTC3300-2 as possible. This

is in addition to bulk capacitance present in the power

stages.

3. Pin 21 (V–) is the ground sense for current sense resis-

tors connected to I1S-I6S and I1P (seven resistors).

Pin 21 should be Kelvined as well as possible with low

impedance traces to the ground side of these resistors

before connecting to the LTC3300-2 exposed pad.

4. Cell inputs C1 to C5 are the ground sense for current

sense resistors connected to I2P-I6P (five resistors).

These pins should be Kelvined as well as possible

with low impedance traces to the ground side of these

resistors.

5. The ground side of the maximum on-time setting resis-

tors connected to the RTONS and RTONP pins should

be Kelvined to Pin 21 (V–) before connecting to the

LTC3300-2 exposed pad.

6. Trace lengths from the LTC3300-2 gate drive outputs

(G1S-G6S and G1P-G6P) and current sense inputs

(I1S-I6S and I1P-I6P) should be as short as possible.

7. The boosted gate drive components (diode and ca-

pacitor), if used, should form a tight loop close to the

LTC3300-2 C6, BOOST+, and BOOST– pins.

8. For the external power components (transformer, FETs

and current sense resistors), it is important to keep the

area encircled by the two high speed current switching

loops (primary and secondary) as tight as possible.

This is greatly aided by having two additional bypass

capacitors local to the power circuit: one differential

cell to cell and one from the transformer secondary to

local V–.

A representative layout incorporating all of these recom-

mendations is implemented on the DC2064A demo board

for the LTC3300-1 companion product (with further ex-

planation in its accompanying demo board manual). To

accommodate the LTC3300-2, only minor modifications

to Pins 43 to 47 connections need to be made. PCB layout

files (.GRB) are also available from the factory.

Figure 15. Typical Pin Voltages for Six 4.2V Cells

LTC3300-2

(EXPOSED PAD = 0V)

0V TO 4.8V

21V

16.8V TO 25.2V

16.8V

12.6V TO 21V

12.6V

8.4V TO 16.8V

8.4V

4.2V TO 12.6V

4.2V

G6S—PIN 1

I6S

G5S

I5S

G4S

I4S

G3S

I3S

G2S

I2S

G1S

I1S

G5P

I5P

G4P

I4P

G3P

I3P

G2P

I2P

VREG

BOOST

BOOST–

BOOST+

G6P

I6P

1.2V

0V/4.8V

0V TO 4.8V

0V TO 8.4V

4.2V

RTONS

RTONP

CTRL

CSBI

SCKI

SDI

SDO

WDT

V–

I1P

G1P

4.8V

0V/4.8V

21V TO 25.2V

25.2V TO 29.4V

25.2V

21V TO 29.4V

21V

33002 F15

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

TYPICAL APPLICATIONS

1:1

•

25mΩ

10µH10µH

0.1µF

10µF

CELL 6

G6P

I6P

LTC3300-2

VREG

BOOST

RTONS ISOLATION

BOUNDARY

RTONP

BOOST+

6.8Ω

BOOST–

CTRL

V–

41.2k

33002 F16

28k10µF

•

25mΩ

10µH10µH

10µF

CELL 5

G5P

I5P

•

25mΩ

10µH10µH

10µF

CELL 2

G2P

I2P

•

25mΩ

10µH10µH

10µF

CELL 1

G1P

I1P

G1S-G6S

I1S-I6S

+ISOLATED

12V LEAD ACID

AUXILIARY

CELL

•

SERIAL

COMMUNICATION

PINS

CSBI

SCKI

SDI

SDO

WDT

Figure 16. LTC3300-2 Unidirectional Discharge-Only Balancing Application to Charge an Isolated Auxiliary Cell

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

TYPICAL APPLICATIONS

Figure 17. LT C 3300-2/LT C 6803-2 Battery and Serial Communication Connections for a 24-Cell Stack

VREG

CSBI

SCKI

SDI

SDO

GPIO2

GPIO1

CSBI

SCKI

SDI

SDO

C11

C10

C12

TOP OF BATTERY STACK

LTC3300-2

ADDRESS =

00011

LTC6803-2

ADDRESS = 0001

V–CVREG4

DIGITAL

ISOLATOR

CELL 24

+CELL 23

+CELL 22

+CELL 21

+CELL 20

+CELL 19

+CELL 18

+CELL 17

+CELL 16

+CELL 15

+CELL 14

+CELL 13

VREG

CSBI

SCKI

SDI

SDO

V–V–

CVREG3 CVREG6

33002 F17

GPIO2

GPIO1

CSBI

SCKI

SDI

SDO

C11

C10

C12

LTC6803-2

ADDRESS = 0000

CELL 12

+CELL 11

+CELL 10

+CELL 9

+CELL 8

+CELL 7

+CELL 6

+CELL 5

+CELL 4

+CELL 3

VREG1 VREG5

+CELL 2

+CELL 1

VREG

V–

CVREG5

CVREG2

VREG1 OR

VREG5

CVREG1

V1+V2+

V1–V2–

CLK

MOSI

MPU

DIGITAL

ISOLATOR

MOSO

DIGITAL

ISOLATOR

DIGITAL

ISOLATOR

DIGITAL

ISOLATOR

LTC3300-2

ADDRESS =

00010

VREG

CSBI

SCKI

SDI

SDO

V–

LTC3300-2

ADDRESS =

00001

VREG

CSBI

SCKI

SDI

SDO

V–

LTC3300-2

ADDRESS =

00000

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

7.00 ±0.10

(4 SIDES)

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

PIN 1 TOP MARK

(SEE NOTE 6)

PIN 1

CHAMFER

C = 0.35

0.40 ±0.10

4847

BOTTOM VIEW—EXPOSED PAD

5.50 REF

(4-SIDES)

0.75 ±0.05 R = 0.115

TYP

0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UK48) QFN 0406 REV C

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 ±0.05

5.50 REF

(4 SIDES) 6.10 ±0.05 7.50 ±0.05

0.25 ±0.05

0.50 BSC

PACKAGE OUTLINE

5.15 ±0.10

5.15 ±0.05

R = 0.10

TYP

UK Package

48-Lead Plastic QFN (7mm × 7mm)

(Reference LTC DWG # 05-08-1704 Rev C)

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

LXE48 LQFP 0113 REV C

0° – 7°

11° – 13°

0.45 – 0.75

1.00 REF

11° – 13°

1.60

MAX

1.35 – 1.45

0.05 – 0.150.09 – 0.20 0.50

BSC 0.17 – 0.27

GAUGE PLANE

0.25

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT

3. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER

4. DRAWING IS NOT TO SCALE

R0.08 – 0.20

7.15 – 7.25

5.50 REF

136

5.50 REF

7.15 – 7.25

13 24

C0.30

PACKAGE OUTLINE

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

BOTTOM OF PACKAGE—EXPOSED PAD (SHADED AREA)

SIDE VIEW

SECTION A – A

0.50 BSC

0.20 – 0.30

1.30 MIN

9.00 BSC

A A

7.00 BSC

7.00 BSC 3.60 ±0.10

3.60 ±0.10

9.00 BSC

48 37

1324

13 24

36 36

SEE NOTE: 3

C0.30 – 0.50

3.60 ±0.05

C0.30

LXE Package

48-Lead Plastic Exposed Pad LQFP (7mm × 7mm)

(Reference LTC DWG #05-08-1832 Rev C)

LTCXXXX

LX-ES

Q_ _ _ _ _ _

XXYY

TRAY PIN 1

BEVEL PACKAGE IN TRAY LOADING ORIENTATION

COMPONENT

PIN “A1”

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 12/13 Add new bullet Integrates Seamlessly with the LTC680x Family of Multicell Battery Stack Monitors

Change part number XF0036-EP135 to XF0036-EP13S

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

 LINEAR TECHNOLOGY CORPORATION 2013

LT 0813 • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3300-2

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC3300-1 High Efficiency Bidirectional Mulitcell Battery Balancer Allows Serial Ports of Multiple Devices to Be Daisy-Chained without

Opto-Couplers or Isolators

LTC6801 Independent Multicell Battery Stack Monitor Monitors Up to 12 Series-Connected Battery Cells for Undervoltage or

Overvoltage, Companion to LTC6802, LTC6803 and LTC6804

LTC6802-1/LTC6802-2 Multicell Battery Stack Monitors Measures Up to 12 Series-Connected Battery Cells, 1st Generation:

Superseded by the LTC6803 and LTC6804 for New Designs

LTC6803-1/LTC6803-3

LTC6803-2/LTC6803-4

Multicell Battery Stack Monitors Measures Up to 12 Series-Connected Battery Cells, 2nd Generation:

Functionally Enhanced and Pin Compatible to the LTC6802

LTC6804-1/LTC6804-2 Multicell Battery Monitors Measures Up to 12 Series-Connected Battery Cells, 3rd Generation:

Higher Precision Than LTC6803 and Built-In isoSPI Interface

LTC6820 isoSPI Isolated Communications Interface Provides an Isolated Interface for SPI Communication Up to 100m

Using a Twisted Pair, Companion to the LTC6804

TYPICAL APPLICATION

9 CELLS

12 CELLS

12-CELL

MODULE 2

ISO IN

GPIO5

GPIO4

GPIO3

SCKI

SDI

SDO

CSBI

LTC6804-2

DATA

LTC3300-2

LTC3300-2 DIGITAL

ISOLATOR

ADDRESS =

00011

ADDRESS =

00001

ADDRESS =

00000

ADDRESS =

00010

ADDRESS =

0001

ISO IN

GPIO5

GPIO4

GPIO3

LTC6804-2

ADDRESS =

0000

12-CELL

MODULE 1

ISO

33002 TA02

SPI 4

SCKI

SDI

SDO

CSBI

LTC6820

isoSPI

LTC3300-2

DIGITAL

ISOLATOR

ADDRESS =

00001

ADDRESS =

00000

LTC3300-2/LTC6804-2 Serial Communication Connections