2SK2735(L), 2SK2735(S)
Silicon N Channel MOS FET
High Speed Power Switching
ADE-208-543 (Z)
1st. Edition
Sep. 1997
Features
• Low on-resistance
RDS = 20 mΩ typ.
• High speed switching
• 4V gate drive device can be driven from 5V source
Outline
123
44
123
1. Gate
2. Drain
3. Source
4. Drain
DPAK–2
D
G
S
2SK2735(L), 2SK2735(S)
2
Absolute Maximum Ratings (Ta = 25°C)
Item Symbol Ratings Unit
Drain to source voltage VDSS 30 V
Gate to source voltage VGSS ±20 V
Drain current ID20 A
Drain peak current ID(pulse)*180 A
Body to drain diode reverse drain current IDR 20 A
Channel dissipation Pch*220 W
Channel temperature Tch 150 °C
Storage temperature Tstg –55 to +150 °C
Notes: 1. PW ≤ 10µs, duty cycle ≤ 1 %
2. Value at Tc = 25°C
2SK2735(L), 2SK2735(S)
3
Electrical Characteristics (Ta = 25°C)
Item Symbol Min Typ Max Unit Test Conditions
Drain to source breakdown
voltage V(BR)DSS 30——V I
D
= 10mA, VGS = 0
Gate to source breakdown
voltage V(BR)GSS ±20——V I
G
= ±100µA, VDS = 0
Gate to source leak current IGSS ——±10 µAV
GS = ±16V, VDS = 0
Zero gate voltege drain
current IDSS ——10µAV
DS = 30 V, VGS = 0
Gate to source cutoff voltage VGS(off) 1.0 — 2.0 V ID = 1mA, VDS = 10V
Static drain to source on state RDS(on) —2028mΩI
D
= 10A, VGS = 10V*1
resistance RDS(on) —3550mΩI
D
= 10A, VGS = 4V*1
Forward transfer admittance |yfs| 8 16 — S ID = 10A, VDS = 10V*1
Input capacitance Ciss — 750 — pF VDS = 10V
Output capacitance Coss — 520 — pF VGS = 0
Reverse transfer capacitance Crss — 210 — pF f = 1MHz
Turn-on delay time td(on) — 16 — ns ID = 10A, VGS = 10V
Rise time tr— 225 — ns RL = 1Ω
Turn-off delay time td(off) —85—ns
Fall time tf—90—ns
Body to drain diode forward
voltage VDF — 1.0 — V IF = 20A, VGS = 0
diF/ dt = 50A/µs
Body to drain diode reverse
recovery time trr —40—V I
F
= 20A, VGS = 0
diF/ dt = 50A/µs
Note: 1. Pulse test
See characteristics curves of 2SK2684
2SK2735(L), 2SK2735(S)
4
Main Characteristics
40
30
20
10
050 100 150 200
500
200
100
20
50
10
2
5
1
0.5
0.1 0.3 1 310 30 100
Ta = 25 °C
100 µs
1 ms
PW = 10 ms (1shot)
DC Operation (Tc = 25°C)
10 µs
Channel Dissipation Pch (W)
Case Temperature Tc (°C)
Power vs. Temperature Derating
Drain to Source Voltage V (V)
DS
Drain Current I (A)
D
Maximum Safe Operation Area
Operation in
this area is
limited by RDS(on)
50
40
30
20
10
0
20
16
12
8
4
8 16243240
0
V = 5 V
10 V
25 V
DD
I = 20 A
D
VGS
VDS
V = 25 V
10 V
5 V
DD
Gate Char
g
e Q
g
(
nc
)
Drain to Source Voltage V (V)
DS
Gate to Source Voltage V (V)
GS
Dynamic Input Characteristics
2SK2735(L), 2SK2735(S)
5
3
1
0.3
0.1
0.03
0.01
10 µ100 µ1 m 10 m 100 m 1 10
DM
P
PW
T
D = PW
T
ch – c(t) = s (t) • ch – c
ch – c = 6.25 °C/W, Tc = 25 °C
θ γ θ
θ
D = 1
0.5
0.2
0.01
0.02
0.1
0.05
1 shot Pulse
Tc = 25°C
Pulse Width PW (S)
Normalized Transient Thermal Impedance
s (t)
γ
Normalized Transient Thermal Impedance vs. Pulse Width
Vin Monitor
D.U.T.
Vin
10 V
RL
V
= 10 V
DD
tr
td(on)
Vin
90% 90%
10%
10%
Vout
td(off)
Vout
Monitor
50Ω
90%
10%
tf
Switching Time Test Circuit Waveform
2SK2735(L), 2SK2735(S)
6
Package Dimensions
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
DPAK (L)-(2)
—
—
0.42 g
6.5 ± 0.5 2.3 ± 0.2
0.55 ± 0.1
1.2 ± 0.3
0.55 ± 0.1
5.5 ± 0.5 1.7 ± 0.5
16.2 ± 0.5
4.7 ± 0.5
5.4 ± 0.5
1.15 ± 0.1
2.29 ± 0.5 2.29 ± 0.5
0.8 ± 0.1
0.55 ± 0.1
3.1 ± 0.5
(0.7)
As of January, 2001
Unit: mm
2SK2735(L), 2SK2735(S)
7
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
DPAK (S)-(1),(2)
—
Conforms
0.28 g
As of January, 2001
Unit: mm
6.5 ± 0.5
5.4 ± 0.5 2.3 ± 0.2
0.55 ± 0.1
0 – 0.25
0.55 ± 0.1
1.7 ± 0.5
5.5 ± 0.5
2.5 ± 0.5
1.15 ± 0.1
0.8 ± 0.1
2.29 ± 0.5
2.29 ± 0.5
1.2 Max
(4.9)
(5.3)
2SK2735(L), 2SK2735(S)
8
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
DPAK (S)-(3)
—
Conforms
0.28 g
As of January, 2001
Unit: mm
6.5 ± 0.5
5.4 ± 0.5 2.3 ± 0.2
0.55 ± 0.1
0 – 0.25
0.55 ± 0.1
1.5 ± 0.5
5.5 ± 0.5
2.5 ± 0.5
1.15 ± 0.1
0.8 ± 0.1
2.29 ± 0.5
2.29 ± 0.5
1.2 Max
(5.1)
(5.1)
(0.1)(0.1)
2SK2735(L), 2SK2735(S)
9
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for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
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failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
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