MB81ES171625-15 - Fujitsu Quantum Devices Limited

16M-bit Consumer FCRAMTM

for SiP

MB81ES171625-12/15 (

16-bit)

MB81ES171625-12/15-X (

16-bit ; Extended Temp.Version)

MB81ES173225-12/15 (

32-bit)

MB81ES173225-12/15-X (

32-bit ; Extended Temp.Version)

The 16M-bit Consumer FCRAMTM with SDRAM interface

has been developed exclusively for the system-in-a-package (SiP).

Compared to conventional SDRAMs, the FCRAMTM core technology

opens up the way to wider bandwidths and lower power consumption.

The device technology is ideal for image processing systems

and other consumer products.

New products

16M-bit Consumer

FCRAM

for SiP

FIND Vol.20

No.22002

Product Overview

The large-density image processing capabilities of the

newest video cameras, DVD recorders, and other appliances

used in today's digital network information society all

depend on DRAMs. To promote the evolution of these

devices, FUJITSU has developed a 16M-bit Consumer

FCRAM to be used exclusively for the system-in-a-package

(SiP). A direct connection between a logic chip and DRAM

chip in a single package reduces the number of external I/O

pin, allowing these two components to function as parts of

the system. Operable at a maximum frequency of 85MHz,

the FCRAM is optimal for use at the 81MHz band most

widely used in the newest image processing systems. As an

added benefit, the adoption of FCRAM core technology

Photo 1 Chip

New products

16M-bit Consumer

FCRAM

for SiP

56 FIND Vol.20 No.2 2002

permits low-voltage (1.8V single power supply), low-power-

consumption (54mW@IDD1) operation.

This product is configured with a general-purpose

SDRAM interface to facilitate design and development for

customers. In addition, our original burn-in simple circuit

and BIST (

＿

Built-

＿

Self

＿

Test) circuit permit memory chip

testing even after these chips are packaged as a SiP.

We now offer a SiP package containing our logic chip and

an FCRAM (wafer) itself.

Fig.1 shows an example of a SiP configured with our logic

chip and an FCRAM in a single package.

Product Features

Table 1 shows the main features of this product. Designed

as a memory for exclusive use with the SiP, this product

offers the following features:

■ 1.8V single power supply

(VDD＝VDDQ＝1.8V±0.15V)

■ SDRAM interface

■ Lower power consumption

The FCRAM core technology achieves low power

consumption, 54mW@85MHz at 32-bit bus. The shortened

wire connection with the logic chip decreases the output load

capacitance and the output transistor size. These features

reduce the power consumption of the input/output part and

will help minimize the noise generated by electromagnetic

interference-a recent concern in the industry.

logicchip

FCRAM

500μm

Fig.1 Example of SiP Containing a Logic Chip and FCRAM in a Single Package

Typeconfiguration MB81ES171625/MB81ES173225

Speedversion −15 −12

Clockfrequency(max.)

Clock(tCK)

66.7MHz 85MHz

/RASaccesstime(tRAC) 57ns 51.9ns

/CASaccesstime(tCAC) 27ns 21.9ns

30nsCL＝1 23.4ns

15nsCL＝2 11.7ns

Accesstimefrom

clock(tAC)

27ns

CL＝1 21.9ns

12nsCL＝2

Operating

temperature

Normalproduct

Temperature

extentionproduct

10.2ns

I/Oconfiguration ×16，×32

Supplyvoltage(VDD＝VDDQ) 1.65Vto1.95V

/RAScycletime(tRC) 75ns

Operatingcurrent(IDD1) 30mA

Powerdowncurrent(IDD2PS) 1mA

Self-refreshcurrent(IDD6) 5mA

0℃to70℃

−40℃to85℃

Refresh

characteristics

Normalproduct

Temperature

extentionproduct

2048cycles/16ms

2048cycles/4ms

Table 1 Main Features

［VDD＝VDDQ］

1.500V

1.550V

1.600V

1.650V

1.700V

1.750V

1.800V

1.850V

1.900V

1.950V

2.000V

2.050V

2.100V

．

PPPPPPPPPPPPPPPPPP

PPPPPPPPPPPPPPPPPPPPPP

PPPPPPPPPPPPPPPPPPPPPPPPPPP

PPPPPPPPPPPPPPPPPPPPPPPPPPPPP

PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP

PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP

PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP

PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP

PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP

．

PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP

PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP

PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP

6.0ns 7.0ns 8.0ns 9.0ns 10.0ns 11.0ns ［tAC2］

Fig. 2 Access Time

−

Supply Voltage Characteristics

New products

16M-bit Consumer

FCRAM

for SiP

FIND Vol.20

No.22002

■ High data transfer rate

The product design supports a data transfer rate of 340M-

byte/sec. by a single chip (×32-bit configuration). When

two chips are mounted to make use of the features of the

SiP, the transfer rate is doubled (680M-byte / sec.).

Fig. 2 shows the access time

―

supply voltage characteristics

of this product.

■ Selectivity of memory density and transfer rate

The ×32-bit configuration, a feature not provided for

conventional 16M-bit products, is suitable for image

processing systems that need wider bandwidths with

comparatively small densities. The use of multiple products

permits the following configurations:

(When two ×32-bit products are mounted)

●256 K words ×64 bits×2 banks

●256 K words ×32 bits×4 banks

●256 K words ×32 bits×2 banks×2 parts (asynchronous

operation in each part)

■ BIST circuit

The BIST circuit built into this product permits memory

tests after the assembly without any of the external pins.

Poorly mounted memories can be rejected easily.

■ Simple circuit for burn-in test

The simple circuit for a burn-in test permits a test

equivalent to the conventional burn-in test just by applying

specified voltage to specific pads.

■ WLT ( ＿

Wafer

＿

Level

＿

Test) function

The WLT function permits shipment of wafers with

guaranteed characteristics.

■ Chip layout

The placement of the pads at the edge permits multi-stage

stack configurations of three or more chips.

Fig. 3 shows the pad layout in the MB81ES171625 and

MB81ES173225. ✱

NOTES

*1: Consumer FCRAM : A high performance RAM which consists

of an FCRAM core with SDRAM interface.

*2: FCRAM (

＿

Fast

＿

Cycle

＿

RAM) is a trademark of FUJITSU

LIMITED.

MB81ES171625

（×16-bit）

PadNo.84

PadNo.1

DSE

BME

TBST

DQC

―

VSS

VDD

VSS

VDD

DQ［8］

DQ［9］

DQ［10］

DQ［11］

VDDQ

VSSQ

DQ［12］

DQ［13］

DQ［14］

DQ［15］

―

DQM［1］

A［12］

A［11］

A［10］（AP）

A［9］

A［8］

A［7］

A［6］

CLK

CKE

VSSQ

S16

VDDQ

XCS

XRAS

XCAS

XWE

A［5］

A［4］

A［3］

A［2］

A［1］

A［0］

DQM［0］

―

DQ［7］

DQ［6］

DQ［5］

DQ［4］

VSSQ

VDDQ

DQ［3］

DQ［2］

DQ［1］

DQ［0］

VDD

VSS

VDD

VSS

―

MB81ES173225

（×32-bit）

DSE

BME

TBST

DQC

DQ［16］

DQ［17］

DQ［18］

DQ［19］

VDDQ

VSSQ

DQ［20］

DQ［21］

DQ［22］

DQ［23］

VSS

VDD

VSS

VDD

DQ［24］

DQ［25］

DQ［26］

DQ［27］

VDDQ

VSSQ

DQ［28］

DQ［29］

DQ［30］

DQ［31］

DQM［2］

DQM［3］

A［12］

A［11］

A［10］（AP）

A［9］

A［8］

A［7］

A［6］

CLK

CKE

VSSQ

S32

VDDQ

XCS

XRAS

XCAS

XWE

A［5］

A［4］

A［3］

A［2］

A［1］

A［0］

DQM［1］

DQM［0］

DQ［15］

DQ［14］

DQ［13］

DQ［12］

VSSQ

VDDQ

DQ［11］

DQ［10］

DQ［9］

DQ［8］

VDD

VSS

VDD

VSS

DQ［7］

DQ［6］

DQ［5］

DQ［4］

VSSQ

VDDQ

DQ［3］

DQ［2］

DQ［1］

DQ［0］

―

Fig.3 Pad Layout