LTC2601/LTC2611/LTC2621
1
2601fb
TYPICAL APPLICATION
DESCRIPTION
16-/14-/12-Bit Rail-to-Rail
DACs in 10-Lead DFN
The LTC
®
2601/LTC2611/LTC2621 are single 16-, 14- and
12-bit,
2.5V-to-5.5V rail-to-rail voltage output DACs in a
10-lead DFN package. They have built-in high performance
output buffers and are guaranteed monotonic.
These parts establish new board-density benchmarks for
16- and 14-bit DACs and advance performance standards
for output drive and load regulation in single-supply, volt-
age-output DACs.
The parts use a simple SPI/MICROWIRE compatible 3-wire
serial interface which can be operated at clock rates up to
50MHz. Daisy-chain capability, hardware CLR and asyn-
chronous DAC update (LDAC) pins are included.
The LTC2601/LTC2611/LTC2621 incorporate a power-on
reset circuit. During power-up, the voltage outputs rise
less than 10mV above zero scale until a valid write and
update take place. The power-on reset circuit resets the
LTC2601-1/LTC2611-1/LTC2621-1 to midscale. The volt-
age outputs stay at midscale until a valid write and update
take place.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 5396245.
FEATURES
APPLICATIONS
n Smallest Pin-Compatible Single DACs:
LTC2601: 16 Bits
LTC2611: 14 Bits
LTC2621: 12 Bits
n Guaranteed Monotonic Over Temperature
n Wide 2.5V to 5.5V Supply Range
n Low Power Operation: 300μA at 3V
n Power Down to 1μA, Max
n High Rail-to-Rail Output Drive (±15mA, Min)
n Double-Buffered Data Latches
n Asynchronous DAC Update Pin
n LTC2601-1/LTC2611-1/LTC2621-1: Power-On Reset
to Midscale
n Tiny (3mm × 3mm) 10-Lead DFN Package
n Mobile Communications
n Process Control and Industrial Automation
n Instrumentation
n Automatic Test Equipment
Differential Nonlinearity (LTC2601)
7
10
1
DAC
REGISTER
INPUT
REGISTER
32-BIT
SHIFT
REGISTER
12-/14-/16-BIT DAC VOUT
CONTROL
DECODE
LOGIC
LDAC
SDO
2SDI
SCK
5CS/LD
9
VCC
6
REF
8
GND
2601 TA01a
4
CLR
3
CODE
0 16384 32768 49152 65535
DNL (LSB)
2600 TA01b
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
VCC = 5V
VREF = 4.096V
LTC2601/LTC2611/LTC2621
2
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PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS
Any Pin to GND ............................................ –0.3V to 6V
Any Pin to VCC.............................................. –6V to 0.3V
Maximum Junction Temperature........................... 125°C
Storage Temperature Range ...................–65°C to 125°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
Operating Temperature Range:
LTC2601C/LTC2611C/LTC2621C
LTC2601C-1/LTC2611C-1/LTC2621C-1 .... 0°C to 70°C
LTC2601I/LTC2611I/LTC2621I
LTC2601I-1/LTC2611I-1/LTC2621I-1 ....–40°C to 85°C
(Note 1)
TOP VIEW
11
DD PACKAGE
10-LEAD (3mm s 3mm) PLASTIC DFN
10
9
6
7
8
4
5
3
2
1LDA
C
VCC
GND
VOUT
REF
SDO
SDI
SCK
CLR
CS/LD
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2601CDD#PBF LTC2601CDD#TRPBF LAGT 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2601IDD#PBF LTC2601IDD#TRPBF LAGT 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2611CDD#PBF LTC2611CDD#TRPBF LBFQ 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2611IDD#PBF LTC2611IDD#TRPBF LBFQ 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2621CDD#PBF LTC2621CDD#TRPBF LBFS 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2621IDD#PBF LTC2621IDD#TRPBF LBFS 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2601CDD-1#PBF LTC2601CDD-1#TRPBF LBZH 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2601IDD-1#PBF LTC2601IDD-1#TRPBF LBZH 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2611CDD-1#PBF LTC2611CDD-1#TRPBF LBZJ 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2611IDD-1#PBF LTC2611IDD-1#TRPBF LBZJ 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2621CDD-1#PBF LTC2621CDD-1#TRPBF LBZK 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2621IDD-1#PBF LTC2621IDD-1#TRPBF LBZK 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2601CDD LTC2601CDD#TR LAGT 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2601IDD LTC2601IDD#TR LAGT 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2611CDD LTC2611CDD#TR LBFQ 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2611IDD LTC2611IDD#TR LBFQ 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2621CDD LTC2621CDD#TR LBFS 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2621IDD LTC2621IDD#TR LBFS 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2601CDD-1 LTC2601CDD-1#TR LBZH 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2601IDD-1 LTC2601IDD-1#TR LBZH 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2611CDD-1 LTC2611CDD-1#TR LBZJ 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2611IDD-1 LTC2611IDD-1#TR LBZJ 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2621CDD-1 LTC2621CDD-1#TR LBZK 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2621IDD-1 LTC2621IDD-1#TR LBZK 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
LTC2601/LTC2611/LTC2621
3
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ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.5V), VOUT unloaded,
unless otherwise noted.
SYMBOL PARAMETER CONDITIONS
LTC2621/ LTC2621-1 LTC2611/ LTC2611-1 LTC2601/ LTC2601-1
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
DC Performance
Resolution l12 14 16 Bits
Monotonicity (Note 2) l12 14 16 Bits
DNL Differential Nonlinearity (Note 2) l±0.5 ±1 ±1 LSB
INL Integral Nonlinearity (Note 2) l±0.8 ±4 ±3 ±16 ±13 ±64 LSB
Load Regulation VREF = VCC = 5V, Midscale
I
OUT = 0mA to 15mA Sourcing
I
OUT = 0mA to 15mA Sinking
l
l
0.03
0.04
0.125
0.125
0.10
0.15
0.5
0.5
0.45
0.60
2
2
LSB/mA
LSB/mA
V
REF = VCC = 2.5V, Midscale
I
OUT = 0mA to 7.5mA Sourcing
I
OUT = 0mA to 7.5mA Sinking
l
l
0.06
0.08
0.25
0.25
0.2
0.3
1
1
0.9
1.2
4
4
LSB/mA
LSB/mA
ZSE Zero-Scale Error Code = 0 l19 19 19 mV
VOS Offset Error (Note 5) l±1.5 ±9 ±1.5 ±9 ±1.5 ±9 mV
VOS Temperature
Coeffi cient
±5 ±5 ±5 μV/°C
GE Gain Error l±0.03 ±0.7 ±0.1 ±0.7 ±0.05 ±0.7 %FSR
Gain Temperature
Coeffi cient
±2 ±2 ±2 ppm/°C
The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C.
REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.5V), VOUT unloaded, unless otherwise noted. (Note 8)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PSR Power Supply Rejection VCC = 5V ±10%
VCC = 3V ±10% l
–80
–80
dB
dB
ROUT DC Output Impedance VREF = VCC = 5V, Midscale; –15mA ≤ IOUT ≤ 15mA
VREF = VCC = 2.5V, Midscale; –7.5mA ≤ IOUT ≤ 7.5mA
l
l
0.04
0.05
0.15
0.15
Ω
Ω
ISC Short-Circuit Output Current VCC = 5.5V, VREF = 5.5V
Code: Zero Scale; Forcing Output to VCC
Code: Full Scale; Forcing Output to GND
l
l
15
15
35
39
60
60
mA
mA
VCC = 2.5V, VREF = 2.5V
Code: Zero Scale; Forcing Output to VCC
Code: Full Scale; Forcing Output to GND
l
l
7.5
7.5
20
27
50
50
mA
mA
Reference Input
Input Voltage Range l0 VCC V
Resistance Normal Mode l88 124 160 kΩ
Capacitance 15 pF
IREF Reference Current, Power Down Mode DAC Powered Down l0.001 1 μA
Power Supply
VCC Positive Supply Voltage For Specifi ed Performance l2.5 5.5 V
ICC Supply Current VCC = 5V (Note 3)
VCC = 3V (Note 3)
DAC Powered Down (Note 3) VCC = 5V
DAC Powered Down (Note 3) VCC = 3V
l
l
l
l
0.375
0.30
0.40
0.10
0.55
0.45
1
1
mA
mA
μA
μA
Digital I/O
VIH Digital Input High Voltage VCC = 2.5V to 5.5V
VCC = 2.5V to 3.6V
l
l
2.4
2.0
V
V
LTC2601/LTC2611/LTC2621
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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIL Digital Input Low Voltage VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
l
l
0.8
0.6
V
V
VOH Digital Output High Voltage Load Current = –100μA lVCC – 0.4 V
VOL Digital Output Low Voltage Load Current = +100μA l0.4 V
ILK Digital Input Leakage VIN = GND to VCC l±1 μA
CIN Digital Input Capacitance (Note 4) l8pF
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.5V), VOUT unloaded,
unless otherwise noted. (Note 8)
The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C.
REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.5V), VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS
LTC2621/ LTC2621-1 LTC2611/ LTC2611-1 LTC2601/ LTC2601-1
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
AC Performance
tSSettling Time (Note 6) ±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
77
9
7
9
10
μs
μs
μs
Settling Time for 1LSB Step
(Note 7)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
2.7 2.7
4.8
2.7
4.8
5.2
μs
μs
μs
Voltage Output Slew Rate 0.80 0.80 0.80 V/μs
Capacitive Load Driving 1000 1000 1000 pF
Glitch Impulse At Midscale Transition 12 12 12 nV • s
Multiplying Bandwidth 180 180 180 kHz
enOutput Voltage Noise
Density
At f = 1kHz
At f = 10kHz
120
100
120
100
120
100
nV/√Hz
nV/√Hz
Output Voltage Noise 0.1Hz to 10Hz 15 15 15 μVP-P
TIMING CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. (See Figure 1) (Notes 4, 8)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC = 2.5V to 5.5V
t1SDI Valid to SCK Setup l4ns
t2SDI Valid to SCK Hold l4ns
t3SCK High Time l9ns
t4SCK Low Time l9ns
t5CS/LD Pulse Width l10 ns
t6LSB SCK High to CS/LD High l7ns
t7CS/LD Low to SCK High l7ns
t8SDO Propagation Delay from SCK Falling Edge CLOAD = 10pF
V
CC = 4.5V to 5.5V
V
CC = 2.5V to 5.5V
l
l
20
45
ns
ns
t9CLR Pulse Width l20 ns
t10 CS/LD High to SCK Positive Edge l7ns
t12 LDAC Pulse Width l15 ns
t13 CS/LD High to LDAC High or Low Transition l200 ns
SCK Frequency 50% Duty Cycle l50 MHz
LTC2601/LTC2611/LTC2621
5
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TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL) Differential Nonlinearity (DNL) INL vs Temperature
DNL vs Temperature INL vs VREF DNL vs VREF
TIMING CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Linearity and monotonicity are defi ned from code KL to code
2N – 1, where N is the resolution and KL is given by KL = 0.016(2N/VREF),
rounded to the nearest whole code. For VREF = 4.096V and N = 16, KL =
256 and linearity is defi ned from code 256 to code 65,535.
Note 3: Digital inputs at 0V or VCC.
Note 4: Guaranteed by design and not production tested.
Note 5: Inferred from measurement at code KL = 0.016(2N/VREF) and at
full scale.
Note 6: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4 scale to 3/4 scale and
3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
Note 7: VCC = 5V, VREF = 4.096V. DAC is stepped ±1LSB between half scale
and half scale – 1. Load is 2k in parallel with 200pF to GND.
Note 8: These specifi cations apply to LTC2601/LTC2601-1,
LTC2611/LTC2611-1, LTC2621/LTC2621-1
LTC2601
CODE
016384 32768 49152 65535
INL (LSB)
2601 G01
32
24
16
8
0
–8
–16
–24
–32
VCC = 5V
VREF = 4.096V
CODE
0 16384 32768 49152 65535
DNL (LSB)
2600 G02
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
VCC = 5V
VREF = 4.096V
TEMPERATURE (°C)
–50 –30 –10 10 30 50 70 90
INL (LSB)
2601 G03
32
24
16
8
0
–8
–16
–24
–32
VCC = 5V
VREF = 4.096V
INL (POS)
INL (NEG)
TEMPERATURE (°C)
–50 –30 –10 10 30 50 70 90
DNL (LSB)
2601 G04
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
VCC = 5V
VREF = 4.096V
DNL (POS)
DNL (NEG)
VREF (V)
012345
INL (LSB)
2601 G05
32
24
16
8
0
–8
–16
–24
–32
VCC = 5.5V
INL (POS)
INL (NEG)
VREF (V)
012345
DNL (LSB)
2601 G06
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
VCC = 5.5V
DNL (POS)
DNL (NEG)
LTC2601/LTC2611/LTC2621
6
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2μs/DIV 2601 G07
VOUT
100μV/DIV
CS/LD
2V/DIV
VCC = 5V, VREF = 4.096V
1/4-SCALE TO 3/4-SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
9.7μs
5μs/DIV 2601 G08
VOUT
100μV/DIV
CS/LD
2V/DIV
SETTLING TO ±1LSB
VCC = 5V, VREF = 4.096V
CODE 512 TO 65535 STEP
AVERAGE OF 2048 EVENTS
12.3μs
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Settling to ±1LSB
Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Settling to ±1LSB
Settling to ±1LSB Settling of Full-Scale Step
LTC2601
LTC2621
LTC2611
CODE
04096 8192 12288 16383
INL (LSB)
2601 G09
8
6
4
2
0
–2
–4
–6
–8
VCC = 5V
VREF = 4.096V
CODE
0 4096 8192 12288 16383
DNL (LSB)
2601 G10
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
VCC = 5V
VREF = 4.096V
2μs/DIV 2601 G11
VOUT
100μV/DIV
CS/LD
2V/DIV
VCC = 5V, VREF = 4.096V
1/4-SCALE TO 3/4-SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
8.9μs
CODE
01024 2048 3072 4095
INL (LSB)
2601 G12
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
VCC = 5V
VREF = 4.096V
CODE
0 1024 2048 3072 4095
DNL (LSB)
2601 G13
VCC = 5V
VREF = 4.096V
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
2μs/DIV 2601 G14
VOUT
1mV/DIV
CS/LD
2V/DIV
VCC = 5V, VREF = 4.096V
1/4-SCALE TO 3/4-SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
6.8μs
LTC2601/LTC2611/LTC2621
7
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TYPICAL PERFORMANCE CHARACTERISTICS
Zero-Scale Error vs Temperature Gain Error vs Temperature Offset Error vs VCC
Gain Error vs VCC ICC Shutdown vs VCC Large-Signal Response
Current Limiting Load Regulation Offset Error vs Temperature
LTC2601/LTC2611/LTC2621
IOUT (mA)
–40 –30 –20 –10 0 10 20 30 40
ΔVOUT (V)
2601 G17
0.10
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
VREF = VCC = 5V
VREF = VCC = 3V
VREF = VCC = 5V
VREF = VCC = 3V
CODE = MIDSCALE
IOUT (mA)
–35 –25 –15 –5 5 15 25 35
ΔVOUT (mV)
2601 G18
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
VREF = VCC = 5V
CODE = MIDSCALE
VREF = VCC = 3V
TEMPERATURE (°C)
–50 –30 –10 10 30 50 70 90
OFFSET ERROR (mV)
2601 G19
3
2
1
0
–1
–2
–3
TEMPERATURE (°C)
–50 –30 –10 10 30 50 70 90
ZERO-SCALE ERROR (mV)
2601 G20
3
2.5
2.0
1.5
1.0
0.5
0
TEMPERATURE (°C)
–50 –30 –10 10 30 50 70 90
GAIN ERROR (%FSR)
2601 G21
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
VCC (V)
2.5 3 3.5 4 4.5 5 5.5
GAIN ERROR (%FSR)
2601 G23
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
VCC (V)
2.5 3 3.5 4 4.5 5 5.5
OFFSET ERROR (mV)
2601 G22
3
2
1
0
–1
–2
–3
VCC (V)
2.5 3 3.5 4 4.5 5 5.5
ICC (nA)
2601 G24
450
400
350
300
250
200
150
100
50
0
2.5μs/DIV
VOUT
0.5V/DIV
2601 G25
VREF = VCC = 5V
1/4-SCALE TO 3/4-SCALE
LTC2601/LTC2611/LTC2621
8
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TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Logic Voltage Hardware CLR to Zero Scale Hardware CLR to Midscale
Power-On Reset to Midscale Multiplying Bandwidth
Output Voltage Noise,
0.1Hz to 10Hz
Midscale Glitch Impulse
Power-On Reset Glitch
to Zero Scale
Headroom at Rails
vs Output Current
LTC2601/LTC2611/LTC2621
VOUT
10mV/DIV
CS/LD
5V/DIV
2.5μs/DIV 2601 G26
12nV-s TYP
VOUT
10mV/DIV
250μs/DIV 2601 G27
VCC
1V/DIV
4mV PEAK
IOUT (mA)
012345678910
VOUT (V)
2601 G28
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5V SOURCING
3V SOURCING
3V SINKING
5V SINKING
LOGIC VOLTAGE (V)
0
0
ICC (mA)
0.2
0.6
0.8
1.0
1.4
0.5 2.5 3.5
2601 G29
0.4
1.2
24.5 5
11.5 34
VCC = 5V
SWEEP SCK, SDI
AND CS/LD
0V TO VCC VOUT
1V/DIV
1μs/DIV 2601 G31
CLR
5V/DIV
VCC = 5V
VREF = 4.096V
CODE = FULL SCALE VOUT
1V/DIV
1μs/DIV 2601 G34
CLR
5V/DIV
VCC = 5V
VREF = 4.096V
CODE = FULL SCALE
1V/DIV
VREF = VCC
VCC
VOUT
500μs/DIV 2601 G35
FREQUENCY (Hz)
1k
dB
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
–30
–33
–36 1M
2601 G32
10k 100k
VCC = 5V
VREF (DC) = 2V
VREF (AC) = 0.2VP-P
CODE = FULL SCALE
VOUT
10μV/DIV
SECONDS
012345678910
2601 G33
LTC2601/LTC2611/LTC2621
9
2601fb
PIN FUNCTIONS
SDO (Pin 1): Serial Interface Data Output. This pin is used
for daisy-chain operation. The serial output of the shift
register appears at the SDO pin. The data transferred to
the device via the SDI pin is delayed 32 SCK rising edges
before being output at the next falling edge. SDO is an
active output and does not go high impedance even when
CS/LD is taken to a logic high level.
SDI (Pin 2): Serial Interface Data Input. Data is applied
to SDI for transfer to the device at the rising edge of SCK
(Pin 3). The LTC2601 accepts input word lengths of either
24 or 32 bits.
SCK (Pin 3): Serial Interface Clock Input. CMOS and TTL
compatible.
CLR (Pin 4): Asynchronous Clear Input. A logic low at this
level-triggered input clears all registers and causes the
DAC voltage outputs to drop to 0V for LTC2601/LTC2611/
LTC2621. A logic low at this input sets all registers to
midscale code and causes the DAC voltage outputs to go
to midscale for LTC2601-1/LTC2611-1/LTC2621-1. CMOS
and TTL compatible.
CS/LD (Pin 5): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on
SDI into the register. When CS/LD is taken high, SCK
is disabled and the specifi ed command (see Table 1) is
executed.
REF (Pin 6): Reference Voltage Input. 0V ≤ VREF ≤ VCC.
VOUT (Pin 7): DAC Analog Voltage Output. The output
range is 0V to VREF.
GND (Pin 8): Analog Ground.
VCC (Pin 9): Supply Voltage Input. 2.5V ≤ VCC ≤ 5.5V.
LDAC (Pin 10): Asynchronous DAC Update Pin. If CS/LD
is high, a falling edge on LDAC immediately updates the
DAC register with the contents of the input register (similar
to a software update). If CS/LD is low when LDAC goes
low, the DAC register is updated after CS/LD returns high.
A low on the LDAC pin powers up the DAC. A software
power down command is ignored if LDAC is low.
Exposed Pad (Pin 11): Ground. Must be soldered to PCB
ground.
TYPICAL PERFORMANCE CHARACTERISTICS
Short-Circuit Output Current vs
VOUT (Sinking)
Short-Circuit Output Current vs
VOUT (Sourcing)
LTC2601/LTC2611/LTC2621
1V/DIV
0
0
10mA/DIV
10
20
30
40
50
1234
2601 G15
56
VCC = 5.5V
VREF = 5.6V
CODE = 0
VOUT SWEPT 0V TO VCC
1V/DIV
0
–50
10mA/DIV
–40
–30
–20
–10
0
1234
2601 G16
56
VCC = 5.5V
VREF = 5.6V
CODE = FULL SCALE
VOUT SWEPT VCC TO 0V
LTC2601/LTC2611/LTC2621
10
2601fb
BLOCK DIAGRAM
TIMING DIAGRAMS
Figure 1a
Figure 1b
7
10
1
DAC
REGISTER
INPUT
REGISTER
32-BIT
SHIFT
REGISTER
12-/14-/16-BIT DAC VOUT
CONTROL
DECODE
LOGIC
LDAC
SDO
2SDI
SCK
5CS/LD
9
VCC
6
REF
8
GND
2601 BD
4
CLR
3
SDI
SDO
C
S/LD
SCK
2601 F01a
t2
t8
t10
t5t7
t6
t1
LDAC
t3t4
1232324
t13 t12
CS/LD
2601 F01b
t13
LDAC
LTC2601/LTC2611/LTC2621
11
2601fb
OPERATION
only be transferred to the device when the CS/LD signal
is low.The rising edge of CS/LD ends the data transfer and
causes the device to execute the command specifi ed in
the 24-bit input word. The complete sequence is shown
in Figure 2a.
The command (C3-C0) assignments are shown in Table
1. The fi rst four commands in the table consist of write
and update operations. A write operation loads a 16-bit
data word from the 32-bit shift register into the input
register of the DAC. In an update operation, the data word
is copied from the input register to the DAC register and
converted to an analog voltage at the DAC output. The
update operation also powers up the DAC if it had been in
power-down mode. The data path and registers are shown
in the Block Diagram.
While the minimum input word is 24 bits, it may option-
ally be extended to 32 bits. To use the 32-bit word width,
8 don’t-care bits are transferred to the device fi rst, followed
by the 24-bit word as just described. Figure 2b shows the
32-bit sequence. The 32-bit word is required for daisy-
chain operation, and is also available to accommodate
microprocessors which have a minimum word width of
16 bits (2 bytes).
Daisy-Chain Operation
The serial output of the shift register appears at the SDO
pin. Data transferred to the device from the SDI input is
delayed 32 SCK rising edges before being output at the
next SCK falling edge.
The SDO output can be used to facilitate control of multiple
serial devices from a single 3-wire serial port (i.e., SCK,
SDI and CS/LD). Such a “daisy chain” series is confi gured
by connecting SDO of each upstream device to SDI of the
Power-On Reset
The LTC2601/LTC2611/LTC2621 clear the outputs to zero
scale when power is fi rst applied, making system initializa-
tion consistent and repeatable. The LTC2601-1/LTC2611-
1/LTC2621-1 set the voltage outputs to midscale when
power is fi rst applied.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2601/
LTC2611/LTC2621 contain circuitry to reduce the power-
on glitch; furthermore, the glitch amplitude can be made
arbitrarily small by reducing the ramp rate of the power
supply. For example, if the power supply is ramped to 5V
in 1ms, the analog outputs rise less than 10mV above
ground (typ) during power-on. See Power-On Reset Glitch
in the Typical Performance Characteristics section.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the range
–0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum Rat-
ings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at VCC (Pin 16) is in transition.
Transfer Function
The digital-to-analog transfer function is:
VkV
OUT IDEAL NREF()
=⎛
⎝
⎜⎞
⎠
⎟
2
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and VREF is the voltage at REF
(Pin 6).
Serial Interface
The CS/LD input is level triggered. When this input is
taken low, it acts as a chip-select signal, powering-on the
SDI and SCK buffers and enabling the input shift register.
Data (SDI input) is transferred at the next 24 rising SCK
edges. The 4-bit command, C3-C0, is loaded fi rst; then
4 don’t care bits; and fi nally the 16-bit data word. The
data word comprises the 16-, 14- or 12-bit input code,
ordered MSB-to-LSB, followed by 0, 2 or 4 don’t care bits
(LTC2601, LTC2611 and LTC2621 respectively). Data can
Table 1.
COMMAND*
C3 C2 C1 C0
0 0 0 0 Write to Input Register
0 0 0 1 Update (Power Up) DAC Register
0 0 1 1 Write to and Update (Power Up)
0 1 0 0 Power Down
1 1 1 1 No Operation
*Command codes not shown are reserved and should not be used.
LTC2601/LTC2611/LTC2621
12
2601fb
OPERATION
next device in the chain. The shift registers of the devices
are thus connected in series, effectively forming a single
input shift register which extends through the entire
chain. Because of this, the devices can be addressed and
controlled individually by simply concatenating their input
words; the fi rst instruction addresses the last device in
the chain and so forth. The SCK and CS/LD signals are
common to all devices in the series.
In use, CS/LD is fi rst taken low. Then the concatenated
input data is transferred to the chain, using SDI of the
fi rst device as the data input. When the data transfer is
complete, CS/LD is taken high, which executes the com-
mands specifi ed for each of the devices simultaneously. A
single device can be controlled by using the no-operation
command (1111) for the other devices in the chain.
Power-Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever the
DAC output is not needed. When in power-down, the buffer
amplifi er, bias circuit and reference input is disabled and
draws essentially zero current. The DAC output is put into a
high impedance state, and the output pin is passively pulled
to ground through 90k resistors. Input- and DAC-register
contents are not disturbed during power-down.
The DAC can be put into power-down mode by using
command 0100b. The 16-bit data word is ignored. The
supply and reference currents are reduced to almost zero
when the DAC is powered down; the effective resistance at
REF rises accordingly becoming a high impedance input
(typically > 1GΩ).
Normal operation can be resumed by executing any com-
mand which includes a DAC update, as shown in Table 1 or
performing an asynchronous update (LDAC) as described
in the next section. The DAC is powered up as its voltage
output is updated. When the DAC in powered-down state
is powered up and updated, normal settling is delayed. The
main bias generation circuit block has been automatically
shut down in addition to the DAC amplifi er and reference
input and so the power up delay time is 12μs (for VCC =
5V) or 30μs (for VCC = 3V).
Asynchronous DAC Update Using LDAC
In addition to the update commands shown in Table 1,
the LDAC pin asynchronously updates the DAC register
with the contents of the input register.
If CS/LD is high, a low on the LDAC pin causes the DAC
register to be updated with the contents of the input
register.
If CS/LD is low, a low going pulse on the LDAC pin before
the rising edge of CS/LD powers up the DAC but does not
cause the output to be updated. If LDAC remains low after
INPUT WORD (LTC2601)
INPUT WORD (LTC2611)
INPUT WORD (LTC2621)
C3
COMMAND DON’T CARE BITS DATA (16 BITS)
C2 C1 C0 XXXXD13D14D15 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
2601 TBL01
MSB LSB
C3
COMMAND DON’T CARE BITS DATA (14 BITS + 2 DON’T CARE BITS)
C2 C1 C0 XXXXD13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X
2601 TBL02
MSB LSB
C3
COMMAND DON’T CARE BITS DATA (12 BITS + 4 DON’T CARE BITS)
C2 C1 C0 XXXXD11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X XXX
2601 TBL03
MSB LSB
LTC2601/LTC2611/LTC2621
13
2601fb
the rising edge of CS/LD, then LDAC is recognized, the
command specifi ed in the 24-bit word just transferred is
executed and the DAC output is updated.
The DAC is powered up when LDAC is taken low, inde-
pendent of the state of CS/LD.
If LDAC is low at the time CS/LD goes high, it inhibits any
software power-down command that was specifi ed in the
input word.
Voltage Outputs
The rail-to-rail amplifi er contained in these parts has
guaranteed load regulation when sourcing or sinking up
to 15mA at 5V (7.5mA at 3V).
Load regulation is a measure of the amplifi er’s ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is expressed
in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifi er’s DC output
impedance is 0.05Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 25Ω typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
25Ω • 1mA = 25mV. See the graph Headroom at Rails vs
Output Current in the Typical Performance Characteristics
section.
The amplifi er is stable driving capacitive loads of up to
1000pF.
Board Layout
The excellent load regulation of these devices is achieved
in part by keeping “signal” and “power” grounds separated
internally and by reducing shared internal resistance.
The GND pin functions both as the node to which the refer-
ence and output voltages are referred and as a return path
OPERATION
for power currents in the device. Because of this, careful
thought should be given to the grounding scheme and
board layout in order to ensure rated performance.
The PC board should have separate areas for the analog
and digital sections of the circuit. This keeps digital signals
away from sensitive analog signals and facilitates the use
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each
other.
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continuous
and uninterrupted plane, except for necessary lead pads
and vias, with signal traces on another layer.
The GND pin of the part should be connected to analog
ground. Resistance from the GND pin to system star
ground should be as low as possible. Resistance here
will add directly to the effective DC output impedance
of the device (typically 0.05Ω). Note that the LTC2601/
LTC2611/LTC2621 are no more susceptible to these ef-
fects than other parts of their type; on the contrary, they
allow layout-based performance improvements to shine
rather than limiting attainable performance with excessive
internal resistance.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is limited
to voltages within the supply range.
Since the analog output of the device cannot go below
ground, it may limit for the lowest codes as shown in Figure
3b. Similarly, limiting can occur near full scale when the
REF pin is tied to VCC. If VREF = VCC and the DAC full-scale
error (FSE) is positive, the output for the highest codes
limits at VCC as shown in Figure 3c. No full-scale limiting
can occur if VREF is less than VCC – FSE.
Offset and linearity are defi ned and tested over the region
of the DAC transfer function where no output limiting can
occur.
LTC2601/LTC2611/LTC2621
14
2601fb
OPERATION
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24
C2 C1 C0 X X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C3
CS/LD
SCK
SDI
COMMAND WORD 4 DON’T CARE BITS DATA WORD
24-BIT INPUT WORD
2601 F02a
Figure 2b. LTC2601 32-Bit Load Sequence (Required for Daisy-Chain Operation).
LTC2611 SDI/SDO Data Word: 14-Bit Input Code + 2 Don’t-Care Bits;
LTC2621 SDI/SDO Data Word: 12-Bit Input Code + 4 Don’t-Care Bits
Figure 2a. LTC2601 24-Bit Load Sequence (Minimum Input Word).
LTC2611 SDI Data Word: 14-Bit Input Code + 2 Don’t-Care Bits;
LTC2621 SDI Data Word: 12-Bit Input Code + 4 Don’t-Care Bits
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
C2 C1 C0 X X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C3XXXXXXXX
CS/LD
SCK
SDI
COMMAND WORD DATA WORD
DON’T CARE 4 DON’T CARE BITS
C2 C1 C0 X X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C3XXXXXXXX
SDO
CURRENT
32-BIT
INPUT WORD
2601 F02b
PREVIOUS 32-BIT INPUT WORD
t2
t3t4
t1
t8
D15
17
SCK
SDI
SDO PREVIOUS D14PREVIOUS D15
18
D14
LTC2601/LTC2611/LTC2621
15
2601fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.38 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
2.38 ±0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD10) DFN 1103
0.25 ± 0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.675 ±0.05
3.50 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
PACKAGE DESCRIPTION
Figure 3. Effects of Rail-to-Rail Operation On the DAC Transfer Curve. (a) Overall Transfer Function (b) Effect
of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale
2601 F03
INPUT CODE
(b)
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
32, 7680 65, 535
INPUT CODE
OUTPUT
VOLTAGE
(a)
VREF = VCC
VREF = VCC
(c)
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE
OPERATION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
LTC2601/LTC2611/LTC2621
16
2601fb
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004
LT 0409 REV B • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATION
Demo Circuit DC777 Schematic. Onboard 20-Bit ADC Measures Key Performance Parameters
LDAC
CLR
SDI
SCK
CS/LD
SDO
SCK
SDO
CS
FO
9
8
7
10
10
4
2
3
5
1
7
56
296 1
2601 TA02
3
100Ω 7.5k
0.1μF
8
VOUT
VCC
SPI
BUS
LTC2601
GND
5V
VREF
1V TO 5V
DAC
OUTPUT
VREF VCC
GND
VIN LTC2421
FSSET
ZSSET
0.1μF
5V
100pF
PART NUMBER DESCRIPTION COMMENTS
LTC1458/LTC1458L Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.096V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1654 Dual 14-Bit Rail-to-Rail VOUT DAC Programmable Speed/Power, 3.5μs/750μA, 8μs/450μA
LTC1655/LTC1655L Single 16-Bit VOUT DACs with Serial Interface in SO-8 VCC = 5V(3V), Low Power, Deglitched
LTC1657/LTC1657L Parrallel 5V/3V 16-Bit VOUT DACs Low Power, Deglitched, Rail-to-Rail VOUT
LTC1660/LTC1665 Octal 10/8-Bit VOUT DACs in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output
LTC1661 Dual 10-Bit VOUT DAC 8-Lead MSOP Micropower Rail-to-Rail Output, 3-Wire Interface
LTC1662 Dual 10-Bit VOUT DAC 8-Lead MSOP Ultralow Power, Rail-to-Rail Output
LTC1663 Single 10-Bit VOUT DAC in SOT-23 SMBus Interface, Pin-for-Pin Compatible with LTC1669
LTC1664 Quad 10-Bit VOUT DAC 16-Lead SSOP Micropower Rail-to-Rail Output, 3-Wire Interface
LTC1669 Single 10-Bit VOUT DAC 5-Lead SOT-23 Pin-for-Pin Compatible with LTC1663
LTC1821 Parallel 16-Bit Voltage Output DAC Precision 16-Bit Settling in 2μs for 10V Step
LTC2600/LTC2610/
LTC2620
Octal 16-Bit/14-Bit/12-Bit VOUT DACs in 16-Lead SSOP 250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output
LTC2602/LTC2612/
LTC2622
Dual 16-Bit/14-Bit/12-Bit VOUT DACs in 8-Lead MSOP 300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output
LTC2604/LTC2614/
LTC2624
Quad 16-Bit/14-Bit/12-Bit VOUT DACs in 16-Lead SSOP 250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output, SPI Serial Interface
LTC2605/LTC2615/
LTC2625
Octal 16-Bit/14-Bit/12-Bit VOUT DACs with I2C Interface 250μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail
Output, I2C Interface
LTC2606/LTC2616/
LTC2626
16-Bit/14-Bit/12-Bit VOUT DACs with I2C Interface 270μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail
Output, I2C Interface
LTC2607/LTC2617/
LTC2627
Dual 16-Bit/14-Bit/12-Bit VOUT DACs in 12-Lead DFN with I2C Interface 260μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail
Output, I2C Interface
LTC2609/LTC2619/
LTC2629
Quad 16-Bit/14-Bit/12-Bit VOUT DACs with I2C Interface 250μA Range per DAC, 2.7V to 5.5V Supply Range,
Rail-to-Rail Output with Separate VREF Pins for Each DAC
