16 Mbit (x16) Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet The SST39WF1601 / SST39WF1602 are a 1M x16 CMOS Multi-Purpose Flash Plus (MPF+) devices manufactured with proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39WF1601 / SST39WF1602 write (Program or Erase) with a 1.65-1.95V power supply. These devices conform to JEDEC standard pin assignments for x16 memories. Features * Organized as 1M x16 * Security-ID Feature - SST: 128 bits; User: 128 bits * Single Voltage Read and Write Operations * Fast Read Access Time: - 1.65-1.95V - 70 ns * Superior Reliability * Latched Address and Data - Endurance: 100,000 Cycles (Typical) - Greater than 100 years Data Retention * Low Power Consumption (typical values at 5 MHz) - Active Current: 5 mA (typical) - Standby Current: 5 A (typical) - Auto Low Power Mode: 5 A (typical) * Hardware Block-Protection/WP# Input Pin - Top Block-Protection (top 32 KWord) for SST39WF1602 - Bottom Block-Protection (bottom 32 KWord) for SST39WF1601 * Sector-Erase Capability - Uniform 2 KWord sectors * Block-Erase Capability - Uniform 32 KWord blocks * Chip-Erase Capability * Erase-Suspend/Erase-Resume Capabilities * Hardware Reset Pin (RST#) * Fast Erase and Word-Program: - Sector-Erase Time: 36 ms (typical) - Block-Erase Time: 36 ms (typical) - Chip-Erase Time: 140 ms (typical) - Word-Program Time: 28 s (typical) * Automatic Write Timing - Internal VPP Generation * End-of-Write Detection - Toggle Bits - Data# Polling * CMOS I/O Compatibility * JEDEC Standard - Flash EEPROM Pin Assignments and Command Sets * Packages Available - 48-ball TFBGA (6mm x 8mm) - 48-ball WFBGA (4mm x 6mm) * All devices are RoHS compliant * AEC-Q100-qualified devices available (c)2013 Silicon Storage Technology, Inc. www.microchip.com DS-20005014B 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet Product Description The SST39WF1601/1602 devices are 1M x16 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thickoxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39WF1601/1602 write (Program or Erase) with a 1.65-1.95V power supply. These devices conform to JEDEC standard pin assignments for x16 memories. Featuring high performance Word-Program, the SST39WF1601/1602 devices provide a typical WordProgram time of 28 sec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. The SST39WF1601/1602 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST39WF1601/1602 are offered in both 48-ball TFBGA and 48-ball WFBGA packages. See Figures 2 and 3 for pin assignments. (c)2013 Silicon Storage Technology, Inc. DS-20005014B 2 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet Block Diagram X-Decoder Memory Address SuperFlash Memory Address Buffer Latches Y-Decoder CE# OE# WE# WP# RESET# I/O Buffers and Data Latches Control Logic DQ15 - DQ0 1297 B1.0 Figure 1: Functional Block Diagram (c)2013 Silicon Storage Technology, Inc. DS-20005014B 3 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet Block Diagram TOP VIEW (balls facing down) 6 A13 A12 A14 A15 A16 NC DQ15 VSS A9 5 4 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 WE# RST# NC A19 DQ5 DQ12 VDD DQ4 NC WP# A18 NC DQ2 DQ10 DQ11 DQ3 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A3 A4 A2 A1 A0 CE# OE# VSS A B C D E 3 2 1 F G H 1297 48-tfbga B3K P1.1 Figure 2: Pin assignments for 48-ball TFBGA TOP VIEW (balls facing down) SST39WF160x 6 A2 A4 A6 A17 A1 A3 A7 WP# A0 A5 A18 NC NC WE# RST# A9 A11 A10 A13 A14 A8 A12 A15 5 NC 4 3 CE# DQ8 DQ10 VSS OE# DQ9 DQ4 DQ11 A16 2 NC A19 DQ5 DQ6 DQ7 1 DQ0 DQ1 DQ2 DQ3 A B C D E VDD DQ12 DQ13 DQ14 DQ15 VSS F G H J K L 1297 48-wfbga MBQ P02.0 Figure 3: Pin assignments for 48-ball WFBGA (c)2013 Silicon Storage Technology, Inc. DS-20005014B 4 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet Table 1: Pin Description Symbol Pin Name Functions AMS1-A0 Address Inputs To provide memory addresses. During Sector-Erase AMS-A11 address lines will select the sector. During Block-Erase AMS-A15 address lines will select the block. DQ15-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. WP# Write Protect RST# Reset To reset and return the device to Read mode. CE# Chip Enable To activate the device when CE# is low. To protect the top/bottom boot block from Erase/Program operation when grounded. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. To provide power supply voltage: 1.65-1.95V VDD Power Supply VSS Ground NC No Connection Unconnected pins. T1.0 20005014 1. AMS = Most significant address AMS = A19 for SST39WF1601/1602 (c)2013 Silicon Storage Technology, Inc. DS-20005014B 5 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. The SST39WF1601/1602 also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 9 mA to typically 5 A. The Auto Low Power mode reduces the typical IDD active read current to the range of 2 mA/MHz of Read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Note that the device does not enter Auto-Low Power mode after power-up with CE# held steadily low, until the first address transition or CE# is driven high. Read The Read operation of the SST39WF1601/1602 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 4). Word-Program Operation The SST39WF1601/1602 are programmed on a word-by-word basis. Before programming, the sector where the word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 40 s. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 20 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. During the command sequence, WP# should be statically held high or low. Sector/Block-Erase Operation The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-by-block) basis. The SST39WF1601/1602 offer both Sector-Erase and Block-Erase modes. The sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 10 and 11 for timing waveforms and Figure 24 for the flowchart. Any commands issued during the Sector- or (c)2013 Silicon Storage Technology, Inc. DS-20005014B 6 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet Block-Erase operation are ignored. When WP# is low, any attempt to Sector- (Block-) Erase the protected block will be ignored. During the command sequence, WP# should be statically held high or low. Erase-Suspend/Erase-Resume Commands The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing one byte command sequence with EraseSuspend command (B0H). The device automatically enters read mode typically within 20 s after the Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erase-suspended sectors/ blocks will output DQ2 toggling and DQ6 at "1". While in Erase-Suspend mode, a Word-Program operation is allowed except for the sector or block selected for Erase-Suspend. To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue Erase Resume command. The operation is executed by issuing one byte command sequence with Erase Resume command (30H) at any address in the last Byte sequence. Chip-Erase Operation The SST39WF1601/1602 provide a Chip-Erase operation, which allows the user to erase the entire memory array to the "1" state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 6 for the command sequence, Figure 10 for timing diagram, and Figure 24 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence, WP# should be statically held high or low. Write Operation Status Detection The SST39WF1601/1602 provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. (c)2013 Silicon Storage Technology, Inc. DS-20005014B 7 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet Data# Polling (DQ7) When the SST39WF1601/1602 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling timing diagram and Figure 21 for a flowchart. Toggle Bits (DQ6 and DQ2) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating "1"s and "0"s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. For Sector, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse. DQ6 will be set to "1" if a Read operation is attempted on an Erase-Suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle. An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular sector is being actively erased or erase-suspended. Table 2 shows detailed status bits information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of Write operation. See Figure 8 for Toggle Bit timing diagram and Figure 21 for a flowchart. Table 2: Write Operation Status Status DQ7 DQ6 DQ2 DQ7# Toggle No Toggle Standard Erase 0 Toggle Toggle Read from Erase-Suspended Sector/Block 1 1 Toggle Data Normal Operation Standard Program Erase-Suspend Mode Read from Non- Erase-Suspended Sector/Block Data Data Program DQ7# Toggle N/A T2.0 20005014 Note: DQ7 and DQ2 require a valid address when reading status information. (c)2013 Silicon Storage Technology, Inc. DS-20005014B 8 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet Data Protection The SST39WF1601/1602 provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Hardware Block Protection The SST39WF1602 support top hardware block protection, which protects the top 32 KWord block of the device. The SST39WF1601 support bottom hardware block protection, which protects the bottom 32 KWord block of the device. The Boot Block address ranges are described in Table 3. Program and Erase operations are prevented on the 32 KWord when WP# is low. If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase operations on that block. Table 3: Boot Block Address Ranges Product Address Range Bottom Boot Block SST39WF1601 000000H-007FFFH Top Boot Block SST39WF1602 0F8000H-0FFFFFH T3.0 20005014 Hardware Reset (RST#) The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode. When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place (see Figure 16). The Erase or Program operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. Software Data Protection (SDP) The SST39WF1601/1602 provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or powerdown. Any Erase operation requires the inclusion of six-byte sequence. These devices are shipped with the Software Data Protection permanently enabled. See Table 6 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value, during any SDP command sequence. (c)2013 Silicon Storage Technology, Inc. DS-20005014B 9 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet Common Flash Memory Interface (CFI) The SST39WF1601/1602 contain the CFI information to describe the characteristics of the device. The SST39WF1601/1602 support the original SST CFI Query mode implementation for compatibility with existing SST devices as well as the general CFI Query mode. Both will be explained in subsequent paragraphs. In order to enter the SST CFI Query mode, the system must write the three-byte sequence, same as the product ID entry command with 98H (CFI Query command) to address 5555H in the last byte sequence. Once the device enters CFI Query mode, the system can read CFI data at the addresses given in Tables 7 through 9. The system must write the CFI Exit command to return to Read mode from the CFI Query mode. In order to enter the general CFI Query mode, the system must write a one-byte sequence with entry command with 98H to address 55H. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 7 through 9. The system must write the CFI Exit command to return to Read mode from the CFI Query mode. Product Identification The Product Identification mode identifies the devices as the SST39WF1601, SST39WF1602 and manufacturer as SST. This mode may be accessed software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 6 for software operation, Figure 12 for the Software ID Entry and Read timing diagram and Figure 22 for the Software ID Entry command sequence flowchart. Table 4: Product Identification Address Data 0000H BFH SST39WF1601 0001H BF274B SST39WF1602 0001H BF274A Manufacturer's ID Device ID T4.0 20005014 Product Identification Mode Exit/CFI Mode Exit In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program or Erase operation. See Table 6 for software command codes, Figure 14 for timing waveform, and Figures 22 and 23 for flowcharts. (c)2013 Silicon Storage Technology, Inc. DS-20005014B 10 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet Security ID The SST39WF1601/1602 devices offer a 256-bit Security ID space. The Secure ID space is divided into two 128-bit segments - one factory programmed segment and one user programmed segment. The first segment is programmed and locked at SST with a random 128-bit number. The user segment is left un-programmed for the customer to program as desired. To program the user segment of the Security ID, the user must use the Security ID Word-Program command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once this is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither Sec ID segment can be erased. The Secure ID space can be queried by executing a three-byte command sequence with Enter Sec ID command (88H) at address 5555H in the last byte sequence. To exit this mode, the Exit Sec ID command should be executed. Refer to Table 6 for more details. (c)2013 Silicon Storage Technology, Inc. DS-20005014B 11 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet Operations Table 5: Operation Modes Selection Mode CE# OE# WE# DQ Address Read VIL VIL VIH DOUT AIN Program VIL VIH VIL DIN AIN VIL X1 Sector or block address, XXH for Chip-Erase Erase VIL Standby VIH X X High Z X X VIL X High Z/ DOUT X X X VIH High Z/ DOUT X VIL VIL VIH Write Inhibit VIH Product Identification Software Mode See Table 6 T5.0 20005014 1. X can be VIL or VIH, but no other value. Table 6: Software Command Sequence Command Sequence 1st Bus Write Cycle Addr1 2nd Bus Write Cycle 3rd Bus Write Cycle Data2 Addr1 Data2 Addr1 Data2 4th Bus Write Cycle Addr1 5th Bus Write Cycle 6th Bus Write Cycle Data2 Addr1 Data2 Addr1 Data2 Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA3 Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX4 30H Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX4 50H Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Erase-Suspend XXXXH B0H Erase-Resume XXXXH 30H Query Sec ID5 5555H AAH 2AAAH 55H 5555H 88H User Security ID Word-Program 5555H AAH 2AAAH 55H 5555H A5H WA6 Data User Security ID Program Lock-Out 5555H AAH 2AAAH 55H 5555H 85H XXH6 0000 H Software ID Entry7,8 5555H AAH 2AAAH 55H 5555H 90H SST CFI Query Entry 2AAAH 55H 5555H 98H 2AAAH 55H 5555H F0H 5555H AAH General CFI Query Mode 55H 98H Software ID Exit9,10 /CFI Exit/Sec ID Exit 5555H AAH Software ID Exit9,10 /CFI Exit/Sec ID Exit XXH F0H Data T6.0 20005014 1. Address format A14-A0 (Hex). Addresses A15-A19 can be VIL or VIH, but no other value, for Command sequence for SST39WF1601/1602. 2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence 3. WA = Program Word address 4. SAX for Sector-Erase; uses AMS-A11 address lines BAX, for Block-Erase; uses AMS-A15 address lines AMS = Most significant address AMS = A19 for SST39WF1601/1602 (c)2013 Silicon Storage Technology, Inc. DS-20005014B 12 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet 5. With AMS-A4 = 0; Sec ID is read with A3-A0, SST ID is read with A3 = 0 (Address range = 000000H to 000007H), User ID is read with A3 = 1 (Address range = 000008H to 00000FH). User ID Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0. 6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000008H to 00000FH. 7. The device does not remain in Software Product ID Mode if powered down. 8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0, SST39WF1601 Device ID = BF274BH, is read with A0 = 1, SST39WF1602 Device ID = BF274AH, is read with A0 = 1. AMS = Most significant address AMS = A19 for SST39WF1601/1602 9. Both Software ID Exit operations are equivalent 10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID mode again (the programmed "0" bits cannot be reversed to "1"). Valid Word-Addresses for Sec ID are from 000000H-000007H and 000008H to 00000FH. Table 7: CFI Query Identification String1 Address Data 10H 0051H 11H 0052H 12H 0059H 13H 0002H 14H 0000H 15H 0000H 16H 0000H 17H 0000H 18H 0000H 19H 0000H 1AH 0000H Data Query Unique ASCII string "QRY" Primary OEM command set Address for Primary Extended Table Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits) T7.0 20005014 1. Refer to CFI publication 100 for more details. Table 8: System Interface Information Address 1BH 1DH 1EH 1FH 20H 21H 22H 23H Data Data 0016H VDD Min (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 0020H VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 0000H VPP min. (00H = no VPP pin) 0000H VPP max. (00H = no VPP pin) 0005H Typical time out for Word-Program 2N s (25 = 32 s) 0000H Typical time out for min. size buffer program 2N s (00H = not supported) 0005H Typical time out for individual Sector/Block-Erase 2N ms (25 = 30 ms) 0007H Typical time out for Chip-Erase 2N ms (27 = 128 ms) 0001H Maximum time out for Word-Program 2N times typical (21 x 25 = 64 s) 24H 25H 26H 0000H 0001H 0001H 1CH Maximum time out for buffer program 2N times typical Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 25 = 64 ms) Maximum time out for Chip-Erase 2N times typical (21 x 27 = 256 ms) T8.0 20005014 (c)2013 Silicon Storage Technology, Inc. DS-20005014B 13 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet Table 9: Device Geometry Information Address Data 27H 0015H Data Device size = 2N Bytes (15H = 21; 221 = 2 MByte) 28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface 29H 0000H 2AH 0000H 2BH 0000H Maximum number of byte in multi-byte write = 2N (00H = not supported) 2CH 0002H Number of Erase Sector/Block sizes supported by device 2DH 00FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size) 2EH 0001H y = 511 + 1 = 512 sectors (01FF = 511) 2FH 0010H 30H 0000H z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16) 31H 001FH Block Information (y + 1 = Number of blocks; z x 256B = block size) 32H 0000H y = 31 + 1 = 32 blocks (001F = 31) 33H 0000H 34H 0001H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256) T9.0 20005014 (c)2013 Silicon Storage Technology, Inc. DS-20005014B 14 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. Table 10: Operating Range Range Commercial Industrial Ambient Temp VDD 0C to +70C 1.65-1.95V -40C to +85C 1.65-1.95V T10.1 20005014 Table 11: AC Conditions of Test1 Input Rise/Fall Time Output Load 5ns CL = 30 pF T11.1 20005014 1. See Figures 18 and 19 (c)2013 Silicon Storage Technology, Inc. DS-20005014B 15 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet Table 12: DC Operating Characteristics VDD = 1.65-1.95V1 Limits Symbol Parameter IDD Power Supply Current Min Max Units Read 10 mA Test Conditions Address input=VILT/VIHT, at f=5 MHz, VDD=VDD Max CE#=VIL, OE#=WE#=VIH, all I/Os open CE#=WE#=VIL, OE#=VIH Program and Erase 25 mA ISB IALP Standby VDD Current2 Auto Low Power 40 40 A A ILI ILIW Input Leakage Current 1 A Input Leakage Current on WP# pin and RST# 10 A WP#=GND to VDD or RST#=GND to VDD ILO VIL VIH VOL VOH Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 1 0.2VDD A V V V V VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min 0.8VDD 0.1 VDD-0.1 CE#=VIHC, VDD=VDD Max CE#=VILC, VDD=VDD Max All inputs=VSS or VDD, WE#=VIHC VIN=GND to VDD, VDD=VDD Max T12.0 20005014 1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25C (room temperature), and VDD = 1.8V. Not 100% tested. 2. For all SST39WF160x commercial and industrial devices, ISB typical is under 5 A. Table 13: Recommended System Power-up Timings Symbol TPU-READ Parameter 1 TPU-WRITE1 Minimum Units Power-up to Read Operation 100 s Power-up to Program/Erase Operation 100 s T13.0 20005014 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Table 14: Capacitance (TA = 25C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum CI/O1 I/O Pin Capacitance VI/O = 0V 12 pF Input Capacitance VIN = 0V 1 CIN 6 pF T14.0 20005014 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Table 15: Reliability Characteristics Symbol Parameter Minimum Specification Units Test Method NEND1,2 TDR1 ILTH1 Endurance 10,000 Cycles JEDEC Standard A117 100 Years JEDEC Standard A103 100 + IDD mA JEDEC Standard 78 Data Retention Latch Up T15.0 20005014 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a higher minimum specification. (c)2013 Silicon Storage Technology, Inc. DS-20005014B 16 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet AC Characteristics Table 16: Read Cycle Timing Parameters VDD = 1.65-1.95V Symbol Parameter Min Max Units TRC Read Cycle Time TCE Chip Enable Access Time 70 70 ns ns TAA Address Access Time 70 ns TOE Output Enable Access Time 35 ns 1 CE# Low to Active Output 0 ns TOLZ1 OE# Low to Active Output 0 ns TCLZ 1 CE# High to High-Z Output 40 ns TOHZ1 OE# High to High-Z Output 40 ns TOH1 TRP1 Output Hold from Address Change 0 ns RST# Pulse Width 500 ns TRHR1 RST# High before Read 50 TRY1,2 RST# Pin Low to Read Mode TCHZ ns 203 s T16.0 20005014 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-Erase operations. 3. This parameter is 100 s if reset after an Erase operation. Table 17: Program/Erase Cycle Timing Parameters Symbol Parameter TBP Word-Program Time Min Max Units 40 s TAS Address Setup Time 0 ns TAH Address Hold Time 50 ns TCS WE# and CE# Setup Time 0 ns TCH WE# and CE# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 10 ns TCP CE# Pulse Width 50 ns TWP WE# Pulse Width 50 ns TWPH1 WE# Pulse Width High 30 ns TCPH1 CE# Pulse Width High 30 ns TDS Data Setup Time 50 ns TDH1 Data Hold Time 0 ns 1 TIDA Software ID Access and Exit Time 150 ns TSE Sector-Erase 50 ms TBE Block-Erase 50 ms TSCE Chip-Erase 200 ms T17.0 20005014 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2013 Silicon Storage Technology, Inc. DS-20005014B 17 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet TRC TAA ADDRESS A19-0 TCE CE# TOE OE# TOHZ TOLZ VIH WE# HIGH-Z DQ15-0 TCHZ TOH TCLZ DATA VALID HIGH-Z DATA VALID 1297 F03.1 Figure 4: Read Cycle Timing Diagram INTERNAL PROGRAM OPERATION STARTS TBP 5555 ADDRESS A19-0 2AAA 5555 ADDR TAH TDH TWP WE# TAS TDS TWPH OE# TCH CE# TCS DQ15-0 XXAA XX55 XXA0 DATA SW0 SW1 SW2 WORD (ADDR/DATA) 1297 F04.1 Note: WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1s after the command sequence. X can be VIL or VIH, but no other value. Figure 5: WE# Controlled Program Cycle Timing Diagram (c)2013 Silicon Storage Technology, Inc. DS-20005014B 18 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet INTERNAL PROGRAM OPERATION STARTS TBP 5555 ADDRESS A19-0 2AAA 5555 ADDR TAH TDH TCP CE# TAS TCPH TDS OE# TCH WE# TCS DQ15-0 XXAA XX55 XXA0 DATA SW0 SW1 SW2 WORD (ADDR/DATA) 1297 F05.1 Note: WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1s after the command sequence. X can be VIL or VIH, but no other value. Figure 6: CE# Controlled Program Cycle Timing Diagram ADDRESS A19-0 TCE CE# TOES TOEH OE# TOE WE# DQ7 DATA DATA# DATA# DATA 1297 F06.1 Figure 7: Data# Polling Timing Diagram (c)2013 Silicon Storage Technology, Inc. DS-20005014B 19 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet ADDRESS A19-0 TCE CE# TOEH TOES TOE OE# WE# DQ6 and DQ2 TWO READ CYCLES WITH SAME OUTPUTS 1297 F07.1 Figure 8: Toggle Bits Timing Diagram TSCE SIX-BYTE CODE FOR CHIP-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA 5555 CE# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX10 SW0 SW1 SW2 SW3 SW4 SW5 1297 F08.1 Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 17.) WP# must be held in proper logic state (VIH) 1 s prior to and 1s after the command sequence. X can be VIL or VIH, but no other value. Figure 9: WE# Controlled Chip-Erase Timing Diagram (c)2013 Silicon Storage Technology, Inc. DS-20005014B 20 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet SIX-BYTE CODE FOR BLOCK-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA TBE BAX CE# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX50 SW0 SW1 SW2 SW3 SW4 SW5 1297 F09.1 Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 17.) BAX = Block Address WP# must be held in proper logic state (VIH) 1 s prior to and 1 s after the command sequence. X can be VIL or VIH, but no other value. Figure 10:WE# Controlled Block-Erase Timing Diagram TSE SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA SAX CE# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX30 SW0 SW1 SW2 SW3 SW4 SW5 1297 F10.1 Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 17.) SAX = Sector Address WP# must be held in proper logic state (VIH) 1 s prior to and 1s after the command sequence. X can be VIL or VIH, but no other value. Figure 11:WE# Controlled Sector-Erase Timing Diagram (c)2013 Silicon Storage Technology, Inc. DS-20005014B 21 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet Three-Byte Sequence for Software ID Entry ADDRESS A14-0 5555 2AAA 5555 0000 0001 CE# OE# TIDA TWP WE# TWPH DQ15-0 TAA XXAA XX55 XX90 SW0 SW1 SW2 00BF Device ID 1297 F11.1 Note: WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1s after the command sequence. Device ID - See Table 4 X can be VIL or VIH, but no other value. Figure 12:Software ID Entry and Read Three-Byte Sequence for CFI Query Entry ADDRESS A14-0 5555 2AAA 5555 CE# OE# TIDA TWP WE# TWPH DQ15-0 TAA XXAA XX55 XX98 SW0 SW1 SW2 1297 F12.1 Note: WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1s after the command sequence. X can be VIL or VIH, but no other value. Figure 13:CFI Query Entry and Read (c)2013 Silicon Storage Technology, Inc. DS-20005014B 22 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESS A14-0 5555 DQ15-0 2AAA XXAA 5555 XX55 XXF0 TIDA CE# OE# TWP WE# TWHP SW0 SW1 SW2 1297 F13.1 Note: WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1s after the command sequence. X can be VIL or VIH, but no other value. Figure 14:Software ID Exit/CFI Exit THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY ADDRESS A19-0 5555 2AAA 5555 CE# OE# TIDA TWP WE# TWPH DQ15-0 TAA XXAA XX55 XX88 SW0 SW1 SW2 1297 F20.1 Note: WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1s after the command sequence. X can be VIL or VIH, but no other value. Figure 15:Sec ID Entry (c)2013 Silicon Storage Technology, Inc. DS-20005014B 23 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet TRP RST# CE#/OE# TRHR 1297 F22.0 Figure 16:RST# Timing Diagram (When no internal operation is in progress) TRP RST# TRY CE#/OE# End-of-Write Detection (Toggle-Bit) 1297 F23.1 Figure 17:RST# Timing Diagram (During Program or Erase operation) (c)2013 Silicon Storage Technology, Inc. DS-20005014B 24 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet VIHT INPUT VIT VOT REFERENCE POINTS OUTPUT VILT 1297 F14.1 AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test Figure 18:AC Input/Output Reference Waveforms VDD TO TESTER 25K TO DUT CL 25K 1297 F15.1 Figure 19:A Test Load Example (c)2013 Silicon Storage Technology, Inc. DS-20005014B 25 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet Start Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XXA0H Address: 5555H Load Word Address/Word Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 1297 F16.0 Note: X can be VIL or VIH, but no other value. Figure 20:Word-Program Algorithm (c)2013 Silicon Storage Technology, Inc. DS-20005014B 26 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet Internal Timer Toggle Bit Data# Polling Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated Wait TBP, TSCE, TSE or TBE Read word Read DQ7 Read same word Program/Erase Completed No Is DQ7 = true data Yes No Does DQ6 match Program/Erase Completed Yes Program/Erase Completed 1297 F17.0 Figure 21:Wait Options (c)2013 Silicon Storage Technology, Inc. DS-20005014B 27 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet General CFI Query Entry CFI Query Entry Command Sequence Command Sequence Software Product ID Sec ID Query Entry Entry Command Sequence Command Sequence Load data: XX98H Address: 55H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Wait TIDA Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Read CFI data Load data: XX98H Address: 5555H Load data: XX88H Address: 5555H Load data: XX90H Address: 5555H Wait TIDA Wait TIDA Wait TIDA Read CFI data Read Sec ID Read Software ID 1297 F21.0 Note: X can be VIL or VIH, but no other value. Figure 22:Software ID/CFI Entry Command Flowcharts (c)2013 Silicon Storage Technology, Inc. DS-20005014B 28 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet Software ID Exit/CFI Exit/Sec ID Exit Command Sequence Load data: XXAAH Address: 5555H Load data: XXF0H Address: XXH Load data: XX55H Address: 2AAAH Wait TIDA Load data: XXF0H Address: 5555H Return to normal operation Wait TIDA Return to normal operation 1297 F18.0 Note: X can be VIL or VIH, but no other value. Figure 23:Software ID/CFI Exit Command Flowcharts (c)2013 Silicon Storage Technology, Inc. DS-20005014B 29 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet Chip-Erase Command Sequence Sector-Erase Command Sequence Block-Erase Command Sequence Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX80H Address: 5555H Load data: XX80H Address: 5555H Load data: XX80H Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX10H Address: 5555H Load data: XX30H Address: SAX Load data: XX50H Address: BAX Wait TSCE Wait TSE Wait TBE Chip erased to FFFFH Sector erased to FFFFH Block erased to FFFFH 1297 F19.0 Note: X can be VIL or VIH, but no other value. Figure 24:Erase Command Sequence (c)2013 Silicon Storage Technology, Inc. DS-20005014B 30 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet Product Ordering Information SST 39 WF XX XX 1601 XXXX - 70 XX - 4C XX - B3KE XXXX - MQ1 XXX Automotive Grade Indicator blank = standard parts MQ1/MQ2 = Automotive Grade 3 Environmental Attribute E1 = non-Pb Package Modifier K = 48 balls Q = 48 balls (66 possible positions) Package Type B3 = TFBGA (6mm x 8mm) MB = WFBGA (5mm x 6mm) MA = WFBGA (4mm x 6mm) Temperature Range C = Commercial = 0C to +70C I = Industrial = -40C to +85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns Hardware Block Protection 1 = Bottom Boot-Block 2 = Top Boot-Block Device Density 160 = 16 Mbit Voltage W = 1.65-1.95V Product Series 39 = Multi-Purpose Flash 1. Environmental suffix "E" denotes non-Pb solder. Non-Pb solder devices are "RoHS Compliant". (c)2013 Silicon Storage Technology, Inc. DS-20005014B 31 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet Valid Combinations for SST39WF1601 SST39WF1601-70-4C-B3KE SST39WF1601-70-4I-B3KE SST39WF1601-70-4C-MAQE SST39WF1601-70-4I-MAQE Valid Combinations for SST39WF1602 SST39WF1602-70-4C-B3KE SST39WF1602-70-4I-B3KE SST39WF1602-70-4C-MAQE SST39WF1602-70-4I-MAQE Valid Combinations for Automotive Grade 3 SST39WF1601-70-4I-B3KE-MQ1 SST39WF1602-70-4I-B3KE-MQ2 Note:Automotive-qualified devices are only available in the B3KE package. Qualification and characterization are performed according to the Automotive Electronics Council's requirement AEC-Q100, Revision G. Note:Valid combinations are those products in mass production or will be in mass production. Consult your Microchip sales representative to confirm availability of valid combinations and to determine availability of new combinations. (c)2013 Silicon Storage Technology, Inc. DS-20005014B 32 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet Packaging Diagrams TOP VIEW BOTTOM VIEW 8.00 0.10 5.60 0.45 0.05 (48X) 0.80 6 6 5 5 4 4.00 6.00 0.10 3 4 3 2 2 1 1 0.80 A B C D E F G H A1 CORNER SIDE VIEW H G F E D C B A 1.10 0.10 A1 CORNER 0.12 SEATING PLANE 1mm 0.35 0.05 Note: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size is 0.38 mm ( 0.05 mm) 48-tfbga-B3K-6x8-450mic-5 Figure 25:48-ball Thin-Profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm Package Code: B3K (c)2013 Silicon Storage Technology, Inc. DS-20005014B 33 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet TOP VIEW BOTTOM VIEW 5.00 6.00 0.08 6 5 4 3 2 1 0.50 4.00 0.08 0.50 A1 CORNER DETAIL 6 5 4 3 2 1 2.50 A B C D E F G H J K L 0.32 0.05 (48X) L K J H G F E D C B A A1 INDICATOR 0.73 max. 0.636 nom. SIDE VIEW 0.08 SEATING PLANE 0.20 0.06 Note: 1mm 1. Complies with JEDEC Publication 95, MO-207, Variant CB-4 except nominal ball size is larger and bottom side A1 indicator is triangle at corner. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.08 mm 4. Ball opening size is 0.29 mm ( 0.05 mm) 48-wfbga-MAQ-4x6-32mic-2.0 Figure 26:48-ball Very-Very-Thin-Profile, Fine-pitch Ball Grid Array (WFBGA) 4mm x 6mm Package Code MAQ (c)2013 Silicon Storage Technology, Inc. DS-20005014B 34 11/2013 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data Sheet Table 18: Revision History Number 00 01 02 Description * * * * * * * 04 * * 05 * 03 06 A B * * * * * * * Date Initial release Added MBQ package information including product numbers. Migrated document to Preliminary Specifications Updated Table 12 on page 16 Added 70 ns to Features: Fast Read Access Time Added 70 ns columns to Table 16 Edited Product Ordering Information and Valid Combination to include 70 ns and remove leaded parts. Added YIQE package Changed 000010H to 000017H to 000008H to 00000FH three places in footnotes of Table 6 on page 12. EOL of SST39WF1601-70-4C-Y1QE, SST39WF1601-70-4I-Y1QE, SST39WF1602-70-4C-Y1QE, and SST39WF1602-70-4I-Y1QE. Replacement parts SST39WF1601-70-4C-MAQE, SST39WF1601-70-4IMAQE, SST39WF1602-70-4C-MAQE, and SST39WF1602-70-4I-MAQE in this document. Added MAQE package drawing and information. Removed all 90ns speed products EOL of MBQE products. Applied new document format Released document under new letter revision system Updated spec number S71297 to DS-20005014 Added information about Automotive Grade 3 parts Oct 2005 Jul 2006 Aug 2007 Jul 2008 Dec 2008 Nov 2009 Jan 2011 Apr 2011 Nov 2013 ISBN:978-1-62077-612-4 (c) 2013 Silicon Storage Technology, Inc-a Microchip Technology Company. All rights reserved. SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and registered trademarks mentioned herein are the property of their respective owners. Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging. Memory sizes denote raw storage capacity; actual usable capacity may be less. SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of Sale. For sales office locations and information, please see www.microchip.com. Silicon Storage Technology, Inc. A Microchip Technology Company www.microchip.com (c)2013 Silicon Storage Technology, Inc. DS-20005014B 35 11/2013