Automotive Power
Data Sheet
Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
coreFLEX TLE8110EE
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Data Sheet 2 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Table of Content
Table of Content
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 Description Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Electrical Characteristics Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Reset and Enable Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1 Description Reset and Enable Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 Electrical Characteristics Reset Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7 Power Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1 Description Power Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.2 Description of the Clamping Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.3 Electrical Characteristics Power Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.4 Parallel Connection of the Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8 Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.1 Diagnosis Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.1.1 Open Load diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.1.2 Overcurrent / Overtemperature diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.2 Electrical Characteristics Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9 Parallel Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.1 Description Parallel Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.2 Electrical Characteristics Parallel Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.1 Electrical Characteristics Overload Protection Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11 16 bit SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
11.1 Description 16 bit SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
11.2 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
11.3 Electrical Characteristics 16 bit SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12 Control of the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.1 Internal Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.2 SPI Interface. Signals and Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.2.1 Description 16 bit SPI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.2.2 Daisy Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.2.3 SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.2.3.1 16-bit protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.2.3.2 2x8-bit protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
12.2.3.3 16- and 2x8-bit protocol mixed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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TLE 8110 EE
Smart Multichannel Switch
Table of Content
Data Sheet 3 Rev. 1.3.1, 2011-05-26
12.2.3.4 Daisy-Chain and 2x8-bit protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
12.2.4 safeCOMMUNICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12.2.4.1 Encoding of the commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12.2.4.2 Modulo-8 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12.3 Register and Command - Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12.3.1 CMD - Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
12.3.1.1 CMD_RSD - Command: Return Short Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.3.1.2 CMD_RSDS - Command: Return Short Diagnosis and Device Status . . . . . . . . . . . . . . . . . . . . 57
12.3.1.3 CMD_RPC - Command: Return Pattern Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
12.3.1.4 CMD_RINx - Command: Return Input Pin (INx) -Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
12.3.2 DCC - Diagnosis Registers and compactCONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
12.3.2.1 DRx - Diagnosis Registers Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
12.3.2.2 DRx - Return on DRx Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.3.2.3 DMSx/OPSx - Diagnosis Mode Set / Output Pin Set Commands . . . . . . . . . . . . . . . . . . . . . . . . 66
12.3.3 OUTx - Output Control Register CHx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
12.3.4 ISx - INPUT or Serial Mode Control Register, Bank A and Bank B . . . . . . . . . . . . . . . . . . . . . . . . . 69
12.3.5 PMx - Parallel Mode Register CHx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
12.3.6 DEVS - Device Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
13 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
14 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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PG-DSO-36-41
Type Package Marking
TLE8110EE PG-DSO-36-41 TLE8110EE
Data Sheet 4 Rev. 1.3.1, 2011-05-26
Smart Multichannel Low Side Switch with Parallel
Control and SPI Interface
coreFLEX
TLE8110EE
1Overview
Features
• Overvoltage, Overtemperature, ESD -Protection
• Direct Parallel PWM Control of all Channels
•safeCOMMUNICATION (SPI and Parallel)
• Efficient Communication Mode: compactCONTROL
• Compatible with 3.3V- and 5V- Micro Controllers I/O ports
•clampSAFE for highly efficient parallel use of the channels
• Green Product (RoHS compliant)
• AEC Qualified
Application
• Power Switch Automotive and Industrial Systems switching Solenoids, Relays and Resistive Loads
Description
10-channel Low-Side Switch in Smart Power Technology [SPT] with Serial Peripheral Interface [SPI] and 10 open
drain DMOS output stages. The TLE8110EE is protected by embedded protection functions and designed for
automotive and industrial applications. The output stages are controlled via Parallel Input Pins for PWM use or SPI
Interface. The TLE8110EE is particularly suitable for Engine Management and Powertrain Systems.
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TLE 8110 EE
Smart Multichannel Switch
Overview
Data Sheet 5 Rev. 1.3.1, 2011-05-26
Figure 1 Block Diagram TLE8110EE
Table 1 Product Summary
Parameter Symbol Value Unit
Analogue Supply voltage VDD 4.50 … 5.50 V
Digital Supply Voltage VCC 3.00 … 5.50 V
Clamping Voltage (CH 1-10) VDS(CL)typ 55 V
On Resistance
typical at Tj=25°C and IDnom
RON1-4 0.30 Ω
RON5-6 0.25 Ω
RON7-10 0.60 Ω
On Resistance
maximum at Tj=150°C and IDnom
RON1-4 0.60 Ω
RON5-6 0.50 Ω
RON7-10 1.20 Ω
Nominal Output current (CH 1-4) IDnom 1.50 A
Nominal Output current (CH 5-6) IDnom 1.70 A
Nominal Output current (CH 7-10) IDnom 0.75 A
Output Current Shut-down Threshold (CH 1-4) min. IDSD(low) 2.60 A
Output Current Shut-down Threshold (CH 5-6) min. IDSD(low) 3.70 A
Output Current Shut-down Threshold (CH 7-10) min. IDSD(low) 1.70 A
Micro
Controller
TLE8110 EE
I/O
I/O
IN1
IN10
SPI _ SI SPI _SI
SPI_SO
SPI _ SO
SPI _ CLK SPI _ CLK
SPI_CSSPI _ CS
V
DD
= typ. 5V
V
CC
= typ . 3. 3….5 V
RST
Supply IC
V
Ba tt
4 to 6
Injectors
or Solenoids
General pur pose
Channels i n
parallel connecti on
General pur pose
Channels for Relays
OUT1
OUT10
Appl _ D iag_ 10 c h_TLE 8110 .vsd
ENI/O
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Data Sheet 6 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Block Diagram
2 Block Diagram
Figure 2 Block Diagram
2.1 Description
Communication
The TLE8110EE is a 10-channel low-side switch in PG-DSO-36-41 package providing embedded protection
functions. The 16-bit serial peripheral interface (SPI) can be utilized for control and diagnosis of the device and
the loads. The SPI interface provides daisy-chain capability in order to assemble multiple devices in one SPI chain
by using the same number of micro-controller pins 1).
The analogue and the digital part of the device is supplied by 5V. Logic Input and Output Signals are then
compatible to 5V logic level [TTL - level]. Optionally, the logic part can be supplied with lower voltages to achieve
signal compatibility with e.g. 3.3V logic level [CMOS - level].
The TLE8110EE is equipped with 10 parallel input pins that are routed to each output channel. This allows control
of the channels for loads driven by Pulse Width Modulation (PWM). The output channels can also be controlled
by SPI.
Reset
The device is equipped with one Reset Pin and one Enable. Reset [RST] serves the whole device, Enable [EN]
serves only the Output Control Unit and the Power Stages.
1) Daisy Chain
Block_diag_10ch_TLE8110.vsd
S_CS
S_SI
S_CLK
S_SO
SPI
(TTL or
CMOS)
open load
detection
temperature
sensor
diagnosis
register
OUT4
OUT3
OUT2
OUT1
gate
control
short circuit
detection
input
register
VCC
Input Control
(TTL or CMOS)
IN3
VDD
RST
OUT8
OUT7
OUT6
OUT5
OUT10
OUT9
short to GND
detection
IN4
IN5
IN6
IN7
IN8
IN9
IN10
IN1
IN2
control
register
Logic
control
unit
analogue
control,
diagnostic
and protective
functions
EN
GND
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TLE 8110 EE
Smart Multichannel Switch
Block Diagram
Data Sheet 7 Rev. 1.3.1, 2011-05-26
Diagnosis
The device provides diagnosis of the load, including open load, short to GND as well as short circuit to VBatt
detection and over-load / over-temperature indication. The SPI diagnosis flags indicates if latched fault conditions
may have occurred.
Protection
Each output stage is protected against short circuit. In case of over load, the affected channel is switched off. The
switching off reaction time is dependent on two switching thresholds. Restart of the channel is done by clearing
the Diagnosis Register 1). This feature protects the device against uncontrolled repetitive short circuits. The
reaction to a short-circuit and over-temperature can be alternatively changed to further modes, such as semi- or
auto - restart of the affected channel.
There is a temperature sensor available for each channel to protect the device in case of over temperature. In case
of over temperature the affected channel is switched off and the Over-Temperature Flag is set. Restart of the
channel is done by deleting the Flag. This feature protects the device against uncontrolled temperature toggling.
Parallel Connection of Channels
The device is featured with a central clamping structure, so-called CLAMPsafe. This feature ensures a balanced
clamping between the channels and allows in case of parallel connection of channels a high efficient usage of the
channel capabilities. This parallel mode is additionally featured by best possible parameter- and thermal matching
of the channels and by controlling the channels accordingly.
1) Restart after Clear
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Data Sheet 8 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Pin Configuration
3 Pin Configuration
3.1 Pin Assignment
Figure 3 Pin Configuration
3.2 Pin Definitions and Functions
Pin Symbol Function
1 GND Ground
2 P_IN1 Parallel Input Pin 1. Default assignment to Output Channel 1.
3 P_IN2 Parallel Input Pin 2. Default assignment to Output Channel 2.
4 EN Enable Input Pin. If not needed, connect with Pull-up resistor to VCC.
5RST Reset Input Pin. (low active). If not needed, connect with Pull-up resistor to VCC.
6 P_IN3 Parallel Input Pin 3. Default assignment to Output Channel 3.
7 P_IN4 Parallel Input Pin 4. Default assignment to Output Channel 4.
8 VDD Analogue Supply Voltage
9 P_IN5 Parallel Input Pin 5. Default assignment to Output Channel 5.
10 VCC Digital Supply Voltage
11 S_SO Serial Peripheral Interface [SPI], Serial Output
12 S_CLK Serial Peripheral Interface [SPI], Clock Input
13 S_CS Serial Peripheral Interface [SPI], Chip Select (active Low)
14 S_SI Serial Peripheral Interface [SPI], Serial Input
15 P_IN6 Parallel Input Pin 6. Default assignment to Output Channel 6.
16 P_IN7 Parallel Input Pin 7. Default assignment to Output Channel 7.
17 P_IN8 Parallel Input Pin 8. Default assignment to Output Channel 8.
18 GND Ground
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
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TLE 8110 EE
Smart Multichannel Switch
Pin Configuration
Data Sheet 9 Rev. 1.3.1, 2011-05-26
19 GND Ground
20 OUT9 Drain of Power Transistor Channel 9
21 OUT10 Drain of Power Transistor Channel 10
22 N.C. internally not connected, connect to Ground
23 GND Ground
24 OUT6 Drain of Power Transistor Channel 6
25 OUT4 Drain of Power Transistor Channel 4
26 OUT3 Drain of Power Transistor Channel 3
27 P_IN9 Parallel Input Pin 9. Default assignment to Output Channel 9.
28 P_IN10 Parallel Input Pin 10. Default assignment to Output Channel 10.
29 OUT2 Drain of Power Transistor Channel 2
30 OUT1 Drain of Power Transistor Channel 1
31 OUT5 Drain of Power Transistor Channel 5
32 GND Ground
33 N.C. internally not connected, connect to Ground
34 OUT8 Drain of Power Transistor Channel 8
35 OUT7 Drain of Power Transistor Channel 7
36 GND Ground
Cooling
Tab
GND Cooling Tab; internally connected to GND
Pin Symbol Function
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Data Sheet 10 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Pin Configuration
3.3 Terms
Figure 4 Terms
Terms_TLE8110.vsd
V
P_IN2
V
RST
V
P_IN3
V
P_IN4
V
VDD
V
P_IN5
V
VCC
V
S_SO
V
S_CLK
V
S_CS
V
S_SI
V
P_IN7
V
OUT7
V
P_IN9
V
OUT3
V
Batt
I
OUT1
I
OUT4
I
OUT2
I
P_IN10
I
P_IN9
I
OUT3
I
P_IN2
I
RST
I
S_SI
I
P_IN7
I
P_IN3
I
P_IN4
I
VDD
I
P_IN5
I
VCC
I
S_SO
I
S_CLK
I
S_CS
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
36
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
11
35
PG-DSO-36
GND
P_IN1
P_IN2
EN
RST
P_IN3
P_IN4
VDD
P_IN5
VCC
S_SO
S_CLK
S_CS
S_SI
P_IN6
P_IN7
P_IN8
GND
GND
OUT7
OUT8
N.C.
GND
OUT5
OUT1
OUT2
P_IN10
P_IN9
OUT3
OUT4
OUT6
GND
N.C.
OUT10
OUT9
GND
I
P_IN1
I
EN
I
P_IN6
I
P_IN8
V
P_IN1
V
EN
V
P_IN6
V
P_IN8
I
OUT7
I
OUT8
I
OUT5
I
OUT6
I
OUT10
I
OUT9
V
OUT8
V
OUT5
V
OUT1
V
OUT2
V
P_IN10
V
OUT4
V
OUT6
V
OUT10
V
OUT9
Top View
Heat- Slug /
Exposed Pad
(back-side)
GND
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TLE 8110 EE
Smart Multichannel Switch
General Product Characteristics
Data Sheet 11 Rev. 1.3.1, 2011-05-26
4 General Product Characteristics
4.1 Absolute Maximum Ratings
Absolute Maximum Ratings1)
Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Max.
Supply Voltages
4.1.1 Digital Supply voltage VCC -0.3 5.5 V permanent
4.1.2 Digital Supply voltage VCC -0.3 6.2 V t < 10s
4.1.3 Analogue Supply voltage VDD -0.3 5.5 V permanent
4.1.4 Analogue Supply voltage VDD -0.3 6.2 V t < 10s
Power Stages
4.1.5 Load Current (CH 1 to 10 ) IDn -I
DSD(low) A–
4.1.6 Reverse Current Output (CH 1-10) IDn -IDSD(low) -A–
4.1.7 Total Ground Current IGND -20 20 A –
4.1.8 Continuous Drain Source Voltage
(Channel 1 to 10)
VDSn -0.3 45 V –
4.1.9 maximum Voltage for short circuit
protection on Output
VDSn - 24 V one event on one
single channel.
Clamping Energy - Single Pulse2)3)
4.1.10 Single Clamping Energy
Channel Group 1-4
EAS -29mJID = 2.6A
1 single pulse
4.1.11 Single Clamping Energy
Channel Group 5-6
EAS -31mJID = 3.7A
1 single pulse
4.1.12 Single Clamping Energy
Channel Group 7-10
EAS -11mJID = 1.7A
1 single pulse
Logic Pins (SPI, INn, EN, RST)
4.1.13 Input Voltage at all Logic Pin Vx-0.3 5.5 V permanent
4.1.14 Input Voltage at all Logic Pin Vx-0.3 6.2 V t < 10s
4.1.15 Input Voltage at Pin 27, 28 (IN9, 10, ) Vx-0.3 45 V permanent
Temperatures
4.1.16 Junction Temperature Tj-40 150 °C–
4.1.17 Junction Temperature Tj-40 175 °C max. 100hrs
cumulative
4.1.18 Storage Temperature Tstg -55 150 °C–
ESD Robustness
4.1.19 Electro Static Discharge Voltage
“Human Body Model - HBM”
VESD -4 4 kV All Pins
HBM4)
1.5KOhm, 100pF
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Data Sheet 12 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
General Product Characteristics
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
4.2 Functional Range
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.1.20 Electro Static Discharge Voltage
“Charged Device Model - CDM”
VESD -500 500 V All Pins
CDM5)
4.1.21 Electro Static Discharge Voltage
“Charged Device Model - CDM”
VESD -750 750 V Pin 1, 18, 19, 36
(corner pins)
CDM5)
1) Not subject to production test, specified by design.
2) One single channel per time.
3) Triangular Pulse Shape (inductance discharge): ID(t) = ID(0)·(1 - t / tpulse); 0 < t < tpulse.
4) ESD susceptibility, HBM according to EIA/JESD 22-A114-B
5) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101-C
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Max.
Supply Voltages
4.2.1 Analogue Supply Voltage VDD 4.5 5.5 V –
4.2.2 Digital Supply Voltage VCC 3VDD V–
4.2.3 Digital Supply Voltage VCC VDD 5.5 V leakage Currents
(ICC) might increase
if VCC > VDD.
Power Stages
4.2.4 Ground Current IGND_typ 9 A resistive loads1)
1) Not subject to production test, specified by design.
Temperatures
4.2.5 Junction Temperature Tj-40 150 °C-
4.2.6 Junction Temperature Tj-40 175 °C1) for 100hrs
Absolute Maximum Ratings1) (cont’d)
Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Max.
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TLE 8110 EE
Smart Multichannel Switch
General Product Characteristics
Data Sheet 13 Rev. 1.3.1, 2011-05-26
4.3 Thermal Resistance
Figure 5 PG-DSO-36-41 PCB set-up
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
4.3.1 Junction to Soldering Point RthJSP - 1.75 3.60 K/W Pvtot = 3W1)2)3)
1) Not subject to production test, specified by design.
2) Homogenous power distribution over all channels (All Power stages equally heated), dependent on cooling set-up.
3) Refer to Figure 5
4.3.2 Junction to Ambient RthJA - 25.00 - K/W Pvtot = 3W1)2)3)
Metallization:
Dimensions:
Thermal Vias:
Rth PCB setup.vsd
1.5mm
35µm, 90% metallization
70µm modeled (traces)
35µm, 90% metallization
70µm, 5% metallization
76.2 x 114.3 x 1.5 mm³ , FR4
JEDEC 2s2p (JESD 51-7) + (JESD 51-5)
Φ=0.3 mm; plating 25 µm; 24 pcs. for PG-DSO-36-41
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Data Sheet 14 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Power Supply
5 Power Supply
5.1 Description Power Supply
The TLE8110EE is supplied by analogue power supply line VDD which is used for the analogue functions of the
device, such as the gate control of the power stages. The digital power supply line VCC is used to supply the digital
part and offers the possibility to adapt the logic level of the serial output pins to lower logic levels.
Figure 6 Block Diagram Supply and Reset
Description Supply
The Supply Voltage Pins are monitored during the power-on phase and under normal operating conditions for
under voltage.
If during Power-on the increasing supply voltage exceeds the Supply Power-on Switching Threshold, the internal
Reset is released after an internal delay has expired.
In case of under voltage, a device internal reset is performed. The Switching Threshold for this case is the Power-
on Switching threshold minus the Switching Hysteresis.
In case of under voltage on the analogue supply line VDD the outputs are turned off but the content of the registers
and the functionality of the logic part is kept alive. In case of under voltage on the digital supply VCC line, a complete
reset including the registers is performed.
After returning back to normal supply voltage and an internal delay, the related functional blocks are turned on
again. For more details, refer to the chapter “Reset”.
The device internal under-voltage set will set the related bits in SDS (Short Diagnosis and Device Status) to allow
the micro controller to detect this reset. For more information, refer to the chapter “Control of the Device”.
Block_diag_Supply_Reset.vsd
Input
and
Serial
Inter-
face
Fault
Detection
Gate Control
diagnosis
register
input
register
VDD
VCC
RST
OUTx
control
register
Logic
control
unit
EN
GND
VCC
Under
Voltage
Monitor
VDD
Under
Voltage
Monitor
oror
analogue
control,
diagnostic
and protective
functions
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TLE 8110 EE
Smart Multichannel Switch
Power Supply
Data Sheet 15 Rev. 1.3.1, 2011-05-26
5.2 Electrical Characteristics Power Supply
Electrical Characteristics: Power Supply
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Digital Supply and Power-on Reset
5.2.1 Digital Supply Voltage VCC 3- 5.5V
5.2.2
a)
b)
Digital Supply Current during Reset
(VCC < VCCpo )
ICCstb -1520µAf
SCLK = 0Hz,
S_CS = VCC,
Tj=85°C 1)
VCC = 2.0V
VDD > VCC
-2040µAf
SCLK = 0Hz,
S_CS = VCC,
Tj=150°C
VCC = 2.0V
VDD > VCC
5.2.3
a)
b)
Digital Supply Current during Reset
( VRST < VRSTl)
ICCstb - 25µAf
SCLK = 0Hz,
S_CS = VCC,
Tj=85°C1)
VDD > VCC
-515µAf
SCLK = 0Hz,
S_CS = VCC,
Tj=150°C
VDD > VCC
5.2.4
a)
b)
Digital Supply Operating Current
VCC = 3.3V
ICC -0.152mAf
SCLK = 0Hz,
Tj=150°C.
all Channels ON
1)
-0.55mAf
SCLK = 5MHz,
Tj=150°C.
all Channels ON
1)2)
5.2.5
a)
b)
Digital Supply Operating Current
VCC = 5.5V
ICC -0.252mAf
SCLK = 0Hz,
Tj=150°C.
all Channels ON
-0.810mAf
SCLK = 5MHz,
Tj=150°C.
all Channels ON
1)2)
5.2.6 Digital Supply Power-on Switching
Threshold
VCCpo 1.9 2.8 3 V VCC increasing
5.2.7 Digital Supply Switching Hysteresis VCChy 100 300 500 mV 1)
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Data Sheet 16 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Power Supply
Analogue Supply and Power-on Reset
5.2.8 Analogue Supply Voltage VDD 4.5- 5.5V -
5.2.9
a)
b)
Analogue Supply Current during
Reset
(VDD< VDDpo )
IDDstb -1020µAf
SCLK = 0Hz,
Tj=85°C 1)
VDD = 2V
-1540µAf
SCLK = 0Hz,
Tj=150°C
VDD = 2V
5.2.10
a)
b)
Analogue Supply Current during
Reset
( VEN< VENl)
IDDstb - 15µAf
SCLK = 0Hz,
Tj=85°C 1)
-215µAf
SCLK = 0Hz,
Tj=150°C
5.2.11 Analogue Supply Operating Current IDD -825mAf
SCLK = 0...5MHz1)
Tj=150°C
all Channels ON
5.2.12 Analogue Supply Power-on
Switching Threshold
VDDpo 34.24.5VVDD increasing
5.2.13 Analogue Supply Switching
Hysteresis
VDDhy 100 200 400 mV 1)
5.2.14 Analogue Supply Power-on Delay
Time
tVDDpo - 100 200 µs VDD increasing 1)
1) Parameter not subject to production test. Specified by design.
2) C = 50pF connected to S_SO
Electrical Characteristics: Power Supply
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
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TLE 8110 EE
Smart Multichannel Switch
Reset and Enable Inputs
Data Sheet 17 Rev. 1.3.1, 2011-05-26
6 Reset and Enable Inputs
6.1 Description Reset and Enable Inputs
The TLE8110EE contains one Reset- and one Enable Input Pin as can be seen in Figure 6.
Description:
Reset Pin [RST] is the main reset and acts as the internal under voltage reset monitoring of the digital supply
voltage VCC: As soon as RST is pulled low, the whole device including the control registers is reset.
The Enable Pin [EN] resets only the Output channels and the control circuits. The content of the all registers is
kept. This functions offers the possibility of a “soft” reset turning off only the Output lines but keeping alive the SPI
communication and the contents of the control registers. This allows the read out of the diagnosis and setting up
the device during or directly after Reset.
6.2 Electrical Characteristics Reset Inputs
Electrical Characteristics: Reset Inputs
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Reset Input Pin [RST]
6.2.1 Low Level of RST VRSTl -0.3 - VCC *0.2 V -
6.2.2 High Level of RST VRSTh VCC *0.4 - VCC V-
6.2.3 RST Switching Hysteresis VRSThy 20 100 300 mV 1)
1) Parameter not subject of production test. Specified by design.
6.2.4 Reset Pin pull-down Current IRSTresh 20 40 85 µA VRST=5V
IRSTresl 2.4 - - µA VRST=0.6V1)
6.2.5 Minimum Reset Duration time RST tRSTmin 1-- µs
1)
Enable Input Pin [EN]
6.2.6 Low Level of EN VENl -0.3 - VCC *0.2 V -
6.2.7 High Level of EN VENh VCC *0.4 - VCC V-
6.2.8 EN Switching Hysteresis VENhy 20 60 300 mV 1)
6.2.9 Enable Pin pull-down Current IENresh 53585µAV
EN=5V
IENresl 2.4 - - µA VEN=0.6V1)
6.2.10 Enable Reaction Time
(reaction of OUTx)
tENrr -4- µs
1)
6.2.11 Minimum Enable Duration time EN tENmin 1.2 - - µs 1)
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Data Sheet 18 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Reset and Enable Inputs
Figure 7 Timing
V
DD
OUTx
t
EN r r
t
t
Enable of
Output
Device
operating t
Enable
valid
t
VDDpo
V
EN
T<
t
EN min
V
EN h
V
EN l
V
EN h y
Exter nal _ r eset. vsd
OUTx OFF
Device ON
Device OFF
Enable
not valid
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TLE 8110 EE
Smart Multichannel Switch
Power Outputs
Data Sheet 19 Rev. 1.3.1, 2011-05-26
7 Power Outputs
7.1 Description Power Outputs
The TLE8110EE is a 10 channel low-side powertrain switch. The power stages are built by N-channel power
MOSFET transistors. The device is a universal multichannel switch but mostly suited for the use in Engine
Management Systems [EMS]. Within an EMS, the best fit of the channels to the typical loads is:
• Channel 1 to 4 for Injector valves or mid-sized solenoids with a nominal current requirement of 1.5A.
• Channel 5 to 6 for mid-sized solenoids or Injector valves with a nominal current requirement of 1.7A
• Channel 7 to 10 for small solenoids or relays with a nominal current requirement of 0.75A
Channel 1 to 10 provide enhanced clamping capabilities of typically 55V best suited for inductive loads such as
injectors and valves. It is recommended in case of an inductive load, to connect an external free wheeling- or
clamping diode, where-ever possible to reduce power dissipation.
All channels can be connected in parallel. Channels 1 to 4, 5 to 6 and 7 to 10 are prepared by matching for parallel
connection with the possibility to use a high portion of the capability of each single channel also in parallel mode
(refer to Chapter 7.4).
Channel 5 and 6 have a higher current shut down threshold to allow to connect in parallel mode a load with a high
inrush-current, such as a lambda sensor heater.
Figure 8 Block Diagram of Control and Power Outputs
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Data Sheet 20 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Power Outputs
7.2 Description of the Clamping Structure
When switching off inductive loads, the potential at pin OUT rises to VDS(CL) potential, because the inductance
intends to continue driving the current. The clamping voltage is necessary to prevent destruction of the device,
see Figure 9 for the clamping circuit principle. Nevertheless, the maximum allowed load inductance is limited.
Figure 9 Internal Clamping Principle
Clamping Energy
During demagnetization of inductive loads, energy has to be dissipated in the device. This energy can be
calculated with following equation:
(1)
The maximum energy, which is converted into heat, is limited by the thermal design of the component.
Attention: It is strongly recommended to measure the load Energy and Current under operating
conditions, example of measurement setup is shown in Figure 10. Load small-signal
parameters might not reflect the real load behavior under operating conditions, see Figure 11.
For more details please refer to the Application Note “Switching Inductive Loads”.
Figure 10 ECL measurement setup
V
bat
I
D
V
DScl
OUT
V
DS
GND
L,
R
L
OutputClam p.vsd
EV
DS CL()
LL
RL
------IL
VDS CL()VBAT
–
RL
------------------------------------- 1
RLI⋅L
VDS CL()VBAT
–
-------------------------------------
+
⎝⎠
⎛⎞
ln⋅–⋅⋅=
Low-Side Switch
VBAT
Ctrl
Load Measurement Setup
DMOS
Active Clamping
VCL
GND
vD(t)
iL(t)
Inductive Load
RL
LL
OUT
Temperature Chamber
T=TL
Oscilloscope
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TLE 8110 EE
Smart Multichannel Switch
Power Outputs
Data Sheet 21 Rev. 1.3.1, 2011-05-26
Figure 11 Deviation of calculation from measurement
7.3 Electrical Characteristics Power Outputs
Electrical Characteristics: Power Outputs
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Output Channel Resistance
7.3.1 On State Resistance
Channel Group 1-4
RDSon -0.3-OhmIDnom=1,5A;
Tj=25°C1)
- 0.45 0.6 Ohm IDnom=1,5A;
Tj=150°C
7.3.2 On State Resistance
Channel Group 5-6
RDSon - 0.25 - Ohm IDnom=1.7A;
Tj=25°C1)
- 0.35 0.5 Ohm IDnom=1.7A;
Tj=150°C
7.3.3 On State Resistance
Channel Group 7-10
RDSon -0.6-OhmIDnom=0.75A;
Tj=25°C1)
- 0.85 1.2 Ohm IDnom=0.75A;
Tj=150°C
Deviation from measured values
ON OFFCtrl
vD, iL
t
t
vD· iL
ECLm
ECL
measured
calculated
L-Saturation
Effect
R-Temp.
Effect
tF
VCL
VBAT
VON
IL
ILm
tFm
0
ON OFFCtrl
vD, iL
t
t
vD· iL
ECLm
ECL
measured
calculated
µ-increase
Effect
R-Temp.
Effect
tF
VCL
VBAT
VON
IL
ILm
tFm
0
Increasing Inductance with IL
(Relays and some Valve types)
Decreasing Inductance with IL
(Injectors, Valves)
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Data Sheet 22 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Power Outputs
Clamping Energy - Repetitive1)2)3)4)
Channel Group 1-4
7.3.4 Repetitive Clamping Energy EAR --11mJID = 1.0A
109 cycles
--12mJ
ID = 2.1A
104 cycles
--15mJ
ID = 2.6A
10 cycles 5)
Channel 5-6
7.3.5 Repetitive Clamping Energy EAR --13mJID = 1.3A
109 cycles
--15mJ
ID = 2.7A
104 cycles
--20mJ
ID = 3.2A
10 cycles 5)
Channel 7-10
7.3.6 Repetitive Clamping Energy EAR --4mJID = 0.7A
109 cycles
--4mJ
ID = 1.4A
104 cycles
--5mJ
ID = 1.7A
10 cycles 5)
Leakage Current
7.3.7 Output Leakage Current in standby
mode, Channel 1 to 4
IDoff --3µAV
DS=13.5V;
VDD=5V,
Tj=85°C1)
--8µAV
DS=13.5V;
VDD=5V,
Tj=150°C
7.3.8 Output Leakage Current in standby
mode, Channel 5 to 6
IDoff --6µAV
DS=13.5V;
VDD=5V,
Tj=85°C1)
--12µAV
DS=13.5V;
VDD=5V,
Tj=150°C
7.3.9 Output Leakage Current in standby
mode, Channel 7 to 10
IDoff --2µAV
DS=13.5V;
VDD=5V,
Tj=85°C1)
--5µAV
DS=13.5V;
VDD=5V,
Tj=150°C
Electrical Characteristics: Power Outputs (cont’d)
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
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TLE 8110 EE
Smart Multichannel Switch
Power Outputs
Data Sheet 23 Rev. 1.3.1, 2011-05-26
Clamping Voltage
7.3.10 Output Clamping Voltage, Channel
1 to 10
VDScl 45 55 60 V
Timing
7.3.11 Output Switching Frequency fOUTx - - 20 kHz 1)
resistive load
duty cycle > 25%.
7.3.12 Turn-on Time tdON -510µsV
DS=20% of Vbatt
Vbatt = 13.5V,
IDS1 to IDS6 = 1A,
IDS7 to IDS10 = 0.5A,
resistive load
7.3.13 Turn-off Time tdOFF -510µsV
DS=80% of Vbatt
Vbatt = 13.5V,
IDS1 to IDS6 = 1A,
IDS7 to IDS10 = 0.5A
resistive load
1) Parameter is not subject to production test, specified by design.
2) Either one of the values has to be considered as worst case limitation. Cumulative scenario and wide range of operating
conditions are treated in the Application Note “Switching Inductive Loads - TLE8110 addendum”.
3) This lifetime statement is an anticipation based on an extrapolation of Infineon's qualification test results. The actual lifetime
of a component depends on its form of application and type of use etc. and may deviate from such statement. The lifetime
statement shall in no event extend the agreed warranty period.
4) Triangular Pulse Shape (inductance discharge): ID(t) = ID(0)·(1 - t / tpulse); 0 < t < tpulse.
5) Repetitive operation not allowed. Starting Tj must be kept within specs. In case of high energy pulse an immediate switch-
off strategy is recommended
Electrical Characteristics: Power Outputs (cont’d)
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
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Data Sheet 24 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Power Outputs
Figure 12 CH 1-4: typical behavior of RDS_ON versus the junction temperature Tj
Figure 13 CH 5-6: typical behavior of RDS_ON versus the junction temperature Tj
-40-200 20406080100120140
0,2
0,3
0,4
0,5
0,6
Tj/°C
RDS_ON /
Ohm
RON_vs_Tj_CH1-4,6.vsd
R
DS_ON
vs. T
j
: CH 1-4 (V
DD
=5V)
-40-200 20406080100120140
0,1
0,2
0,3
0,4
0,5
Tj/°C
RDS_ON /
Ohm
RON_vs_Tj_CH5-6.vsd
R
DS_ON
vs. T
j
: CH 5-6 (V
DD
=5V)
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TLE 8110 EE
Smart Multichannel Switch
Power Outputs
Data Sheet 25 Rev. 1.3.1, 2011-05-26
Figure 14 CH7-10: typical behavior of RDS_ON versus the junction temperature Tj
Figure 15 All Channels: typical behavior of the clamping voltage versus the junction temperature
-40 -20 0 20 40 60 80 100 120 140
0.4
0.6
0.8
1.0
1.2
Tj/°C
RDS_ON /
Ohm
RON_vs_Tj_CH7-10.vsd
RDS_ON vs. Tj: CH 7-10 (V DD=5V)
-40-20 0 20406080100120140
53
54
55
56
57
Tj/°C
VCL / V
VCL_vs_Tj_all_CH.vsd
V
CLn
vs. T
j
: all Channels
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Data Sheet 26 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Power Outputs
Figure 16 Timing of Output Channel switching (resistive load)
7.4 Parallel Connection of the Power Stages
The TLE8110EE is equipped with a structure which improves the capability of parallel-connected channels. The
device can be “informed” via the PMx.PMx - bits (see chapter control of the device) which of the channels are
connected in parallel. The input channels can be mapped to the parallel connected output channels in order to
apply the PWM signals. This feature allows a flexible adaptation to different load situations within the same
hardware setup.
In case of overload the ground current and the power dissipation is increasing. The application has to take into
account that all maximum ratings are observed (e.g. operating temperature TJ and total ground current IGND, see
Maximum Ratings). In case of parallel connection of channels with or w/o PM-bit set, the defined maximum
clamping energy must not be exceeded.
All stages are switched on and off simultaneously. The µC has to ensure that the stages which are connected in
parallel have always the same state (on or off). The PM-bit should be set according to the parallel connected power
stages in order to achieve the best possible performance.
The PM-bit is set to its default value in case of a Reset event (Reset pin Low or at Digital Supply undervoltage),
that means the improved Parallel Mode is no longer active. In the event of reset the channels will be switched off
causing the clamping energy to be dissipated with low performance of the current sharing as without PM-bit set,
for more details please refer to the Application Note Switching Inductive Loads - TLE8110 addendum.
The performance during parallel connection of channels is specified by design and not subject to the production
test. All channels at the same junction temperature level.
ON-Resistance
The typical ON-Resistance RDSsum(typ) of parallel connected channels is given by:
(2)
Ti mi ng_ Power _ Outx _res1 .vsd
t
t
V
IN x
V
OUTx
V
IN h
V
IN h
V
BATT
t
dON
t
dOFF
80%
20%
RDSsum typ() 1
RDSon n typ(),
-----------------------------1
RDSon n 1typ()+,
------------------------------------
+1–
=
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TLE 8110 EE
Smart Multichannel Switch
Power Outputs
Data Sheet 27 Rev. 1.3.1, 2011-05-26
Table 2 Performance1)2)3)4) in case of Parallel Connection of Channels: related PM-Bit set
1) The performance during parallel connection of channels is specified by design and not subject to the production test.
2) Homogenous power distribution over all channels (all power stages equally heated), dependent on cooling set-up.
3) This lifetime statement is an anticipation based on an extrapolation of Infineon's qualification test results. The actual lifetime
of a component depends on its form of application and type of use etc. and may deviate from such statement. The lifetime
statement shall in no event extend the agreed warranty period.
4) Triangular Pulse Shape (inductance discharge): ID(t) = ID(0)·(1 - t / tpulse); 0 < t < tpulse.
Pos. Parameter Symbol Channels in Parallel Unit Conditions
2x 3x 4x
Channel Group 1-4
7.4.1 Maximum overall current before
reaching lower limit threshold
IDsum(low) 5.1 7.6 10.1 A 1)
7.4.2 Maximum overall Repetitive
Clamping Energy
EARsum 37--mJID=1.0A
109 cycles
17 38 69 mJ ID=1.75A
109 cycles
- 2342mJ
ID=2.5A
109 cycles
--33mJ
ID=3.0A
109 cycles
Channel Group 5-6
7.4.3 Maximum overall current before
reaching lower limit threshold
IDsum(low) 7.2--A
7.4.4 Maximum overall Repetitive
Clamping Energy
EARsum 43--mJID=1.3A
109 cycles
21--mJ
ID=2.2A
109 cycles
Channel Group 7-10
7.4.5 Maximum overall current before
reaching lower limit threshold
IDsum(low) 3.3 5.0 6.6 A
7.4.6 Maximum overall Repetitive
Clamping Energy
EARsum 15--mJID=0.7A
109 cycles
6 1530mJ
ID=1.2A
109 cycles
-918mJ
ID=1.6A
109 cycles
--11mJ
ID=2.1A
109 cycles
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Data Sheet 28 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Power Outputs
Table 3 Performance1)2)3)4) in case of Parallel Connection of Channels: related PM-Bit NOT set
1) The performance during parallel connection of channels is specified by design and not subject to the production test.
2) Homogenous power distribution over all channels (all power stages equally heated), dependent on cooling set-up.
3) This lifetime statement is an anticipation based on an extrapolation of Infineon's qualification test results. The actual lifetime
of a component depends on its form of application and type of use etc. and may deviate from such statement. The lifetime
statement shall in no event extend the agreed warranty period.
4) Triangular Pulse Shape (inductance discharge): ID(t) = ID(0)·(1 - t / tpulse); 0 < t < tpulse.
Pos. Parameter Symbol Channels in Parallel Unit Conditions
2x 3x 4x
Channel Group 1-4
7.4.1 Maximum overall current before
reaching lower limit threshold
IDsum(low) 5.1 7.6 10.1 A 1)
7.4.2 Maximum overall Repetitive
Clamping Energy
EARsum 18--mJID=1.0A
109 cycles
8 1319mJ
ID=1.75A
109 cycles
-811mJ
ID=2.5A
109 cycles
--9mJ
ID=3.0A
109 cycles
Channel Group 5-6
7.4.3 Maximum overall current before
reaching lower limit threshold
IDsum(low) 7.2--A
7.4.4 Maximum overall Repetitive
Clamping Energy
EARsum 22--mJID=1.3A
109 cycles
11--mJ
ID=2.2A
109 cycles
Channel Group 7-10
7.4.5 Maximum overall current before
reaching lower limit threshold
IDsum(low) 3.3 5.0 6.6 A
7.4.6 Maximum overall Repetitive
Clamping Energy
EARsum 7--mJID=0.7A
109 cycles
347mJ
ID=1.2A
109 cycles
- 34mJ
ID=1.6A
109 cycles
--3mJ
ID=2.1A
109 cycles
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TLE 8110 EE
Smart Multichannel Switch
Diagnosis
Data Sheet 29 Rev. 1.3.1, 2011-05-26
8 Diagnosis
8.1 Diagnosis Description
The TLE8110EE provides diagnosis information about the device and about the load. Following diagnosis flags
have been implemented for each channel:
Updating of the Diagnosis is based on a filter-dependent standard delay time (td) of 220µs max. This value is set
as a default. Refer to Figure 18 for details.
If SCG or OL condition is asserted and before the Diagnosis Delay Time (td) is elapsed a condition change occurs,
OL-to-SCG or SCG-to-OL, filter timer is not reset and latest condition before td expiration will be stored into the
diagnosis register.
• Application Hint: It is recommended to avoid OFF periods of the channel shorter than td(max) (220µs) in order
to ensure the filter time is expired and the correct diagnosis information is stored.
• Application Hint: In specific application cases - such as driving Uni-Polar Stepper Motor - it might be possible,
that reverse currents flow for a short time, which possibly can disturb the diagnosis circuit at neighboring
channels and cause wrong diagnosis results of those channels. To reduce the possibility, that this effect
appears in a certain timing range, the filter time of Channels 7 to 10 can be extended to typ. 2.5ms or typ. 5ms
by setting the “Diagnosis Blind Time” - Bits (DBTx). If Channels 7 to 10 are used for driving loads causing
reverse currents, they influence each other and additionally might affect Channels 5 and 6 . It is recommended
to use the channels 7 + 8 and 9 + 10 as pairs for anti-parallel control signals, such as for the stepper motors.
For logic setting details, see chapter “Control of the Device”.
Diagnosis1)
1) No priority scheme is implemented for the diagnosis detection, any new diagnosis entry will override the previous one
Symbol DRn[1:0]x2)
2) Diagnosis Register (A/B banks) bit configuration, see Chapter 12.3.2.1
Device reaction Confirmation
Procedure3)
3) For some diagnosis a confirmation procedure is required for a safe operation of the device, refer to Figure 17
Short to Ground SCG 00B--
No Fault OK 11B--
Open Load OL 01B-Chapter 8.1.1
Overcurrent / Overtemperature OCT 10BSwitch-off of related channel Chapter 8.1.2
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Data Sheet 30 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Diagnosis
8.1.1 Open Load diagnosis
If an OL is read out of the Diagnosis Register, the following procedure is required in order to confirm the channel
status and ensure a safe operation of the device:
After reading the OL [01B] in the diagnosis register (Chapter 12.3.2)
1. Switch-OFF for t ≥ td(max) the related channel (via serial or direct control, see Chapter 12.3.3 and
Chapter 12.3.4)
2. Read again the diagnosis register
a) If OL is confirmed Then take actions according to system implementation
3. Continue normal operation
Refer to Figure 17 for the procedure flow-chart.
8.1.2 Overcurrent / Overtemperature diagnosis
After an OCT assertion the related channel is switched OFF for safety reasons. If an OCT is read out of the
Diagnosis Register, the following procedure is required in order to confirm the channel status and ensure a safe
operation of the device:
After reading the OCT [10B] in the diagnosis register (Chapter 12.3.2)
1. Set related bit DEVS.DCCx = 0 to disable OFF-diagnosis, see Chapter 12.3.6
2. Clear the Diagnosis issuing a DCC.DRxCL command, see Chapter 12.3.2
3. Switch-ON for t ≥ tOFFcl_l(max) the related channel
4. Read again the diagnosis register
a) If OCT is confirmed Then take actions according to system implementation
5. Set related bit DEVS.DCCx = 1 to enable OFF-diagnosis
6. Continue normal operation
Refer to Figure 17 for the procedure flow-chart.
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TLE 8110 EE
Smart Multichannel Switch
Diagnosis
Data Sheet 31 Rev. 1.3.1, 2011-05-26
Figure 17 Diagnosis Confirmation procedure
Figure 18 Block Diagram of Diagnosis
Diagnosi s C onfir m ati on
OK
?
SCG
?take SCG action
yes
no
yes
no
OL
?
yes
no
OCT
?
yes
no
DEVS.DCCx=0
(disable OFF-diag)
DCC.DRxCL
(clear diagnosis)
DCC.DRx
(read Diagnosis)
DEVS.DCCx=1
(enable OFF-diag)
OCT
?
yes
no
take OCT action
take OL action
DCC.DRx
(read diagnosis)
no actions
wait
t
d
(max)
with
Channel OFF
OL
?
yes
no
DCC.DRx
(read Diagnosis)
wait
t
OFFcl_l
(ma x)
with
Channel ON
OUTn
I
DSpd
Latch
V
DD
V
DSsg
Diagnosis-serial.vsd
protective functions
n
n
OR
Diagnosis
Register
MUX
00
01
10
Latch
V
DSol
gate contr ol
Latch
GND
I
DSsg
Temp.
Sensor
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Data Sheet 32 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Diagnosis
8.2 Electrical Characteristics Diagnosis
Electrical Characteristics: Diagnosis
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Open Load Diagnosis
8.2.1 Open load detection threshold
voltage
VDSol 2.00 2.60 3.20 V -
8.2.2 Output pull-down diagnosis current
per channel (low level)
IDpd 50 90 150 μAVDS = 13.5 V
8.2.3 Open Load Diagnosis Delay Time
(all channels)
td100 - 220 µs DEVS.DBT1=0
DEVS.DBT2=1
or 0
8.2.4
a)
b)
Channel 7-10:
Open Load Diagnosis Delay Time
“Diagnosis Blind Time” see chapter
“Control of the device”
Figure 19, Figure 20
td1.65 2.5 3.45 ms DEVS.DBT1=1
DEVS.DBT2=0
3.3 5 7.3 ms DEVS.DBT1=1
DEVS.DBT2=1
Short to GND Diagnosis
8.2.5 Short to ground detection threshold
voltage
VDSsg 1.00 1.50 2.00 V -
8.2.6 Output diagnosis current for short
to ground per channel (low level)
IDsg -150 -100 -50 μAVDS = 0V
8.2.7 Short to GND Diagnosis Delay
Time
td100 - 220 µs DEVS.DBT1=0
DEVS.DBT2=1
or 0
8.2.8
a)
b)
Channel 7-10:
Short to GND Diagnosis Delay
Time. “Diagnosis Blind Time” see
chapter “Control of the device”,
Figure 19, Figure 20
td1.65 2.5 3.45 ms DEVS.DBT1=1
DEVS.DBT2=0
3.3 5 7.3 ms DEVS.DBT1=1
DEVS.DBT2=1
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TLE 8110 EE
Smart Multichannel Switch
Diagnosis
Data Sheet 33 Rev. 1.3.1, 2011-05-26
Figure 19 Diagnosis Blind Time
Figure 20 Diagnosis Blind Time - Logic Flow
Channel 7 - 10
OFF
OL, SG -Diagnosis active
ON
1
Incident - e.g.
temporal „short to GND“
[SG]
1 1 1 0 01 1
Diagnosis Blind Time
[DBT]
active
Diagnosis Blind Time
[DBT]
triggered by
Diagnostic Incident Diagnostic Register Entry,
because Failure present
after ending DBT
Diagnosis Register :
11: No Error
10: Over Load
01: Open Load
00: Short to Ground
Diagnosis Blind Time [DBT] activation
DBT is triggered by Open Load [OL] or Short-to-Ground [SG] -detection during OFF-condition of CH7-10.
DBT is activated by DEVS .DBT1, DEVS.DBT2 (see „Control of the device“).
DBT.vsd
INx Signal
Output
Voltage
DBT
t
err
<
t
DBT
t
err
<
t
DBT
t
err >
t
DBT
„Blind“ window finishes as
soon as the error
disappears within the DBT
OL, SG-
Error
detected
DBT
Counter
SET 0 = t
DBT
Decrement
DBT Counter
OL, SG-
Error
present?
Counter
t > t
DBT
Yes
Reset Counter
(finish DBT-
frame)
No
OL, SG-
Error
present?
YES
Channel
OFF
YES
Failure detected
=> Register Entry
Yes
DBT_Flow. vsd
No
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Data Sheet 34 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Parallel Inputs
9 Parallel Inputs
9.1 Description Parallel Inputs
There are 10 input pins available are on TLE8110EE to control the output stages.
Each input signal controls the output stages of its assigned channel. For example, IN1 controls OUT1, IN2 controls
OUT2, etc.
A “Low”-Signal at INx switches the related Output Channel off. The zener diode protects the input circuit against
ESD pulses.
For details about the Boolean operation, refer to the chapter “Control of the device”, for details about timing refer
to Figure 12.
9.2 Electrical Characteristics Parallel Inputs
Electrical Characteristics: Parallel Inputs
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Parallel Inputs
9.2.1 Low Level of parallel Input pin VINxl -0.3 - VCC*
0.2
V-
9.2.2 High Level of Parallel Input pin VINxh VCC*
0.4
-V
CC V-
9.2.3 Parallel Input Pin Switching
Hysteresis
VINxhy 15 60 300 mV 1)
1) Parameter not subject to production test. Specified by design.
9.2.4 a)
.........b)
Input Pin pull-down Current IINxh 20 40 85 µA VINx=5V
IINxl 2.4--µAV
INx=0.6V1)
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TLE 8110 EE
Smart Multichannel Switch
Protection Functions
Data Sheet 35 Rev. 1.3.1, 2011-05-26
10 Protection Functions
The device provides embedded protective functions. Integrated protection functions are designed to prevent IC
destruction under fault conditions described in this Document. Fault conditions are considered “outside” the
normal operating range. Protection functions are not designed for continuous repetitive operation.
There is an over load and over temperature protection implemented in the TLE8110EE.
If a protection function becomes active during the write cycle of Diagnosis Information into the Diagnosis Register,
the information is latched and stored into the diagnosis register after the write process.
In order to achieve a maximum protection, the affected channel with over current or over temperature (OCT) is
switched and latched OFF, channel can be turned ON again after the diagnosis register is cleared
(Chapter 12.3.2) or if a different new diagnosis overrides the OCT.
For the failure condition of Reverse Currents, the device contains a “Reverse Current Protection Comparator”
[RCP]. This RCP can optionally be activated by setting the DEVS.RCP Bit.
In case the comparator is activated, it detects a reverse current and switches ON the related output channel. The
channel is kept ON up to a reverse current channel dependent threshold IRCP_off. This threshold is defined by
regulators target value to keep the output voltage at >/~-0.3V. If the current exceeds a defined value, the
comparator switches OFF and other protection functions are protecting the circuit against reverse current. That
means that at higher currents / or in case RCP is de-activated / not activated, the reverse current is flowing through
the body diode of the DMOS. In that case, the voltage drops to typically -0.6V according the voltage of the body
diode. In case the comparator threshold has been exceeded and the RCP has been switched OFF, the functions
remains OFF until the reverse current arrives back to zero reverse current. Only then, the comparator can be
activated again after a delay time tRCP_on_delay.
This function reduces the un-wanted influence of a reverse current to the analogue part of the circuit (such as the
diagnosis). For more details about the functionality, see Figure 23 and Figure 24 and concerning the settings and
the related registers, refer to Chapter “Control of the Device”.
Figure 21 Block Diagram Protection Functions
Block_diag_Protection.vsd
temperature
sensor
short circuit
detection
OUTx
gate
control
Serial
contr ol
T
Logic
Ctrl.
Ref.
-300mV
RCP
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Data Sheet 36 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Protection Functions
Figure 22 Overload shutdown thresholds and delay times
Over l oad shutdown thr esholds and delay tim es
t
I
DSD(low)
I
DSD(high)
t
OFFcl _l
t
OFFcl_h
I
DS
no switch-off with
I
<
I
DSD ( lo w)
switch-off after
t
OFFcl_l
(long) with
I
>
I
DSD(low)
immediate switch-off if
I
=
I
DSD(high)
after
t
OFFcl_h
switch-off after
t
OFFcl_h
(short) with
I
>
I
DSD (hi gh )
switch-off after
t
OFFcl_l
(long)
if
I
falls below
I
DSD ( hi gh)
before
t
OFFcl_h
Filter timer is started at
I
DSD(low)
threshold and stopped:
•at
t
=
t
OFFcl_h
if at
t
=
t
OFFcl _h
I
>
I
DSD(high)
•at
t
=
t
OFFcl_l
if
I
DSD ( lo w)
<
I
<
I
DSD(high)
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TLE 8110 EE
Smart Multichannel Switch
Protection Functions
Data Sheet 37 Rev. 1.3.1, 2011-05-26
10.1 Electrical Characteristics Overload Protection Function
Electrical Characteristics: Overload Protection Function
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Over Current Protection
10.1.1 Output Current Shut-down
Threshold Low (Channel 1 to 4)
IDSD(low) 2.6 3.8 5 A -
10.1.2 Output Current Shut-down
Threshold Low (Channel 5 to 6)
IDSD(low) 3.70 4.85 6.00 A -
10.1.3 Output Current Shut-down
Threshold Low (Channel 7 to 10)
IDSD(low) 1.7 2.3 2.9 A -
10.1.4 Output Current Shut-down
Threshold High (Channel 1 to 4)
IDSD(high) - 1.5 *
IDSD
(low)
-A
1)
10.1.5 Output Current Shut-down
Threshold High (Channel 5 to 6)
IDSD(high) - 1.5 *
IDSD
(low)
-A
1)
10.1.6 Output Current Shut-down
Threshold High (Channel 7 to 10)
IDSD(high) - 1.5 *
IDSD
(low)
-A
1)
10.1.7 Short Overload shutdown Delay
Time (all Channels)
tOFFcl_h 5 21 40 µs valid for “Output
Current Threshold
High” 1)
10.1.8 Long Overload shutdown Delay
Time (all Channels)
tOFFcl_l 10 40 70 µs valid for “Output
Current Threshold
Low”
Over Temperature Protection
10.1.9 Thermal Shut Down Temperature TjSD 175 190 205 °C 1)
10.1.10 Thermal Shut Down Hysteresis TjSDh 10 - 20 K 1)
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Data Sheet 38 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Protection Functions
Reverse Current Protection
10.1.11 Reverse Current Comparator
Switch-off Current level CH 1 - 4
IRCP_off - -0.9 - A DEVS.RCP = 11)
Tj = 25°C
10.1.12 Reverse Current Comparator
Switch-off Current level CH 5 - 6
IRCP_off - -0.6 - A DEVS.RCP = 11)
Tj = 25°C
10.1.13 Reverse Current Comparator
Switch-off Current level CH 7 - 10
IRCP_off - -0.45 - A DEVS.RCP = 11)
Tj = 25°C
10.1.14 Reverse Current Comparator
switch on delay time
tRCP_on_
delay
- 24 - µs DEVS.RCP = 11)
Tj = 25°C
1) Parameter not subject to production test. Specified by design.
Electrical Characteristics: Overload Protection Function (cont’d)
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
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TLE 8110 EE
Smart Multichannel Switch
Protection Functions
Data Sheet 39 Rev. 1.3.1, 2011-05-26
Figure 23 Reverse Current Protection Comparator 6
Reverse Current
I
D
Leakage
(neighbour
channel)
RCP not active
RCP active
I
RCP_off
RCP.vsd
I
D
t
t
Reverse Current
Comparator
Switch-off
Current level
I
RCP_off
Reverse
Current
Comparator
Switch-off
Current level
Maximum
Rating
-
I
DSD (low)
V
D
V
Batt
~ - 300mV
RCP active:
Regulation to
VD ~ - 300mV;
-ID through DMOS
RCP not active:
ID through Body
Diode of DMOS
0
0
t
RCP_on_delay
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Data Sheet 40 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Protection Functions
Figure 24 Reverse Current Protection Comparator (typical behavior vs junction temperature)
Tj / °C
I
RCP_off
/A
-40 -20 0 20 40 60 80 100 120 140
-0.1
-0.3
-0.5
-0.7
-0.9
-1.1
-1.3
-1.5
CH1-6
CH7-10
IRCP_OFF_TC_12_ch.vsd
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TLE 8110 EE
Smart Multichannel Switch
16 bit SPI Interface
Data Sheet 41 Rev. 1.3.1, 2011-05-26
11 16 bit SPI Interface
11.1 Description 16 bit SPI Interface
The diagnosis and control interface is based on a serial peripheral interface (SPI).
The SPI is a full duplex synchronous serial slave interface, which uses four lines: S_SO, S_SI, S_CLK and S_CS.
Data is transferred by the lines S_SI and S_SO at the data rate given by S_CLK. The falling edge of S_CS
indicates the beginning of a data access. Data is sampled in on line S_SI at the falling edge of S_CLK and shifted
out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of S_CS. A modulo
8 counter ensures that data is taken only, when a multiple of 8 bit has been transferred. If in one transfer cycle not
a multiple of 8 bits have been counted, the data frame is ignored. The interface provides daisy chain capability.
Figure 25 16 bit SPI Interface
The SPI protocol is described in Chapter “Control of the device”. Concerning Reset of the SPI, please refer to the
chapter “Reset”
11.2 Timing Diagrams
Figure 26 Data Transfer in Daisy Chain Configuration
14 13 12 11
14 13 12 11MSB
MSB LSB6 5 4 3 2 1
LSB6 5 4 3 2 1
10 9 8
10 9 8
7
7
S_SO
S_SI
S_CS
S_CLK
time
SPI.vsd
S_CS
S_CLK
S_SI
t
CS lead
t
CSt d
t
CSlag
t
SCLKh
t
SCLKl
t
SCLKp
t
SIsu
t
SIh
S_SO
t
SOdis
0.7V
dd
0.2V
dd
0.7V
dd
0.2V
dd
0.7V
dd
0.2V
dd
0.7V
dd
0.2V
dd
t
SOv
t
SO(en)
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Data Sheet 42 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
16 bit SPI Interface
11.3 Electrical Characteristics 16 bit SPI Interface
Electrical Characteristics: 16 bit SPI Interface
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Input Characteristics (CS, SCLK, SI)
11.3.1 L level of pin
S_CS
S_CLK
S_SI
VS_CSl
VS_CLKl
VS_SIl
-0.3 - VCC*
0.2
V-
11.3.2 H level of pin
S_CS
S_CLK
S_SI
VS_CSh
VS_CLKh
VS_SIh
VCC*
0.4
-V
CC V-
11.3.3 Hysteresis Input Pins VS_CShy
VS_CLKhy
VS_SIhy
20 100 300 mV -
11.3.4
a)
b)
Input Pin pull-down Current
S_CLK
S_SI
IS_CLKh
IS_SIh
20 40 85 µA VIN=5V
IS_CLKl
IS_SIl
2.4--µAV
IN=0.6V1)
11.3.5
a)
b)
Input Pin pull-up Current
S_CS
IS_CSh -4 - - μAVS_CS = 2 V,
VCC=3.3V
IS_CSl -20 -40 -85 μAVS_CS = 0 V,
VCC=5V
Output Characteristics (SO)
11.3.6 L level output voltage VS_SOl 0-0.4VIS_SO = -2 mA
11.3.7 H level output voltage VS_SOh Vcc -
0.4 V
-Vcc IS_SO = 1.5 mA
11.3.8 Output tristate leakage current IS_SOoff -10 - 10 μAVS_SO = Vcc
Timings
11.3.9 Serial clock frequency fS_CLK 0-5MHz-CL = 50 pF 1)
11.3.10 Serial clock period tS_CLK(P) 200 - - ns 1)
11.3.11 Serial clock high time tSCLK(H) 50 - - ns 1)
11.3.12 Serial clock low time tSCLK(L) 50 - - ns 1)
11.3.13 Enable lead time (falling CS to rising
SCLK)
tCS(lead) 250 - - ns 1)
11.3.14 Enable lag time (falling SCLK to rising
CS)
tCS(lag) 250 - - ns 1)
11.3.15 Transfer delay time (rising CS to falling
CS)
tCS(td) 250 - - ns 1)
11.3.16 Data setup time (required time SI to
falling SCLK)
tSI(su) 20 - - ns 1)
11.3.17 Data hold time (falling SCLK to SI) tSI(h) 20 - - ns 1)
11.3.18 Output enable time (falling CS to SO
valid)
tSO(en) - - 200 ns CL = 50 pF 1)
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TLE 8110 EE
Smart Multichannel Switch
16 bit SPI Interface
Data Sheet 43 Rev. 1.3.1, 2011-05-26
11.3.19 Output disable time (rising CS to SO tri-
state)
tSO(dis) - - 200 ns CL = 50 pF 1)
11.3.20 Output data valid time with capacitive
load
tSO(v) - - 100 ns CL = 50 pF 1)
11.3.21 Diagnosis Clear-to-Read Idle Time tDidle 16 - - µs 1)
11.3.22 Diagnosis Overcurrent-to-Clear Idle
Time
tOCidle 12 - - µs 1)
1) Not subject to production test, specified by design.
Electrical Characteristics: 16 bit SPI Interface (cont’d)
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
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Data Sheet 44 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Control of the device
12 Control of the device
This chapter describes the SPI-Interface signals, the protocol, registers and commands. Reading this chapter
allows the Software Engineer to control the device. The chapter contains also some information about
communication safety features of the protocol.
12.1 Internal Clock
The device contains an internal clock oscillator.
12.2 SPI Interface. Signals and Protocol
12.2.1 Description 16 bit SPI Interface Signals
S_CS - Chip Select:
The system micro controller selects the TLE8110EE by means of the S_CS pin. Whenever the pin is in low state,
data transfer can take place. When S_CS is in high state, any signals at the S_CLK and S_SI pins are ignored
and S_SO is forced into a high impedance state.
S_CS High to Low transition:
• The information to be transferred loaded into the shift register (16-bit Protocol).
•
S_CS Low to High transition:
• Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3, …) of eight
S_CLK signals have been detected. (See Modulo-8 Counter: Chapter 12.2.4.2)
Electrical Characteristics: Internal Clock
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Parallel Inputs
12.1.1 internal clock oscillator frequency fint_osc - 500 - kHz 1)
1) Parameter not subject to production test. Specified by design.
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Data Sheet 45 Rev. 1.3.1, 2011-05-26
S_CLK - Serial Clock:
This input pin clocks the internal shift register. The serial input (S_SI) transfers data is shifted into the register on
the falling edge of S_CLK while the serial output (S_SO) shifts the information out on the rising edge of the serial
clock. It is essential that the S_CLK pin is in low state whenever chip select CS makes any transition.
S_SI - Serial Input:
Serial input data bits are shifted in at this pin, the most significant bit first. The bit at the S_SI Pin is read on the
falling edge of S_CLK.
S_SO Serial Output:
Data is shifted out serially at this pin, the most significant bit first. S_SO is in high impedance state until the S_CS
pin goes to low state.The next bits will appear at the S_SO pin following the rising edge of S_CLK.
12.2.2 Daisy Chain
The SPI-Interface of TLE8110EE provides daisy chain capability, see Chapter 12.2.3.4 for more details. In this
configuration several devices are activated by the same S_CS signal. The S_SI line of one device is connected
with the S_SO line of another device (see Figure 27), which builds a chain. The ends of the chain are connected
with the output and input of the master device, S_SO and S_SI respectively. The master device provides the
master clock CLK, which is connected to the S_CLK line of each device in the chain. By each clock edge on
S_CLK, one bit is shifted into the S_SI. The bit shifted out can be seen at SO. After 16 S_CLK cycles, the data
transfer for one device has been finished. In single chip configuration, the S_CS line must go high to make the
device accept the transferred data. In daisy chain configuration the data shifted out at device 1 has been shifted
in to device 2. Example: When using three devices in daisy chain, three times 16 bits have to be shifted through
the devices. After that, the S_CS line must go high (see Figure 27).
Figure 27 Principle example for Data Transfer in Daisy Chain Configuration
Note: Due to the integrated modulo 8 counter, 8 bit and 16 bit devices can be used in one daisy chain.
12.2.3 SPI Protocol
The device contains two protocol styles which are applied dependent of the used commands. There is the
standard 16-bit protocol and the 2x8-bit protocol. Both protocols can appear also be mixed.
12.2.3.1 16-bit protocol
Each Cycle where a serial data or command frame is sent to the S_SI of the SPI interface, a data frame is returned
at the same time by the S_SO The content of the S_SO frame is dependent on the previous command which has
been sent to S_SI. Read Command (R/W = R) returns one cycle later the content of the addresses register. (see
Figure 28 ).
SI
SO
CS
CLK
SI device 3 SI device 2 SI device 1
SO device 3 SO device 2 SO device 1
time
SPI_DasyChain2.emf
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Data Sheet 46 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Control of the device
Figure 28 16-bit protocol
S_SI
Serial Input Reset Value: N.A.
1514131211109876543210
W/R ADDR DATA / CMD
Field Bits Description
W/R 15 W/R - Write / Read
0 Write register: The register content of the addressed register will be updated after
CS low →high transition. After sending a WRITE command, the device returns
data according the addressed register
1 Read register: The register content of the addressed register will be sent in the
next frame.
ADDR 14:12 ADDR - Address
Pointer to register for read and write command
DATA/CMD 11:0 DATA_CMD - Data / Command
Data written to or read from register selected by address ADDR
S_SO
Serial Output Reset Value: xxxx xxxx xxxx xxxxB
1)
1) after reset is send a Short Diagnosis and Device Status CMD_CSDS, see Chapter 12.3.1.2.
CS1514131211109876543210
PAR ADDR DATA
Field Bits Description
PAR 15 PAR - Parity Bit
1: odd number of '1' in data and address field
0: even number of '1' in data and address field
ADDR 14:12 Address
Address which has bin addressed
DATA 11:0 Data
Content of Address or feedback Data
RADR / DATA WADR / DATA ADR / DATAR
dept. of
previous R/W Register Short Diagnosis*
S_CS
S_SI
S_SO
SPI_Protocol_Normal_Mode.vsd
* dependent on ADR; In case CMD or DCC is addressed, related content.
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TLE 8110 EE
Smart Multichannel Switch
Control of the device
Data Sheet 47 Rev. 1.3.1, 2011-05-26
Note: Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second frame the output at
SPI signal SO will contain the requested information. A new command can be executed in the second frame.
12.2.3.2 2x8-bit protocol
Each Cycle where a serial data or command frame is sent to the S_SI of the SPI interface, a data frame is returned
at the same time by the S_SO. The content of the S_SO frame is dependent of the previous command which has
been sent to S_SI and the content of the actual content of S_SI: The first Upper Byte send to S_SI controls the
content of the Lower Byte actual returned by S_SO. The Lower Byte send to S_SI controls the Lower Byte in S_SO
of the next frame. (see Figure 29 ).
Figure 29 2x8-bit protocol
DMSx
S_CS
S_SI
S_SO
SPI_Protocol_2x8bit.vsd
OPSx
Upper
Byte DO
Upper
Byte
Lower
Byte
OPF Lower
Byte
Upper
Byte
Lower
Byte
Upper
Byte
Lower
Byte
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Data Sheet 48 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Control of the device
Note: Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second frame the output at
SPI signal SO will contain the requested information. A new command can be executed in the second frame.
12.2.3.3 16- and 2x8-bit protocol mixed.
The 16-bit and 2x8-bit protocols are mixed according the used commands (see Chapter 12.3.1). Special care
should be taken, changing from the 16-bit protocol to the 2x8-bit protocol. In this case, it is important to send a
NOP command to S_SI. Otherwise, by sending instead a Command, a collision between the S_SO data in the
following frame and the Lower Byte of the 2x8-bit protocol will happen (see Chapter 12.2.3.2).
S_SI
Serial Input Reset Value: N.A.
1514131211109876543210
Upper Byte Lower Byte
Field Bits Description
Upper Byte 15:8 Upper Byte
contains the command, which is performed after sending 8 bit to S_SI. The action out of
this command is affecting the Lower Byte of S_SO of the actual communication
frame.
Lower Byte 7:0 Lower Byte
contains the command and data, which is performed at the end of the actual
communication frame. The action out of this command is affection the Upper Byte
of S_SO of next communication frame.
S_SO
Serial Output Reset Value: xxxx xxxx xxxx xxxxB
1)
1) after reset is send a Short Diagnosis and Device Status CMD_CSDS, see Chapter 12.3.1.2.
CS1514131211109876543210
Upper Byte Lower Byte
Field Bits Description
Upper Byte 15:8 Upper Byte
contains the data according the command and data in the Lower Byte of the previous
communication Frame.
Lower Byte 7:0 Lower Byte
contains the data according the command in the Upper Byte of the actual communication
frame
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TLE 8110 EE
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Data Sheet 49 Rev. 1.3.1, 2011-05-26
Figure 30 16-bit protocol
12.2.3.4 Daisy-Chain and 2x8-bit protocol
When using the TLE8110EE in a daisy-chain connection with other devices (TLE8110EE and non) special care
has to be taken to avoid interference of 2x8-bit protocol with normal communication. Few simplified rules must be
followed for a safe SPI communication in daisy-chain environment:
1. All TLE8110EE devices have to be routed at the beginning of the chain, other devices than TLE8110EE
afterward
2. compactCONTROL commands (2x8-bit protocol) must not be addressed to TLE8110EE
3. The SPI frame of the daisy-chain must be extended of additional 8-bit (all zeros 00H) at beginning of the frame
4. When a Read/Clear Diagnosis Register A command (DRA, DRACL) is addressed to TLE8110EE, a NOP
command must be sent to the next TLE8110EE on the chain
5. When a Read/Clear Diagnosis Register A command (DRA, DRACL) is addressed to TLE8110EE, response of
the next device on the chain must be ignored in the next SPI cycle
Details in Figure 31 and Figure 32.
Upper
Byte
S_CS
S_SI
S_SO
SPI_Protocol_16_2x8bit_mixed.vsd
Lower
Byte
Upper
Byte
Lower
Byte
CMD
Upper
Byte 0
CMD
Data
NOP
Data
Upper
Byte
Lower
Byte
0Lower
Byte
Upper
Byte
Lower
Byte
Upper
Byte
Lower
Byte
Protocol Change from 2x8-bit to 16-bit
Protocol Change from 16-bit to 2x8-bit
Critical Protocol Change from 16-bit to 2x8-bit
S_CS
S_SI
S_SO
CMD
Data
Upper
Byte
Lower
Byte
Data... Lower
Byte
Upper
Byte
Lower
Byte
Upper
Byte
Lower
Byte
S_CS
S_SI
S_SO
collission
2x8-bit protocol is
dominant
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Data Sheet 50 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Control of the device
Figure 31 Daisy-Chain and 2x8-bit protocol
Daisy-C hain and 2x8 -bit pr otoc ol
from dev.n from dev.1
to dev.n to dev.1
S_CS
S_SI
S_SO
SPI daisy-chain word
first 8-bit that could interfere with
compacCONTROL of device 1
lower-byte from dev.n affected by the
reaction of dev.1 to compactCONTROL
t
from dev.n from dev.1
to dev.n to dev.1
S_CS
S_SI
S_SO
SPI daisy-chain word
t
00
H
all zeros 8-bit extension
last 8-bit to be ignored
Safe Communication with first all zeros 8-bit extension
Critical Communication with first 8-bit interpreted as compactCONTROL (2x8-bit protocol)
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Data Sheet 51 Rev. 1.3.1, 2011-05-26
Figure 32 DRA, DRACL to dev.n and NOP command to dev.n+1
DRA, DRACL to dev .n and NOP command to dev .n+1
from dev.n
to dev.n+1
S_CS
S_SI
S_SO
SPI daisy-chain word
t
Safe Communication with NOP command send to dev .n+1 and ignored response
Critical Communication with dev.n+1 response altered by dev .n response to previous DRA /DRACL
to dev.n
from dev.n+1
DRA/DRACLNOP
from dev.n
to dev.n+1 to dev.n
from dev.n+1
SPI daisy-chain word
no response expected
ignored
response to DRA-/CL
from dev.n
to dev.n+1
S_CS
S_SI
S_SO
SPI daisy-chain word
t
to dev.n
from dev.n+1
DRA/DRACLx-command
from dev.n
to dev.n+1 to dev.n
from dev.n+1
SPI daisy-chain word
response to x-command
8-bit altered by dev.n response to DRA-/CL
response to DRA-/CL
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Data Sheet 52 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Control of the device
12.2.4 safeCOMMUNICATION
The devise contains some safety features, which are improving the protecting of the application against mal-
function in case of disturbance of the communication between the Micro Controller and the Device:
12.2.4.1 Encoding of the commands
The Commands are encoded. In case other bit-patterns, then the defined once are received, the commands are
ignored and the communication error can be read out with the command CMD_RSDS (seeChapter 12.3.1.2).
12.2.4.2 Modulo-8 Counter
The modulo is the integral remainder in integral division. In data communications, a modulo based approach is
used to ensure that user information in SPI protocols is in the correct order. The device has a receiver-side
counter, and a defined counter size. The modulo counter specifies the number of subsequent numbers available.
In case of TLE8110EE Modulo 8 counter specifies 8 serial numbers. The modulo 8 counter ensures that data is
taken only, when a multiple of 8 bit has been transferred. If in one transfer cycle not a multiple of 8 bits have been
counted, the data frame is ignored and a Communication Error is indicated in the CMD_RSDS - Feedback
(seeChapter 12.3.1.2).
12.3 Register and Command - Overview
This Chapter describes the Registers and Commands. The commands allow to carry through some actions, such
as reading out or clearing the diagnosis or reading out the Input Pins.
Specially highlighted here should be the encoded CMD_DMSx/OPSx commands - compactCONTROL -, a highly
efficient command-set to set a part of the output pins and read out the diagnosis at the same time. Included in this
command set is the possibility to check, if the communication works well as also the possibility to read-out some
of the parallel Input Pins INx. Using this compact command set can reduce the workload of the micro-controller
during run-time significantly.
CMD_RSD is preformed and short diagnostics [SD] is returned after each Write Cycle to any of the writable
registers.
After start-up of the device, the registers are loaded with the default settings as described below in the register
descriptions. The Registers are cleared and set back to the default values, when a low signal is applied to the pin
RST or an under-voltage condition appears at the supply pin VCC what causes an under-voltage reset. If a low
signal at pin EN is applied or an under-voltage condition appears at pin VDD, the Registers are not cleared.
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Data Sheet 53 Rev. 1.3.1, 2011-05-26
Table 1
Name Type Addr Short Description see:
CMD W1)
1) if a read command is send, the command is ignored and S_SO returns a frame with ’0’.
000BCommands Chapter 12.3.1
DCC W1) 001BDiagnosis Registers and Compact Control Chapter 12.3.2
OUTx W/R 010BOutput Control Register CHx. Chapter 12.3.3
DEVS W/R 011BDevice Settings Chapter 12.3.6
MSCS W/R 100B reserved
ISAx W/R 101BInput or Serial Mode Register CHx Bank A Chapter 12.3.4
ISBx W/R 110BInput or Serial Mode Register CHx Bank B Chapter 12.3.4
PMx W/R 111BParallel Mode Control of CHx with CHy Chapter 12.3.5
Table 2
Register Overview
Name Addr11109876543210def.
1)
1) Default Values after Reset
CMD W2)
2) if a read command is send, the command is ignored and S_SO returns a frame with ’0’.
000B0111 Command ---
DCC W2) 001BCommand ---
OUTx W/R 010B11OUT
10
OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1
C00h
DEVS W/R 011BRCP DBT2 DBT1 0 0 0 0 0 0 DCC
10
DCC 9 DCC
18 007h
MSCS W/R 100Breserved 000h
ISAx W/R 101BIS6 IS5 IS4 IS3 IS2 IS1 AAAh
ISBx W/R 110B 0 0 0 0 IS10 IS9 IS8 IS7 0AAh
PMx W/R 111B0000PM91
0
PM89 PM78 PM56 0 PM34 PM23 PM12 000h
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Data Sheet 54 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Control of the device
Figure 33 Logic Output Control Block Diagram TLE8110EE
OUT1
OUT2
OUT3
Diagn. current off = 0
Diagn. Current on = 1
DC18[0]:
IN3
PM12=1
PM12=0
PM23=0
OUT10
IN1 0
PM910=1
PM910=0
Logic_Output_Control_CORE10.vsd
Serial-Mode OUT1=0 = 00
AND IN/Serial-Mod0 = 11
IN-Mode = 10
Serial-Mode OUT1=1 = 01
IS1[1:0]:
IN4
OUT6
OUT7
OUT8
PM78=0
PM78=1
PM23=1
PM56=0
PM56=1
IS2[1:0]
IS1[1:0]
CH5
CH9
IN1
OUT1
IN2
OUT2
11
10
0x
11
10
0x
OUT
10
11
10
0x
IS10 [1:0]
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Data Sheet 55 Rev. 1.3.1, 2011-05-26
12.3.1 CMD - Commands
By using the Address Range CMD[14:12]=’000’ commands can be send to the device. The Feedback of the
commands is provided in the next SPI SO Frame.Details about the Feedback on each command is described in
the Chapter 12.3.1.1.
It is possible to perform per each Communication Frame ONE Command out of Group-A (see following description
of the Commands) and ONE Command out of Group-B at the same time. Performing more then one Command of
one Group is not possible. For the case, this happens, the commands are ignored.
Overview Commands
CMD
Command Register Reset Value: N.A.
S_SI
SPI_Serial Input
CMD 11109876543210
RSD 011100000001
RSDS 011100000010
RPC 011100000100
RINx 011100001000
CSDS 011100010000
NOP 011100000000
Field Command Type Description
Command Bits Group-B (Bits [7:4])
All other bit combinations are not valid. Command will be ignored then.
NOP 0000 W NOP - no operation.
A frame with ’0000h’ will be returned
CMD_CSDS 0001 W CMD_CSDS - Command: Clear Short Diagnosis and Device
Status
Clear the Device Status information.
Performing this Clear Command clears the Information in the Reset
and Communication Error Information as long as the incident is not
present anymore. If the incident is still present, the related Bits remain
setted. Performing this command does NOT clear the Diagnosis
Registers. The Diagnosis Information is cleared by the Clear
Diagnosis Commands. (see Chapter 12.3.2)
SO returns a Frame with ’0000h’ after performing CMD_CSDS or in case
this command is carried out together with a command out of
Group-A, the feedback is according the Group-A command
Command Bits Group-A (Bits [3:0])
All other bit combinations are not valid. Command will be ignored then.
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Data Sheet 56 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Control of the device
12.3.1.1 CMD_RSD - Command: Return Short Diagnosis
The Command CMD_RSD offers the possibility to read out the OR-operated “short”-Diagnosis within one SO
Feedback Frame. The data to be send is latched at the end of the command frame .
Figure 34 SPI Feedback on CMD_RSD
CMD_NOP 0000 W NOP - no operation.
A frame with ’0000h’ will be returned
CMD_RINx 1000 W CMD_RINx - Command: Return Input Pin INx -Status
(Chapter 12.3.1.4)
CMD_RPC 0100 W CMD_RPC - Command: Return Pattern Check
(Chapter 12.3.1.3)
CMD_RSDS 0010 W CMD_RSDS - Command: Return Short Diagnosis and Device
Status
(Chapter 12.3.1.2)
CMD_RSD 0001 W CMD_RSD - Command: Return Short Diagnosis
(Chapter 12.3.1.1)
S_SO
SPI_Serial Output
CS1514131211109876543210
PAR 0 0 0 0 0 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1
Field Command Type Description
WCMD_RSD R/W xxxx
dept. of
previous R/W SD xxxx
S_CS
S_SI
S_SO
SPI_Protocol_CMD_RSD.vsd
CMD_RSD
R/W xxxx
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Data Sheet 57 Rev. 1.3.1, 2011-05-26
12.3.1.2 CMD_RSDS - Command: Return Short Diagnosis and Device Status
The Command CMD_RSD offers the possibility to read out the OR-operated “short”-Diagnosis and the device
Status - such as Reset-Information and Communication Error - within one SO Feedback Frame. The data to be
send is latched at the end of the command frame .
Figure 35 SPI Feedback on CMD_RSDS
Field Bits Type Description
---
SD1-10 Short Diagnosis
0 Normal Operation
1 Each SD-Bit contains the NAND-operated Diagnosis Error of each
related Channel. Details can be read in diagnosis registers
SD is returned after each Write Cycle to any of the writable registers.
WCMD_RSDS R/W xxxx
dept. of
previous R/W SDS xxxx
S_CS
S_SI
S_SO
SPI_Protocol_CMD_RSDS.vsd
CMD_RSDS
R/W xxxx
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Data Sheet 58 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Control of the device
S_SO
SPI_Serial Output
CS1514131211109876543210
PAR 0 0 0 0 0 0 0 SDS8 SDS7 SDS6 SDS5 SDS4 SDS3 SDS2 SDS1
Field Bits Type Description
-7:0-SDS - Short Diagnosis and Device Status
-0-SDS1 - Diagnosis Error in Channel 1 to 6
0 normal operation
1 diagnosis failure
-1-SDS2 - Diagnosis Error in Channel 7 to 10
0 normal operation
1 diagnosis failure
-2-SDS3 - Under Voltage on VCC (Digital Supply Voltage)
see Figure 36
-3-SDS4 - Under Voltage on VDD (Analogue Supply Voltage)
see Figure 36
-4-SDS5 - Modulo Counter Error
0 normal operation
1Previous
Modulo Counter Error
-5-SDS6 - Previous Communication Error - Encoded Command Ignored
0 normal operation
1Previous Communication Error - Encoded Command Ignored
-6-SDS7 - not used = ’0’
always ’0’
-7-SDS8 - not used = ’0’
always ’0’
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Data Sheet 59 Rev. 1.3.1, 2011-05-26
Figure 36 Behaviour of SDS3, 4
Behaviour of SDS 3 and SDS 4 in relation to RST , EN, VDD, VCC and CMD .CSDS
VCC
RST
or...
SDS3 0 1 0
CMD.CSDS
SDS3
VCC
RST
or...
SDS4 0 1 0
CMD.CSDS
SDS4
EN=1
VDD
SDS4 0 1 1 0
CMD.CSDS
VCC
RST
or...
SDS4 0 0 0
CMD.CSDS
SDS4
EN=0
VDD
SDS4 0 0 0 0
CMD.CSDSSDS4
EN=0Æ1
EN
SDS4 0 1* 0
CMD.CSDS
SDS3_4_behaviour.vsd
* During EN = 0, the device internal VDD supply is disabled in order to fulfill low
quiescent current requirements. After the transition from EN=0 to 1, the SDS4
will detect under voltage (it is set SDS4=1) until the clear command CMD.CSDS
it sent (SDS4=0).
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Data Sheet 60 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Control of the device
12.3.1.3 CMD_RPC - Command: Return Pattern Check
The Command CMD_RPC offers the possibility to get returned the previous Command to check if the
communication works well. The data to be send is latched at the end of the command frame .
Figure 37 SPI Feedback on CMD_RPC
12.3.1.4 CMD_RINx - Command: Return Input Pin (INx) -Status
The Command CMD_RINx offers the possibility to read out the actual status of the Input Pins. This command
allows to check the correct communication on the INx Pins. The data to be send is latched at the end of the
command frame .
S_SO
SPI_Serial Output
CS1514131211109876543210
PAR=
0000011100000100
Field Bits Type Description
---
CMD_RPC is returned
WCMD_RPC R/W xxxx
dept. of
previous R/W CMD_RPC xxxx
S_CS
S_SI
S_SO
SPI_Protocol_CMD_RPC.vsd
CMD_RPC
R/W xxxx
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Data Sheet 61 Rev. 1.3.1, 2011-05-26
Figure 38 SPI Feedback on CMD_RINx
S_SO
SPI_Serial Output
CS1514131211109876543210
PAR 0 0 0 0 0 IN10 IN9 IN8 IN7 IN6 IN5 IN4 IN3 IN2 IN1
Field Bits Type Description
---
INx Input Pin Status
The Status of the INx Pins is read out at the moment of CS High-to-Low
transition. Details see Figure 39.
0 INx = Low corresponding OFF
1 INx = High corresponding ON
WCMD_RINx R/W xxxx
dept. of
previous R/W INx xxxx
S_CS
S_SI
S_SO
SPI_Protocol_CMD_RINx.vsd
CMD_RINx
R/W xxxx
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Data Sheet 62 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Control of the device
Figure 39 Read-out of INx Pins
12.3.2 DCC - Diagnosis Registers and compactCONTROL
The DCC - Diagnosis and Compact Control Set allows to read out and clear the Diagnosis Registers. Additionally
this Command set offers the possibility to proceed with a compactCONTROL Mode using DMS - Diagnosis Mode
Set and OPS - Output Pin Set Commands. This compactCONTROL Mode offers the possibility to Control the
device with lowest work load on the micro controller side.
If any other pattern then the defined commands is received on S_SI, the command is ignored and rated as a
Communication Error. In this case, this incident is reported in SDS (Chapter 12.3.1.2).
If an Error in the Output Channels is detected by the diagnosis circuit, the result is latched in the diagnosis registers
related to each channel.
The Diagnosis Register is not deleted, when it is just read out. The Diagnosis Register byte can only be cleared
by using the appropriated command. In this case, the complete Register Bank is cleared.
When issuing a Diagnosis Register Clear command (DRxCL or DMSCL), the idle time tDidle needs to elapse, from
the CS low-to-high transition of the clear command, before the register content is effectively cleared (Figure 40);
this time has to be taken into account when trying to read the Diagnosis register content after a clear, see
Chapter 11.3 for tDidle definition.
After an overcurrent entry is stored in the diagnosis register (OC), the idle time tOCidle needs to elapse before a
clear command can effectively clear the entry; if trying to clear the Diagnosis register after an OCT entry is read
(Figure 40), this time has to be taken into account starting from the CS high-to-low transition of the previous read
command, see Chapter 11.3 for tOCidle definition.
IN1
IN2
INx
Control Logic
OUT1
OUT2
OUTn
Transfer on CS to
SPI-SO-Register
Latch on CS
CMD_RINx
RINx
SI
SO
INx_readout.vsd
CS
Temporal INx Register
latched by CMD_PINx and
CS High-to-Low transition
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Data Sheet 63 Rev. 1.3.1, 2011-05-26
Figure 40 Diagnosis idle times
DCC
Diagnosis Registers and Compact Control Reset Value: N.A.
S_SI
SPI_Serial Input
DCC 11109876543210
DRA 010100000000
DRB 011000000000
DRACL 000100000000
DRBCL 001000000000
DMSCL/OPSx 1 0 0 0 OPSx
DMS1/OPSx 1 0 1 1 OPSx
DMS2/OPSx 1 1 0 1 OPSx
DMS3/OPSx 1 1 1 0 OPSx
Diagnosis Idle Times
Diagnosis Clear-to-Read idle time (
t
Didle
)
S_CS
S_SI
t
Didle
t
Clear Diagnosis
DRxCL/DMSCL
Read Diagnosis
DRx
Diagnosis gets cleared
Cleared diagnosis can be read
t
>
t
Didle
Diagnosis Overcurrent -to-Clear idle time (
t
OCidle
)
S_CS
S_SI
t
OCidle
t
Read Diagnosis
DRx
Clear Diagnosis
DRxCL/DMSCL
OCT can be cleared
Effective Diagnosis Clear
t
>
t
OCidle
OCT detected
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Data Sheet 64 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Control of the device
DMSx/OPS11 DMSx 00000001
DMSx/OPS21 DMSx 00000010
DMSx/OPS31 DMSx 00000100
DMSx/OPS41 DMSx 00001000
DMSx/OPS51 DMSx 00010000
DMSx/OPS61 DMSx 00100000
DMSx/OPS71 DMSx 01000000
DMSx/OPS81 DMSx 10000000
Field Bits Type Description
DCC_DRA
11:0 W DRA - Diagnosis Register A (see Chapter 12.3.2.1)
Read out Diagnosis Register A. Return the contents in the next SPI
Frame. (see Chapter 12.3.2.2)
DCC_DRB
11:0 W DRB - Diagnosis Register B (see Chapter 12.3.2.1)
Read out Diagnosis Register B. Return the contents in the next SPI
Frame. (see Chapter 12.3.2.2)
DCC_
DRACL
11:0 W DRACL - Diagnosis Register A Clear
Clear the contents of the Diagnosis Register A. Return the content
present before the clear in the next SPI Frame. If the Diagnosis
Error Remains, the Information remains.(see Chapter 12.3.2.2)
DCC_
DRBCL
11:0 W DRBCL - Diagnosis Register B Clear
Clear the contents of the Diagnosis Register B. Return the content
present before the clear in the next SPI Frame. If the Diagnosis
Error Remains, the Information remains. (see
Chapter 12.3.2.2)
DCC_
DMSCL
11:8 W DMSCL/OPSx - Diagnosis Mode Set, Clear / Output Pins Set
On sending this command, the diagnosis registers DRA, DRB as well
as the “virtual” Diagnosis Output Registers DO[7:0] (see
Chapter 12.3.2.3) are cleared. Output Pin Settings are done
according the content of OPSx.
Returns the contents of cleared DR2 on SO in the 2nd byte of the
actual communication frame and the Output Pin Feedback in
the 1st Byte of the next frame. (see Chapter 12.3.2.3)
DCC_
DMS1
11:8 W DMS1/OPSx - Diagnosis Mode Set, Register1 / Output Pins Set
On sending this command, the diagnosis registers DR1 is selected.
Output Pin Settings are done according the content of OPSx.
Returns the contents of DR1 on SO in the 2nd byte of the actual
communication frame and the Output Pin Feedback in the 1st
Byte of the next frame. (see Chapter 12.3.2.3)
DCC_
DMS2
11:8 W DMS2/OPSx - Diagnosis Mode Set, Register2 / Output Pins Set
On sending this command, the diagnosis registers DR2 is selected.
Output Pin Settings are done according the content of OPSx.
Returns the contents of DR2 on SO in the 2nd byte of the actual
communication frame and the Output Pin Feedback in the 1st
Byte of the next frame. (see Chapter 12.3.2.3)
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Data Sheet 65 Rev. 1.3.1, 2011-05-26
12.3.2.1 DRx - Diagnosis Registers Contents
DCC_
DMS3
11:8 W DMS3/OPSx - Diagnosis Mode Set, Register3 / Output Pins Set
On sending this command, the diagnosis registers DR3 is selected.
Output Pin Settings are done according the content of OPSx.
Returns the contents of DR3 on SO in the 2nd byte of the actual
communication frame and the Output Pin Feedback in the 1st
Byte of the next frame. (see Chapter 12.3.2.3)
DCC_
DMSx/OPSx
7:0 W DMSx/OPS1 - Diagnosis Mode Set x/ Output Pin Set Command 1
On sending this command, the diagnosis register is selected
according DMSx. The Output Pins of Channel 7-10 are set
according the following definitions. The OPSx are commands,
no register. The commands are controlling the contents of ISA,
ISB and OUTx.
OPS[7:0] - Output Pin Set
0000 0001: CH7 input select, 1: parallel* / 0 : Serial
0000 0010: CH8 input select, 1: parallel* / 0 : Serial
0000 0100: CH9 input select, 1: parallel* / 0 : Serial
0000 1000: CH10 input select, 1: parallel* / 0 : Serial
0001 0000: CH7 output set, 1: ON / 0:OFF
0010 0000: CH8 output set, 1: ON / 0:OFF
0100 0000: CH9 output set, 1: ON / 0:OFF
1000 0000: CH10 output set, 1: ON / 0:OFF
(*parallel controlled by INx)
Sending OR operated combinations of above listed options (only
OPSx) are possible in order to control more then one channel at
the same time.
If parallel mode Mode is selected (in “input select”), the serial settings
(in “output select”) are ignored.
In parallel Mode, the selected Channels are controlled via INx Pins.
The default setting of ISB corresponds the command OPS[7:0] = xxxx
1111b. (parallel mode, status of the Outputs according signal on
INx)
Returns the contents the selected DRx register on SO in the 2nd byte
of the actual communication frame and the Output Pin
Feedback [OPF] in the 1st Byte of the next frame. (see
Chapter 12.3.2.3)
DRA[1:0]x / DRB[1:0]x
Diagnosis Register CHx Bank A and Bank B Reset Value: 0000 0000 0000B = 000h
Field Bits Type Description
11 10 9876543210
DRA[1]6 DRA[0]6 DRA[1]5 DRA[0]5 DRA[1]4 DRA[0]4 DRA[1]3 DRA[0]3 DRA[1]2 DRA[0]2 DRA[1]1 DRA[0]1
11 10 9876543210
0 0 0 0 DRB[1]10 DRB[0]10 DRB[1]9 DRB[0]9 DRB[1]8 DRB[0]8 DRB[1]7 DRB[0]7
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Data Sheet 66 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Control of the device
12.3.2.2 DRx - Return on DRx Commands
Figure 41 SPI Feedback on x_DRx commands
12.3.2.3 DMSx/OPSx - Diagnosis Mode Set / Output Pin Set Commands
Protocol
Field Bits Type Description
DRA[1:0]x /
DRB[1:0]x
1:0 R DRA[1:0]x / DRB[1:0]x
DRn[1]x/DRn[0]x = 11 no Error
DRn[1]x/DRn[0]x = 10 Over Load, Shorted Load, Over temperature in
ON-Mode
DRn[1]x/DRn[0]x = 01 Open Load in OFF-Mode
DRn[1]x/DRn[0]x = 00 Short to GND in OFF-Mode
default DRx[1:0] = 11B
A new error on the same channel will overwrite older information.
The diagnosis information which is returned by SO is latched when
CS makes a High-to-Low transistion of the frame which sends
out the register.
S_SO
SPI_Serial Output
CS1514131211109876543210
PAR 0 0 1 DRx
[1]x
DRx
[0]x
DRx
[1]x
DRx
[0]x
DRx
[1]x
DRx
[0]x
DRx
[1]x
DRx
[0]x
DRx
[1]x
DRx
[0]x
DRx
[1]x
DRx
[0]x
Field Bits Type Description
---
DRx Contents
0 no Diagnosis Error
1 Diagnosis Error
Wx_DRx R/W xxxx
dept. of
previous R/W DRx xxxx
S_CS
S_SI
S_SO
SPI_Protocol_x_DRx.vsd
x_DRx
R/W xxxx
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Data Sheet 67 Rev. 1.3.1, 2011-05-26
Each Cycle where a serial data or command frame is sent to the Serial Input [SI] of the SPI interface, a data frame
is returned immediately by the Serial Output [SO]. The content of the SO frame is dependent of the previous
command which has been sent to SI and the content of the actual content of SI: The first Byte send by S_SI
controls the content of the second byte actual returned by S_SO. The second Byte send by S_SI controls the first
byte in S_SO of the next frame. (see Figure 42)
Figure 42 Data Transfer in Diagnosis and Compact Control
Diagnosis Register
S_SI
SPI_Serial Input
1514131211109876543210
Diagnosis Mode Set DMS[4:0] Output Pin Set OPS[7:0]
- serial mode selected parallel or serial mode
0001----CH10:
1:ON
0:OFF
CH9:
1:ON
0:OFF
CH8:
1:ON
0:OFF
CH7:
1:ON
0:OFF
CH10:
0 =
serial
1 =
par.
CH9:
0 =
serial
1 =
par.
CH8:
0 =
serial
1 =
par.
CH7:
0 =
serial
1 =
par.
S_SO
SPI_Serial Output
1514131211109876543210
Output Pin Set Feedback OPF[7:0] Diagnosis Output DO[7:0]
Diagnosis Output Registers DO[7:0]
76543210
Diag Register-1 DR4[1] DR4[0] DR3[1] DR3[0] DR2[1] DR2[0] DR1[1] DR1[0]
Diag Register-2 DR1NA DR3NA 1 1 DR6[1] DR6[0] DR5[1] DR5[0]
Diag Register-3 DR10[1] DR10[0] DR9[1] DR9[0] DR8[1] DR8[0] DR7[1] DR7[0]
DMSx
S_CS
S_SI
S_SO
SPI_Protocol_Short_Mode.vsd
OPSx
Upper
Byte DO
Upper
Byte
Lower
Byte
OPF Lower
Byte
Upper
Byte
Lower
Byte
Upper
Byte
Lower
Byte
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Data Sheet 68 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Control of the device
Output Pin Feedback
12.3.3 OUTx - Output Control Register CHx
The Output Control Register OUTx consists of 10 Bits to control the Output Channel. Each Bit switches ON/OFF
the related Channel.
OUTx becomes only active when ISx[1:0] = 0x. For details refer to Chapter 12.3.4.
Field Bits Type Description
DO[7:0] 7:0 R DO[7:0] - Diagnosis Output
Contents according settings of DMS[4:0]
Returned within the same frame as the pointer is send.
DRx[1:0] definitions: see Chapter 12.3.2.1
DO[7:6]
Diag
Register-2
7:6 R DO1NA: NAND-operated diagnosis of Diag Register-1
DO3NA: NAND-operated diagnosis of Diag Register-3
1: at least one diagnosis error is stored in the related Diag Register
0: no diagnosis error is stored in the related Diag Register.
Output Pin Feedback OPF[7:0]
15 14 13 12 11 10 9 8
OPF[7] OPF[6] OPF[5] OPF[4] OPF[3] OPF[2] OPF[1] OPF[0]
Field Bits Type Description
OPF[7:0] 15:8 R OPF[7:0] - Output Pin Feedback
Principally, OPF can return the previously send OPS word and the IN
10:7 -pin settings, dependent serial/parallel-setting of OPS:
- If Serial Mode is selected by one or more OPS[3:0]-bits, the related
OPF[7:4]-bits are returning the settings of OPS[7:4], send at the
previous frame.
- if parallel Mode is selected by one or more OPS[3:0]-bits, the related
OPF[7:4]-bits are returning the condition available at the related
IN 10:7 Pins at the moment of S_CS high-to-low transition.
A mix of both modes is possible and depends on the channel related
settings.
OUTx
Output Control Register
DATA
Reset Value: 1100 0000 0000B = C00h
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Data Sheet 69 Rev. 1.3.1, 2011-05-26
12.3.4 ISx - INPUT or Serial Mode Control Register, Bank A and Bank B
The INPUT or Serial Control Register [ ISx[1:0] ] allows to define the way of controlling the Output Channels. There
are 4 setting options possible:
• Standard Serial Control: The related Output Channel is set according the content of the OUTx Register.
(Chapter 12.3.3)
• A further possibility is the control by the Input Pins
• The settings of the Parallel Mode Register PMx[0]. (Chapter 12.3.5)
• Additionally possible is the AND operation between the setting of the OUTx register and the PWM signal at the
INPUT Pin.
11109876543210
1 1 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3] OUT2 OUT1
Field Bits Type Description
OUTx[9:0] 9:0 R/W Data - OUTx[9:0]
OUTx = 0 According Channel is switched OFF
OUTx = 1 According Channel is switched ON
default (all channels OFF) OUT[9:0] = 00 0000 0000B = 000h
OUT[11:10] 11:10 R/W Data - OUTx[11:10]
bits are set to OUT[11:10] = 1.
ISAx
INPUT or Serial Mode Control Register Bank A
COMMAND
Reset Value: 1010 1010 1010B = AAAh
11 10 9876543210
IS6 IS5 IS4 IS3 IS2 IS1
ISBx
INPUT or Serial Mode Control Register Bank B
COMMAND
Reset Value: 0000 1010 1010B = 0AAh
11 10 9876543210
0 0 0 0 IS10 IS9 IS8 IS7
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Data Sheet 70 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Control of the device
12.3.5 PMx - Parallel Mode Register CHx
The Parallel Mode Register PMx[1] allows to “inform” the device about externally parallel connected output
channels. If a PMx bit is set, the “lower” related Input Channel controls the indicated Output Channels to achieve
best possible matching and according to that highest efficiency of both channels. Additionally to that, the
CLAMPsafe feature allows high matching during clamping.
12.3.6 DEVS - Device Settings
This Register allows additional Device settings. For details refer also to the Chapter “Electrical Characteristics”.
The Diagnosis Current Control register allow to select between different Diagnosis Modes. The Diagnosis
Currents can be switched off to avoid glowing of any connected LEDs.
Field Bits Type Description
ISx[1:0] 11:0 ISAx
7:0 ISBx
R/W Command - IS[1:0]
ISx[1:0]=
0x: Serial Mode - The Channel is set ON/OFF by OUTx.
10: INPUT Mode - CHx ON/OFF according INx
11: AND operate Mode INx with OUTx
-> CHx ON if OUTx & INx =1
default all Channels ISx[1:0] = 10B
PMx
Parallel Mode Register CHx
COMMAND
Reset Value: 0000 0000 0000B = 000h
11 10 9876543210
0 0 0 0 PM910 PM89 PM78 PM56 0 PM34 PM23 PM12
Field Bits Type Description
PMx 11:8 R/W 0
PMx 7:0 R/W PMx - Parallel Mode Bit
0 Direct Mode
1 Parallel Mode of Channel 1 with x+1
default PMx[0] = 0
Controlling Parallel Mode is possible between Channel 1 to 4, 5 to 6,
7 to 10. In between the groups, no parallel mode is supported
but possible.
In case Parallel Mode is chosen and a diagnosis error at only one of
the channels is detected, the according diagnosis bit is set. This
information mismatch can be caused by tolerance related in-
balance of the channels connected together in parallel mode.
The diagnosis bits should be or-operated by the Micro Controller
side.
DEVS
Device Settings
COMMAND
Reset Value: 0000 0000 0111B = 007h
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Data Sheet 71 Rev. 1.3.1, 2011-05-26
11 10 9876543210
RCP DBT2 DBT1 0 0 0 0 0 0 DCC10 DCC9 DCC18
Field Bits Type Description
RCP 11 R/W RCP - Reverse Current Protection
1: reverse current comp is enabled (valid for all Channels)
0: disabled
default: RCP = 0
DBT2 10 R/W DBT2,1 - Diagnosis Blind Time Channel 7 to 10
0,0 standard Filter Time of typ. 150µs
1,0 standard Filter Time of typ. 150µs
0,1 OFF-state diagnosis Blind Time of typ. 2.5ms
1,1 OFF-state diagnosis Blind Time of typ. 5ms
DBT1 9
DEVS[7:5] 7:5 R/W Reserved, must be set to 0
default: 0
DEVS[4:3] 4:3 R/W not used. set to ’0’
DCCx 2:0 R/W DCCx - Diagnosis Current Control
DCC18 switching ON/OFF diagnosis current of CH1-8
DCC9 switching ON/OFF diagnosis current of CH9
DCC10 switching ON/OFF diagnosis current of CH10
0 OFF-State Diagnosis (Detection of open load and short to GND)
of CHx is switched OFF. ON state diagnosis (over current and
over temperature detection) is still active.
Diagnosis Current is switched OFF.
1 OFF-State (Detection of open load and short to GND) and ON-
State (over current and over temperature detection) Diagnosis
of CHx switched ON,
Diagnosis Current is switched ON
default DCC = 1
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Data Sheet 72 Rev. 1.3.1, 2011-05-26
TLE 8110 EE
Smart Multichannel Switch
Package Outlines
13 Package Outlines
Figure 43 PG-DSO-36-41 Exposed Pad
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
P_DSO_36_24_outline .vsd
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.Dimensions in mm
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Revision History
Data Sheet 73 Rev. 1.3.1, 2011-05-26
14 Revision History
TLE8110EE
Revision History: 2011-05-26 Rev. 1.3.1
Rev. 1.3.1 2011-05-26: Data Sheet Release
New detailed description of device diagnosis in Chapter 8, polling procedure provided
Load Clamping Energy measurement setup description added at Chapter 7.2
Removed LOTC-bit configuration/functionality, Chapter 10
Added Figure 22 for Over-Current protection explanation
Added Item 11.3.21, Item 11.3.22 for diagnosis clear/read delays
Chapter 12.3.2, added description of Diagnosis Clear/Read delays
Chapter 12.2.3.4 added to describe daisy-chain operation
TOR-bit Functionality Removed
Rev. 1.3 2011-05-02: Added Reverse Current Comparator Functionality
Rev. 1.2 2011-02-02: Removed Reverse Current Comparator Functionality
Rev. 1.11 2011-02-02: footnote added for EAR specs
added footnotes 2) 3) 4) 5) in Chapter 7.3
Rev. 1.1 2011-01-10: EAS/EAR Spec Update for Single and Parallel Connection
Parallel Connection factors removed, parallel EAR spec cleaned/updated, Chapter 7.4
EAR Cumulative Scenario removed, Chapter 7.2
EAR ratings cleaned/updated, Chapter 7.3
EAS ratings cleaned/updated, Chapter 4.1
Rev. 1.01 2010-12-01: Minor changes
Clamping Energy Formula reorganized in Chapter 7.2, Equation for RL=0 removed
Rev. 1.0 2009-06-15: Data Sheet Release
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Edition 2011-05-26
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2011 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
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characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
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of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
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