ADC0816/ADC0817
8-Bit µP Compatible A/D Converters with 16-Channel
Multiplexer
General Description
The ADC0816, ADC0817 data acquisition component is a
monolithic CMOS device with an 8-bit analog-to-digital con-
verter, 16-channel multiplexer and microprocessor compat-
ible control logic. The 8-bit A/D converter uses successive
approximation as the conversion technique. The converter
features a high impedance chopper stabilized comparator, a
256R voltage divider with analog switch tree and a succes-
sive approximation register. The 16-channel multiplexer can
directly access any one of 16-single-ended analog signals,
and provides the logic for additional channel expansion. Sig-
nal conditioning of any analog input signal is eased by direct
access to the multiplexer output, and to the input of the 8-bit
A/D converter.
The device eliminates the need for external zero and
full-scale adjustments. Easy interfacing to microprocessors
is provided by the latched and decoded multiplexer address
inputs and latched TTL TRI-STATE®outputs.
The design of the ADC0816, ADC0817 has been optimized
by incorporating the most desirable aspects of several A/D
conversion techniques. The ADC0816, ADC0817 offers high
speed, high accuracy, minimal temperature dependence, ex-
cellent long-term accuracy and repeatability, and consumes
minimal power. These features make this device ideally
suited to applications from process and machine control to
consumer and automotive applications. For similar perfor-
mance in an 8-channel, 28-pin, 8-bit A/D converter, see the
ADC0808, ADC0809 data sheet. (See AN-258 for more in-
formation.)
Features
nEasy interface to all microprocessors, or operates “stand
alone”
nOperates ratiometrically or with 5 V
DC
or analog span
adjusted voltage reference
n16-channel multiplexer with latched control logic
nOutputs meet TTL voltage level specifications
n0V to 5V analog input voltage range with single 5V
supply
nNo zero or full-scale adjust required
nStandard hermetic or molded 40-pin DIP package
nTemperature range −40˚C to +85˚C or −55˚C to +125˚C
nLatched TRI-STATE output
nDirect access to “comparator in” and “multiplexer out” for
signal conditioning
nADC0816 equivalent to MM74C948
nADC0817 equivalent to MM74C948-1
Key Specifications
nResolution: 8 Bits
nTotal Unadjusted Error: ±
1
⁄
2
LSB and ±1 LSB
nSingle Supply: 5 V
DC
nLow Power: 15 mW
nConversion Time: 100 µs
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
December 1994
ADC0816/ADC0817 8-Bit µP Compatible A/D Converters with 16-Channel Multiplexer
© 1997 National Semiconductor Corporation DS005277 www.national.com
Block Diagram
DS005277-1
www.national.com 2
Absolute Maximum Ratings (Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) (Note 3) 6.5V
Voltage at Any Pin −0.3V to (V
CC
+0.3V)
Except Control Inputs
Voltage at Control Inputs −0.3V to 15V
(START, OE, CLOCK, ALE, EXPANSION CONTROL,
ADD A, ADD B, ADD C, ADD D)
Storage Temperature Range −65˚C to + 150˚C
Package Dissipation at T
A
=25˚C 875 mW
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (Plastic) 260˚C
Dual-In-Line Package (Ceramic) 300˚C
Molded Chip Carrier Package
Vapor Phase (60 seconds) 215˚C
Infrared (15 seconds) 220˚C
ESD Susceptibility (Note 9) 400V
Operating Conditions (Notes 1, 2)
Temperature Range (Note 1) T
MIN
≤T
A
≤T
MAX
ADC0816CCJ, ADC0816CCN, −40˚C≤T
A
≤+85˚C
ADC0817CCN
Range of V
CC
(Note 1) 4.5 V
DC
to 6.0 V
DC
Voltage at Any Pin 0V to V
CC
Except Control Inputs
Voltage at Control Inputs 0V to 15V
(START, OE, CLOCK, ALE, EXPANSION CONTROL,
ADD A, ADD B, ADD C, ADD D)
Electrical Characteristics
Converter Specifications: V
CC
=5V
DC
=V
REF(+)
,V
REF(−)
=GND, V
IN
=V
COMPARATOR IN,
T
MIN
≤T
MAX
and f
CLK
=640 kHz unless
otherwise stated.
Symbol Parameter Conditions Min Typ Max Units
ADC0816
Total Unadjusted Error 25˚C ±
1
⁄
2
LSB
(Note 5) T
MIN
to T
MAX
±
3
⁄
4
LSB
ADC0817
Total Unadjusted Error 0˚C to 70˚C ±1 LSB
(Note 5) T
MIN
to T
MAX
±1
1
⁄
4
LSB
Input Resistance From Ref(+) to Ref(−) 1.0 4.5 kΩ
Analog Input Voltage Range (Note 4) V(+) or V(−) GND−0.10 V
CC
+0.10 V
DC
V
REF(+)
Voltage, Top of Ladder Measured at Ref(+) V
CC
V
CC
+0.1 V
Voltage, Center of Ladder V
CC
/2−0.1 V
CC
/2 V
CC
/2+0.1 V
V
REF(−)
Voltage, Bottom of Ladder Measured at Ref(−) −0.1 0 V
Comparator Input Current f
c
=640 kHz, (Note 6) −2 ±0.5 2 µA
Electrical Characteristics
Digital Levels and DC Specifications: ADC0816CCJ, ADC0816CCN, ADC0817CCN—4.75V≤V
CC
≤5.25V, −40˚C≤T
A
≤+85˚C
unless otherwise noted.
Symbol Parameter Conditions Min Typ Max Units
ANALOG MULTIPLEXER
R
ON
Analog Multiplexer ON (Any Selected Channel)
Resistance T
A
=25˚C, R
L
=10k 1.5 3 kΩ
T
A
=85˚C 6 kΩ
T
A
=125˚C 9 kΩ
∆R
ON
∆ON Resistance Between Any (Any Selected Channel) 75 Ω
2 Channels R
L
=10k
I
OFF+
OFF Channel Leakage Current V
CC
=5V, V
IN
=5V,
T
A
=25˚C 10 200 nA
T
MIN
to T
MAX
1.0 µA
I
OFF(−)
OFF Channel Leakage Current V
CC
=5V, V
IN
=0,
T
A
=25˚C −200 nA
T
MIN
to T
Max
−1.0 µA
3 www.national.com
Electrical Characteristics (Continued)
Digital Levels and DC Specifications: ADC0816CCJ, ADC0816CCN, ADC0817CCN—4.75V≤V
CC
≤5.25V, −40˚C≤T
A
≤+85˚C
unless otherwise noted.
Symbol Parameter Conditions Min Typ Max Units
CONTROL INPUTS
V
IN(1)
Logical “1” Input Voltage V
CC
−1.5 V
V
IN(0)
Logical “0” Input Voltage 1.5 V
I
IN(1)
Logical “1” Input Current V
IN
=15V 1.0 µA
(The Control Inputs)
I
IN(0)
Logical “0” Input Current V
IN
=0 −1.0 µA
(The Control Inputs)
I
CC
Supply Current f
CLK
=640 kHz 0.3 3.0 mA
DATA OUTPUTS AND EOC (INTERRUPT)
V
OUT(1)
Logical “1” Output Voltage I
O
−360 µA, T
A
=85˚C V
CC
−0.4 V
I
O
=−300 µA, T
A
=125˚C
V
OUT(0)
Logical “0” Output Voltage I
O
=1.6 mA 0.45 V
V
OUT(0)
Logical “0” Output Voltage EOC I
O
=1.2 mA 0.45 V
I
OUT
TRI-STATE Output Current V
O
=V
CC
3.0 µA
V
O
=0 −3.0 µA
Electrical Characteristics
Timing Specifications: V
CC
=V
REF(+)
=5V, V
REF(−)
=GND, t
r
=t
f
=20 ns and T
A
=25˚C unless otherwise noted.
Symbol Parameter Conditions Min Typ Max Units
t
WS
Minimum Start Pulse Width (
Figure 5
) (Note 7) 100 200 ns
t
WALE
Minimum ALE Pulse Width (
Figure 5
) 100 200 ns
t
s
Minimum Address Set-Up Time (
Figure 5
)2550ns
T
H
Minimum Address Hold Time (
Figure 5
)2550ns
t
D
Analog MUX Delay Time R
S
=OΩ(
Figure 5
) 1 2.5 µS
from ALE
t
H1
,t
H0
OE Control to Q Logic State C
L
=50 pF, R
L
=10k (
Figure 8
) 125 250 ns
t
1H,
t
0H
OE Control to Hi-Z C
L
=10 pF, R
L
=10k (
Figure 8
) 125 250 ns
t
C
Conversion Time f
c
=640 kHz, (
Figure 5
) (Note 8) 90 100 116 µs
f
c
Clock Frequency 10 640 1280 kHz
t
EOC
EOC Delay Time (
Figure 5
) 0 8+2µs Clock
Periods
C
IN
Input Capacitance At Control Inputs 10 15 pF
C
OUT
TRI-STATE Output At TRI-STATE Outputs (Note 8) 10 15 pF
Capacitance
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: A zener diode exists, internally, from VCC to GND and has a typical breakdown voltage of 7 VDC.
Note 4: Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater
than the VCC supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more
than 100 mV, the output code will be correct. To achieve an absolute 0 VDC to5V
DC input voltage range will therefore require a minimum supply voltage of 4.900
VDC over temperature variations, initial tolerance and loading.
Note 5: Total unadjusted error includes offset, full-scale, and linearity errors. See
Figure 3
. None of these A/Ds requires a zero or full-scale adjust. However, if an
all zero code is desired for an analog input other than 0.0V, or if a narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the reference voltages can be
adjusted to achieve this. See
Figure 13
.
Note 6: Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and has little
temperature dependence (
Figure 6
). See paragraph 4.0.
Note 7: If start pulse is asynchronous with converter clock or if fc>640 kHz, the minimum start pulse width is 8 clock periods plus 2 µs. For synchronous operation
at fc≤640 kHz take start high within 100 ns of clock going low.
Note 8: The outputs of the data register are updated one clock cycle before the rising edge of EOC.
Note 9: Human body model, 100 pF discharged through a 1.5 kΩresistor.
www.national.com 4
Functional Description
Multiplexer: The device contains a 16-channel single-ended
analog signal multiplexer. A particular input channel is se-
lected by using the address decoder.
Table *NO TGT: table
NS0669*
shows the input states for the address line and the
expansion control line to select any channel. The address is
latched into the decoder on the low-to-high transition of the
address latch enable signal.
Selected Address Line Expansion
Analog Channel DCBA Control
IN0 LLLL H
IN1 L L L H H
IN2 L L H L H
IN3 L L H H H
IN4 L H L L H
IN5 LHLH H
IN6 LHHL H
IN7 L H H H H
IN8 H L L L H
IN9 HLLH H
IN10 HLHL H
IN11 H L H H H
IN12 H H L L H
IN13 H H L H H
IN14 H H H L H
IN15 HHHH H
All Channels OFF XXXX L
X
=
don’t care
Additional single-ended analog signals can be multiplexed to
theA/D converter by disabling all the multiplexer inputs using
the expansion control. The additional external signals are
connected to the comparator input and the device ground.
Additional signal conditioning (i.e., prescaling, sample and
hold, instrumentation amplification, etc.) may also be added
between the analog input signal and the comparator input.
CONVERTER CHARACTERISTICS
The Converter
The heart of this single chip data acquisition system is its
8-bit analog-to-digital converter. The converter is designed to
give fast, accurate, and repeatable conversions over a wide
range of temperatures. The converter is partitioned into 3
major sections: the 256R ladder network, the successive ap-
proximation register, and the comparator. The converter’s
digital outputs are positive true.
The 256R ladder network approach
Figure 1
was chosen
over the conventional R/2R ladder because of its inherent
monotonicity, which guarantees no missing digital codes.
Monotonicity is particularly important in closed loop feedback
control systems.A non-monotonic relationship can cause os-
cillations that will be catastrophic for the system.Additionally,
the 256R network does not cause load variations on the ref-
erence voltage.
The bottom resistor and the top resistor of the ladder net-
work in
Figure 1
are not the same value as the remainder of
the network. The difference in these resistors causes the
output characteristic to be symmetrical with the zero and
full-scale points of the transfer curve. The first output transi-
tion occurs when the analog signal has reached +
1
⁄
2
LSB
and succeeding output transitions occur every 1 LSB later up
to full-scale.
DS005277-2
FIGURE 1. Resistor Ladder and Switch Tree
5 www.national.com
Functional Description (Continued)
Timing Diagram
DS005277-3
FIGURE 2. 3-Bit A/D Transfer Curve
DS005277-4
FIGURE 3. 3-Bit A/D Absolute Accuracy Curve
DS005277-5
FIGURE 4. Typical Error Curve
DS005277-7
FIGURE 5.
www.national.com 6
Timing Diagram (Continued)
The successive approximation register (SAR) performs 8 it-
erations to approximate the input voltage. For any SAR type
converter, n-iterations are required for an n-bit converter.
Figure 2
shows a typical example of a 3-bit converter. In the
ADC0816, ADC0817, the approximation technique is ex-
tended to 8 bits using the 256R network.
The A/D converter’s successive approximation register
(SAR) is reset on the positive edge of the start conversion
(SC) pulse. The conversion is begun on the falling edge of
the start conversion pulse.A conversion in process will be in-
terrupted by receipt of a new start conversion pulse. Con-
tinuous conversion may be accomplished by tying the
end-of-conversion (EOC) output to the SC input. If used in
this mode, an external start conversion pulse should be ap-
plied after power up. End-of-conversion will go low between
0 and 8 clock pulses after the rising edge of start conversion.
The most important section of the A/D converter is the com-
parator. It is this section which is responsible for the ulimate
accuracy of the entire converter. It is also the comparator
drift which has the greatest influence on the repeatability of
the device. A chopper-stabilized comparator provides the
most effective method of satisfying all the converter require-
ments.
The chopper-stabilized comparator converts the DC input
signal into an AC signal. This signal is then fed through a
high gain AC amplifier and has the DC level restored. This
technique limits the drift component of the amplifier since the
drift is a DC component which is not passed by the AC am-
plifier. This makes the entire A/D converter extremely insen-
sitive to temperature, long term drift and input offset errors.
Figure 4
shows a typical error curve for the ADC0816 as
measured using the procedures outlined in AN-179.
Connection Diagram
DS005277-6
Order Number ADC0816CCN, ADC0817CCN,
ADC0816CCJ or ADC0816CJ
See NS Package Number J40A or N40A
7 www.national.com
Typical Performance Characteristics
TRI-STATE Test Circuits and Timing Diagrams
Applications Information
OPERATION
1.0 RATIOMETRIC CONVERSION
The ADC0816, ADC0817 is designed as a complete Data
Acquisition System (DAS) for ratiometric conversion sys-
tems. In ratiometric systems, the physical variable being
measured is expressed as a percentage of full-scale which is
not necessarily related to an absolute standard. The voltage
input to the ADC0816 is expressed by the equation
(1)
V
IN
=Input voltage into the ADC0816
V
fs
=Full-scale voltage
V
Z
=Zero voltage
D
X
=Data point being measured
D
MAX
=Maximum data limit
D
MIN
=Minimum data limit
DS005277-18
FIGURE 6. Comparator I
IN
vs V
IN
(V
CC
=V
REF
=5V)
DS005277-19
FIGURE 7. Multiplexer R
ON
vs V
IN
(V
CC
=V
REF
=5V)
DS005277-9
DS005277-10
FIGURE 8.
www.national.com 8
Applications Information (Continued)
A good example of a ratiometric transducer is a potentiom-
eter used as a position sensor. The position of the wiper is di-
rectly proportional to the output voltage which is a ratio of the
full-scale voltage across it. Since the data is represented as
a proportion of full-scale, reference requirements are greatly
reduced, eliminating a large source of error and cost for
many applications. A major advantage of the ADC0816,
ADC0817 is that the input voltage range is equal to the sup-
ply range so the transducers can be connected directly
across the supply and their outputs connected directly into
the multiplexer inputs, (
Figure 9
).
Ratiometric transducers such as potentiometers, strain
gauges, thermistor bridges, pressure transducers, etc., are
suitable for measuring proportional relationships; however,
many types of measurements must be referred to an abso-
lute standard such as voltage or current. This means a sys-
tem reference must be used which relates the full-scale volt-
age to the standard volt. For example, if V
CC
=V
REF
=
5.12V, then the full-scale range is divided into 256 standard
steps. The smallest standard step is 1 LSB which is then 20
mV.
2.0 RESISTOR LADDER LIMITATIONS
The voltages from the resistor ladder are compared to the
selected input 8 times in a conversion. These voltages are
coupled to the comparator via an analog switch tree which is
referenced to the supply. The voltages at the top, center and
bottom of the ladder must be controlled to maintain proper
operation.
The top of the ladder, Ref(+), should not be more positive
than the supply, and the bottom of the ladder, Ref(−), should
not be more negative than ground. The center of the ladder
voltage must also be near the center of the supply because
the analog switch tree changes from N-channel switches to
P-channel switches These limitations are automaticaly satis-
fied in ratiometric systems and can be easily met in ground
referenced systems.
Figure 10
shows a ground referenced system with a sepa-
rate supply and reference. In this system, the supply must be
trimmed to match the reference voltage. For instance, if a
5.12V reference is used, the supply should be adjusted to
the same voltage within 0.1V.
The ADC0816 needs less than a milliamp of supply current
so developing the supply from the reference is readily ac-
complished. In
Figure 11
a ground references system is
shown which generates the supply from the reference. The
buffer shown can be an op amp of sufficient drive to supply
the millliamp of supply current and the desired bus drive, or
if a capacitive bus is driven by the outputs a large capacitor
will supply the transient supply current as seen in
Figure 12
.
The LM301 is overcompensated to insure stability when
loaded by the 10 µF output capacitor.
The top and bottom ladder voltages cannot exceed V
CC
and
ground, respectively, but they can be symmetrically less than
V
CC
and greater than ground. The center of the ladder volt-
age should always be near the center of the supply. The sen-
sitivity of the converter can be increased, (i.e., size of the
LSB steps decreased) by using a symmetrical reference sys-
tem. In
Figure 13
, a 2.5V reference is symmetrically cen-
tered about V
CC
/2 since the same current flows in identical
resistors. This system with a 2.5V reference allows the LSB
to be half the size of the LSB in a 5V reference system.
DS005277-11
FIGURE 9. Ratiometric Conversion System
9 www.national.com
Applications Information (Continued)
DS005277-12
FIGURE 10. Ground Referenced
Conversion System Using Trimmed Supply
DS005277-13
FIGURE 11. Ground Referenced Conversion System with
Reference Generating V
CC
Supply
DS005277-14
FIGURE 12. Typical Reference and Supply Circuit
www.national.com 10
Applications Information (Continued)
3.0 CONVERTER EQUATIONS
The transition between adjacent codes N andN+1isgiven
by:
(2)
The center of an output code N is given by:
(3)
The output code N for an arbitrary input are the integers
within the range:
(4)
where: V
IN
=Voltage at comparator input
V
REF
=Voltage at Ref(+)
V
REF
=Voltage at Ref(−)
V
TUE
=Total unadjusted error voltage (typically
V
REF
(+) ÷512)
4.0 ANALOG COMPARATOR INPUTS
The dynamic comparator input current is caused by the pe-
riodic switching of on-chip stray capacitances These are
connected alternately to the output of the resistor ladder/
switch tree network and to the comparator input as part of
the operation of the chopper stabilized comparator.
The average value of the comparator input current varies di-
rectly with clock frequency and with V
IN
as shown in
Figure
6
.
If no filter capacitors are used at the analog or comparator in-
puts and the signal source impedances are low, the com-
parator input current should not introduce converter errors,
as the transient created by the capacitance discharge will die
out before the comparator output is strobed.
If input filter capacitors are desired for noise reduction and
signal conditioning they will tend to average out the dynamic
comparator input current. It will then take on the characteris-
tics of a DC bias current whose effect can be predicted con-
ventionally. See AN-258 for further discussion.
DS005277-15
FIGURE 13. Symmetrically Centered Reference
11 www.national.com
Typical Application
Microprocessor Interface Table
PROCESSOR READ WRITE INTERRUPT (COMMENT)
8080 MEMR MEMW INTR (Thru RST Circuit)
8085 RD WR INTR (Thru RST Circuit)
Z-80 RD WR INT (Thru RST Circuit, Mode 0)
SC/MP NRDS NWDS SA (Thru Sense A)
6800 VMA•φ2•R/W VMA•Q
2
•R/W IRQA or IRQB (Thru PIA)
Ordering Information
TEMPERATURE RANGE −40˚C to +85˚C
Error ±
1
⁄
2
Bit Unadjusted ADC0816CCN ADC0816CCJ
±1 Bit Unadjusted ADC0817CCN
Package Outline N40A Molded DIP J40A Hermetic DIP
DS005277-16
*Address latches needed for 8085 and SC/MP interfacing the ADC0816, 17 to a microprocessor
www.national.com 12
Physical Dimensions inches (millimeters) unless otherwise noted
Cavity Dual-In-Line Package (J)
NS Package Number J40A
Molded Dual-In-Line Package (N)
NS Package Number N40A
13 www.national.com
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ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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ADC0816/ADC0817 8-Bit µP Compatible A/D Converters with 16-Channel Multiplexer
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
