DATASHEET RAA210850 FN9346 Rev.1.00 Mar 15, 2019 Pin-Configurable 50A DC/DC Power Module with PMBus Interface The RAA210850 is a pin-strap configurable 50A step-down PMBus-compliant DC/DC power supply module that integrates a digital PWM controller, synchronous MOSFETs, power inductor, and passive components. Only input and output capacitors are needed to finish the design. Because of its thermally enhanced HDA packaging technology, the module can deliver up to 50A of continuous output current without the need for airflow or additional heat sinking. The RAA210850 simplifies configuration and control of Renesas digital power technology while offering an upgrade path to full PMBus configuration through the pin-compatible ISL8272M. The RAA210850 operates with the ChargeModeTM control architecture, which responds to a transient load within a single switching cycle. The RAA210850 can be easily programmed with pin-strap resistors to set the output voltage, switching frequency, input UVLO, soft-start/stop, and device addresses. PMBus can be used to monitor voltages, currents, temperatures, and fault status. The RAA210850 is supported by PowerNavigatorTM software, a Graphical User Interface (GUI), that can configure modules for desired solutions. The RAA210850 is available in a low profile, compact, (18mmx23mmx7.5mm) fully encapsulated, thermally enhanced HDA package, suitable for automated assembly by standard surface mount equipment. Related Literature Features * Wide input voltage range: 4.5V to 14V * Up to 96% efficiency * Programmable output voltage * 0.6V to 5V output voltage settings * 1.2% VOUT accuracy over line, load, and temperature * PMBus compliant communication interface * Pin-strap mode for standard settings * VOUT, switching frequency, input UVLO, soft-start/stop, and external synchronization * Real-time telemetry for VIN, VOUT, IOUT, temperature, duty cycle, and switching frequency * Complete overvoltage, undervoltage, current and temperature protections with fault logging * PowerNavigator supported * Thermally enhanced HDA package Applications * Server, telecom, storage, and datacom * Industrial/ATE and networking equipment * General purpose power for ASIC, FPGA, DSP, and memory For a full list of related documents, visit our website: * RAA210850 product page VIN VIN CIN VOUT VDD VSENP ENABLE EN VOUT 18m COUT m 23 VSENN VR5 10F 10F VR6 VDRV m m VR RAA210850 VR55 VCC SCL VDRV1 100k SDA 2x10F SALRT VMON 6.65k SGND PMBus Interface 7.5mm PGND Note: 1. Figure 1 represents a typical implementation of the RAA210850. Renesas recommends tying the enable pin (EN) to SGND for Figure 1. 50A Application Circuit FN9346 Rev.1.00 Mar 15, 2019 Figure 2. A Small Package for High Power Density Page 1 of 58 RAA210850 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 1.2 1.3 1.4 1.5 2. Typical Application Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 8 9 9 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 2.2 2.3 2.4 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 11 12 Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 3.2 3.3 4. Efficiency Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Transient Response Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Derating Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 5. SMBus Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soft-Start/Stop Delay and Ramp Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Good. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Frequency and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loop Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMBus Module Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Prebias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Overcurrent Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Overload Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitoring with SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Snapshot Parameter Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 21 22 22 22 23 24 25 26 27 27 27 28 28 Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 5.2 5.3 5.4 5.5 5.6 Thermal Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCB Layout Pattern Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stencil Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reflow Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FN9346 Rev.1.00 Mar 15, 2019 30 30 30 30 30 30 Page 2 of 58 RAA210850 6. PMBus Command Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1 6.2 PMBus Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PMBus Use Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7. PMBus Commands Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.1 8.2 9. Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Datasheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 FN9346 Rev.1.00 Mar 15, 2019 Page 3 of 58 RAA210850 Overview 1.1 Typical Application Module 6&/ 6'$ 6'$ 6$/57 3* &)* 5 5 5 95 95 6$/57 ) %XON & 5 96(7B),1( 6&/ 5 $6&5 5 5 6<1& 5 5 6$ 5 9 3* N N N Note 3 9,1 (1 Note 2 Note 2 6689/2 9$8;RU9&& 9WR9 (1 3LQ6WUDS5HVLVWRUV 96(7B&56 FN9346 Rev.1.00 Mar 15, 2019 1. [) &HUDPLF 6: 9,1 & & 6:' 6:' 9'' ) ) ) & & 6: 5$$ 95 [) &HUDPLF 95 [) 326&$3 9287 9'59 9'59 9021 5 N & 5 96(11 & 96(13 & & 3*1' 5 N 9&& 6*1' 9&& ) ) 9287 9$ Figure 3. Typical Application Circuit - Single Module 1. Overview Page 4 of 58 Notes: 2. R2 and R3 are not required if the PMBus host already has I2C pull-up resistors. 3. R6 through R11 can be selected according to the tables for the pin-strap resistor setting in this document. 4. V25, VR, and VR55 do not need external capacitors. V25 can be no connection. RAA210850 1. Overview Table 1. RAA210850 Design Guide Matrix and Output Voltage Response COUT (Ceramic) (F) ASCR Residual (Note 6) ASCR Gain (Note 6) P-P Deviation (mV) Recovery Time (s) VIN (V) VOUT (V) COUT (Bulk) (F) 12 0.7 5x470 12 x100 90 280 64.39 12.8 0 - 25 364 12 0.7 4x470 8 x100 90 600 61.25 10.23 0 - 25 615 5 0.7 5x470 12 x100 90 280 62.36 12.26 0 - 25 364 5 0.7 4x470 8 x100 90 500 61.32 7.47 0 - 25 640 12 0.8 5x470 10 x100 90 250 72.59 14.7 0 - 25 364 12 0.8 3x470 10 x100 100 450 70.76 9.83 0 - 25 615 5 0.8 5x470 10 x100 90 250 65.88 11.86 0 - 25 364 5 0.8 3x470 10 x100 90 450 65.29 8.66 0 - 25 615 12 0.9 4x470 12 x100 90 230 80 12.8 0 - 25 364 12 0.9 3x470 8 x100 90 320 81.85 10.58 0 - 25 615 5 0.9 4x470 12 x100 90 230 73.84 12.26 0 - 25 364 5 0.9 3x470 8 x100 90 320 78.73 9.06 0 - 25 615 12 1 3x470 10 x100 90 250 91.65 10.8 0 - 25 421 12 1 2x470 9 x100 100 320 92.06 11.38 0 - 25 615 5 1 3x470 10 x100 90 220 84.2 12.65 0 - 25 421 5 1 2x470 9 x100 100 320 85.83 11.46 0 - 25 727 12 1.2 2x470 11 x100 100 240 107.16 10.41 0 - 25 471 12 1.2 2x470 8 x100 90 320 103.49 8.22 0 - 25 727 5 1.2 2x470 11 x100 100 240 98.35 15 0 - 25 471 5 1.2 2x470 8 x100 90 320 99.77 8.62 0 - 25 727 12 1.5 2x470 6 x100 90 160 137.69 10.4 0 - 25 471 12 1.5 1x470 8 x100 100 240 131.45 9.71 0 - 25 727 5 1.5 2x470 6 x100 90 160 133.77 17 0 - 25 471 5 1.5 1x470 8 x100 100 240 140.51 12.61 0 - 25 727 12 1.8 1x470 12 x100 100 160 151.12 12.61 0 - 25 471 12 1.8 1x470 6 x100 100 200 159.72 9.46 0 - 25 727 5 1.8 1x470 12 x100 100 160 150.77 22.98 0 - 25 471 5 1.8 1x470 6 x100 100 200 159.62 17.39 0 - 25 727 12 2.5 1x470 9 x100 100 160 174.37 9.81 0 - 25 533 5 2.5 1x470 9 x100 100 160 168.41 29.37 0 - 25 533 12 3.3 1x470 7 x100 90 120 218.11 8.62 0 - 25 533 12 5 1x470 9 x100 90 120 224.44 5.03 0-2 571 Load Step Frequency (A) (Note 7) (kHz) Notes: 5. 1 x 470F input bulk (EEE1EA471P) and 6x22F input ceramic (CRM32ER71C226KE18L) capacitors are used to evaluate all test conditions above. The CIN bulk capacitor is optional only for energy buffer from the long input power supply cable. 6. ASCR gain and residual are selected to ensure phase margin higher than 60 and gain margin higher than 8dB at room temperature. 7. Output voltage response is tested with 0 to 50% load step and slew rate at 15A/s. FN9346 Rev.1.00 Mar 15, 2019 Page 5 of 58 RAA210850 1. Overview Table 2. Recommended Input/Output Capacitors Vendors Value Part Number Murata, Input Ceramic 47F, 16V, 1210 GRM32ER61C476ME15L Murata, Input Ceramic 22F, 25V, 1210 GRM32ER61E226KE15L Murata, Input Ceramic 22F, 16V, 1210 GRM32ER71C226KE18L Murata, Output Ceramic 100F, 6.3V, 1206 GRM31CR60J107ME39L TDK, Output Ceramic 100F, 6.3V, 1206 C3216X5R0J107M160AB Panasonic, Output Bulk 470F, 4V, 2917 4TPE470MCL Panasonic, Output Bulk 470F, 6.3V, 2917 6TPF470MAH Panasonic, Input Bulk 470F, 25V EEE1EA471P FN9346 Rev.1.00 Mar 15, 2019 Page 6 of 58 RAA210850 9'59 9'59 9&& 9,1 95 95 9 95 95 Internal Block Diagram 9'' 1.2 1. Overview /'2 2989 2787 2&8& 6:' 6: /RJLF + /'2V 9287 9'59 ,17(5/($9( 3RZHU0DQDJHPHQW 3*1' 66 $6&5 96(7B),1( 96(7B&56 6689/2 (1 3* &)* 9'59 9,1 )LOWHU 61$36+27 6<1& 287 3:0 6<1& 3// '3:0 3:0 &KDUJH0RGH70 &RQWURO 6XSHUYLVRU 9,1 9'59 190 6:' 6: $'& + &6$ 9'59 $'& /RJLF 3URWHFWLRQ 9287 &6$ $'& 3*1' 96$ 9'' $'& ,QWHUQDO7HPS 6HQVRU 6&/ 6'$ 6$/57 30%XV,& ,QWHUIDFH : 6$ 96(13 96(11 6*1' : 3*1' 6*1' 9021 'LJLWDO&RQWUROOHU Figure 4. Internal Block Diagram FN9346 Rev.1.00 Mar 15, 2019 Page 7 of 58 RAA210850 1.3 1. Overview Ordering Information Part Number (Notes 9, 10) Part Marking Temp Range (c) Tape and Reel (Units) (Note 8) Package (RoHS Compliant) Pkg. Dwg. # RAA2108502GLG#AG0 RAA2108502 -40 to +85 - 58 Ld 18x23 HDA Y58.18x23 RAA2108502GLG#HG0 RAA2108502 -40 to +85 100 58 Ld 18x23 HDA Y58.18x23 RTKA2108502H00000BU Single-Module Evaluation Board Notes: 8. Refer to TB347 for details about reel specifications. 9. These Pb-free plastic packaged products are RoHS compliant by EU exemption 7C-I and 7A. They employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4 termination finish, which is compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 10. For Moisture Sensitivity Level (MSL), refer to the RAA210850 device. For more information about MSL, refer to TB363. Table 3. Key Differences between Family of Parts Part Number Description VIN Range (V) VOUT Range (V) IOUT (A) RAA210850 50A DC/DC single channel power module 4.5 - 14 0.6 - 5 50 RAA210833 33A DC/DC single channel power module 4.5 - 14 0.6 - 5 33 RAA210825 25A DC/DC single channel power module 4.5 - 14 0.6 - 5 25 RAA210870 70A DC/DC single channel power module 4.5 - 14 0.6 - 2.5 70 RAA210925 25A/25A DC/DC dual channel power module 4.5 - 14 0.6 - 5 25/25 Table 4. Comparison of Simple Digital and Full Digital Parts ISL8272M RAA210850 VIN (V) 4.5 - 14 4.5 - 14 VOUT (V) 0.6 - 5 0.6 - 5 50 50 296 - 1067 296 - 1067 IOUT (Max) (A) fSW (kHz) Digital PMBus Programmablility for Configuration of Modules All PMBus commands. NVM access to store module configuration Configuration of modules supported by pin-strap resistors. Digital programmability supports configuration changes during run-time operation with a subset of PMBus commands. No NVM access to store module configuration Power Navigator Support Yes Yes SYNC Capability Yes Yes Current Sharing Multi-Modules Yes No DDC Pin (Inter-Device Communication) Yes No Note: For a full comparison of all the RAA210XXX and ISL827XM product offerings, please visit the simple-digital module family page. FN9346 Rev.1.00 Mar 15, 2019 Page 8 of 58 RAA210850 1.4 1. Overview Pin Configuration 58 Ld HDA Top View $ 3$' 9287 3$' 9287 % 96(7B&56 & ( 6&/ 6689/2 96(7B),1( 9021 6$/57 6'$ 3$' 3$' ' ) 6$ &)* 7(67 7(67 7(67 6<1& 3* 7(67 (1 3*1' 3*1' 7(67 3*1' 3*1' 7(67 * 3$' 96(13 $6&5 3$' - 3$' + 7(67 96(11 9 6*1' . 9'' / 6*1' 95 6:' 95 3*1' 3*1' 0 95 9&& 95 6*1' 1 3 3$' 6:' 3*1' 9'59 9'59 9'59 9'59 9,1 5 3$' 7 9,1 8 3$' 3*1' 3$' 3$' 9,1 3*1' 9 : 6: 3*1' 6: 3*1' < $$ 3$' 3$' $% 3$' $& 1.5 3$' Pin Descriptions Pin Label Type PAD1, 2 VOUT PWR Power supply output voltage. Output voltage from 0.6V to 5V. Tie these two pads together to achieve a single output. For higher output voltage, refer to the derating curves starting on page 17 to set the maximum output current from these pads. PAD3, 4, 5, 7, 10, 12, 13, 15 PGND PWR Power ground. Refer to "Layout Guidelines" on page 29 for the PGND pad connections and I/O capacitor placement. PAD6 SGND PWR Signal ground. Refer to "Layout Guidelines" on page 29 for the SGND pad connections. PAD8, 9, 11 VIN PWR Input power supply voltage to power the module. The input voltage range is 4.5V to 14V. PAD14, 16 SW1, SW2 PWR Switching node pads. The SW pads dissipate heat and provide good thermal performance. Refer to "Layout Guidelines" on page 29 for the SW pad connections. C6 VSET_CRS I Output voltage selection pin. Used to set the VOUT set point. Use VSET_FINE for fine-tuning. C7 VSET_FINE I Output voltage fine-tuning. Provides increased VOUT resolution based on the programmed VSET_CRS value. FN9346 Rev.1.00 Mar 15, 2019 Description Page 9 of 58 RAA210850 1. Overview Pin Label Type Description C8 CFG I Clock source configuration pin. If the clock source is set to be internal, the internal frequency is set according to the SYNC pin resistor settings. If the clock source is set to external, the internal frequency is set according to the CFG pin resistor. Refer to "Switching Frequency and PLL" on page 22 for more information. C9 VMON I Driver voltage monitoring. Use this pin to monitor VDRV through an external 16:1 resistor divider. C10 SA I Serial address selection pin. Assigns a unique address for each individual device and enables certain management features. C11 SALRT O Serial alert. Connect to an external host if desired. SALRT is asserted low upon a fault event and deasserted when the fault is cleared. A pull-up resistor is required. C12 SDA I/O Serial data. Connect to an external host and/or to other Digital-DCTM devices. A pull-up resistor is required. C13 SCL I/O Serial clock. Connect to an external host and/or to other Digital-DC devices. A pull-up resistor is required. D4 SS/ UVLO I Soft-start/stop and undervoltage lockout selection pin. Sets the turn on/off delay and ramp time and the input UVLO threshold levels. D5 PG O Power-good output. The power-good is configured as an open-drain output. D13 SYNC I/O Clock synchronization input. Sets the frequency of the internal switch clock, or synchronizes to an external clock. E14 EN I Enable pin. Logic high to enable the module output. C5, D14, E4, E15, F4, F15, G4 TEST - Test pins. Do not connect these pins. G14 ASCR I ChargeModeTM control ASCR parameters selection pin. Sets ASCR gain and residual values. G15 V25 PWR Internal 2.5V reference that powers internal circuitry. No external capacitor is required for this pin. H3 VSENN I Differential output voltage sense feedback. Connect to the negative output regulation point. H4 VSENP I Differential output voltage sense feedback. Connect to the positive output regulation point. H16, J16, K16, M14 SGND PWR Signal grounds. Use multiple vias to connect the SGND pins to the internal SGND layer. K14 VDD PWR Input supply voltage for the controller. Connect the VDD pad to the VIN supply. L2 VR PWR Internal LDO bias pin. Tie VR directly to VR55 with a short loop trace. L3, P11 SWD1, SWD2 PWR Switching node driving pins. Directly connect to the SW1 and SW2 pads with short loop wires. L14 VR5 PWR Internal 5V reference that powers internal circuitry. Place a 10F decoupling capacitor for this pin. M1 VCC PWR Internal LDO output. Connect VCC to VDRV for internal LDO driving. M5, M17, N5 PGND PWR Power grounds. Use multiple vias to connect the PGND pins to the internal PGND layer. M10 VR55 PWR Internal 5.5V bias voltage for internal LDO use only. Tie VR55 directly to the VR pin. M13 VR6 PWR Internal 6V reference used to power internal circuitry. Place a 10F decoupling capacitor for this pin. N6, N16 VDRV PWR Power supply for internal FET drivers. Connect a 10F bypass capacitor to each of these pins. These pins can be driven by the internal LDO through VCC pin or by the external power supply directly. Keep the driving voltage between 4.5V and 5.5V. For 5V input applications, use an external supply or connect this pin to VIN. R8, R17 VDRV1 I FN9346 Rev.1.00 Mar 15, 2019 Bias pin of the internal FET drivers. Always tie to VDRV. Page 10 of 58 RAA210850 2. 2. Specifications Specifications 2.1 Absolute Maximum Ratings Parameter Minimum Maximum Unit Input Supply Voltage, VIN Pin -0.3 +17 V Input Supply Voltage for Controller, VDD Pin -0.3 +17 V MOSFET Switch Node Voltage, SW1/2, SWD1/2 -0.3 +17 V MOSFET Driver Supply Voltage, VDRV, VDRV1 Pin -0.3 +6.0 V Output Voltage, VOUT pin -0.3 +6.0 V Internal Reference Supply Voltage, VR6 Pin -0.3 +6.6 V Internal Reference Supply Voltage, VR, VR5, VR55 Pin -0.3 +6.5 V Internal Reference Supply Voltage, V25 Pin -0.3 +3 V Logic I/O Voltage for EN, CFG, PG, ASCR, VSET_FINE, SA, SCL, SDA, SALRT, SYNC, SS/UVLO, VMON, VSET_CRS -0.3 +6.0 V VSENP -0.3 +6.0 V VSENN -0.3 +0.3 V Analog Input Voltages ESD Rating Value Unit 2 kV Machine Model (Tested per JESD22-A115C) 200 V Charged Device Model (Tested per JS-002-2014) 750 V Latch-Up (Tested per JESD78E; Class 2, Level A) 100 mA Human Body Model (Tested per JS-001-2017) CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty. 2.2 Thermal Information Thermal Resistance (Typical) 58 Ld HDA Package (Notes 11, 12) JA (C/W) JC (C/W) 5.3 1.1 Notes: 11. JA is measured in free air with the module mounted on an 8-layer evaluation board 4.7x4.8inch in size with 2oz Cu on all layers and multiple via interconnects as specified in the RTKA2108502H00000BU evaluation board user guide. 12. For JC, the "case temp" location is the center of the package underside. Parameter Minimum Maximum +125 C -55 +150 C Maximum Junction Temperature (Plastic Package) Storage Temperature Range Pb-Free Reflow Profile 2.3 Unit See Figure 29 on page 31 Recommended Operating Conditions Parameter Minimum Maximum Unit Input Supply Voltage Range, VIN 4.5 14 V Input Supply Voltage Range for Controller, VDD 4.5 14 V Output Voltage Range, VOUT 0.6 5 V FN9346 Rev.1.00 Mar 15, 2019 Page 11 of 58 RAA210850 2. Specifications Parameter Minimum Maximum Unit Output Current Range, IOUT(DC) (Note 15) 0 50 A Operating Junction Temperature Range, TJ -40 +125 C 2.4 Electrical Specifications VIN = VDD= 12V, fSW = 533kHz, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C. Boldface limits apply across the operating temperature range, -40C to +85C. Parameter Symbol Test Conditions Min (Note 13) Typ Max (Note 13) Unit 40 50 mA 5.5 6.1 6.6 V 4.5 5.2 5.5 V 2.25 2.5 2.75 V Input And Supply Characteristics Input Supply Current for Controller IDD 6V Internal Reference Supply Voltage VR6 5V Internal Reference Supply VR5 2.5V Internal Reference Supply V25 Internal LDO Output Voltage Vcc Internal LDO Output Current IVCC Input Supply Voltage for Controller Read Back Resolution VDD_READ_RES Input Supply Voltage for Controller Read Back Total Error (Note 16) VDD_READ_ERR VIN = VDD = 12V, VOUT = 0V, module not enabled IVR5 <5mA 5.3 VIN = VDD = 12V, VCC connected to VDRV, module enabled V 50 PMBus Read mA 20 mV 2 %FS Output Characteristics Output Voltage Adjustment Range VOUT_RANGE VIN > VOUT + 1.8V Output Voltage Set-Point Range VOUT_RES Configured using PMBus Output Voltage Set-Point Accuracy (Note 14, 16) VOUT_ACCY Includes line, load, and temperature (-20C TA +85C) Output Voltage Read Back Resolution VOUT_READ_RES Output Voltage Read Back Total Error (Note 16) VOUT_READ_ERR Output Current Read Back Resolution IOUT_READ_RES Output Current Range (Note 15) IOUT_RANGE Output Current Read back Total Error IOUT_READ_ERR 0.54 5.5 0.025 -1.2 % 1.2 0.15 PMBus read -2 %FS %FS 2 %FS 0.2 A 50 PMBus read at max load. VOUT = 1.5V V A 3 A Soft-Start and Sequencing Delay Time From Enable to VOUT Rise tON_DELAY Accuracy tON_DELAY 2 tON_DELAY_ACCY Output Voltage Ramp-Up Time tON_RISE Output Voltage Ramp-Up Time Accuracy tON_RISE_ACCY FN9346 Rev.1.00 Mar 15, 2019 Configured using pin-strap resistors or PMBus 300 2 Configured using pin-strap resistors or PMBus 0.5 ms 120 250 ms ms s Page 12 of 58 RAA210850 2. Specifications VIN = VDD= 12V, fSW = 533kHz, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C. Boldface limits apply across the operating temperature range, -40C to +85C. (Continued) Parameter Delay Time From Disable to VOUT Fall tOFF_DELAY Accuracy Output Voltage Fall Time Output Voltage Fall Time Accuracy Symbol tOFF_DELAY Test Conditions Configured using pin-strap resistors or PMBus Min (Note 13) 2 tOFF_DELAY_ACCY tOFF_FALL Typ Max (Note 13) Unit 300 ms 2 Configured using pin-strap resistors or PMBus 0.5 ms 120 ms tON_FALL_ACCY 250 s VPG_DELAY 3 ms Power-Good Power-Good Delay Temperature Sense Temperature Sense Range TSENSE_RANGE Configurable using PMBus -50 150 C Internal Temperature Sensor Accuracy INT_TEMPACCY Tested at +100C -5 5 C 4.18 16 V Fault Protection VDD Undervoltage Threshold Range VDD_UVLO_RANGE VDD Undervoltage Threshold Accuracy (Note 16) VDD_UVLO_ACCY 2 %FS VDD Undervoltage Response Time VDD_UVLO_DELAY 10 s VOUT Overvoltage Threshold Range VOUT_OV_RANGE 1.15VOUT V VOUT Undervoltage Threshold Range VOUT_UV_RANGE Measured internally Factory default Configured using PMBus Configured using PMBus VOUT OV/UV Threshold Accuracy (Note 14) VOUT_OV/UV_ACCY VOUT OV/UV Response Time VOUT_OV/UV_DELAY Output Current Limit Set-Point Accuracy (Note 16) ILIMIT_ACCY Tested at IOUT_OC_FAULT_LIMIT = 50A Output Current Fault Response Time (Note 17) ILIMIT_DELAY TJUNCTION Over-Temperature Protection Threshold (Controller Junction Temperature) Thermal Protection Hysteresis FN9346 Rev.1.00 Mar 15, 2019 0.85VOUT V V 0 0.95VOUT V -2 2 % 10 s 10 % FS Factory default 3 tSW Factory default 115 C Configured using PMBus TJUNCTION_HYS VOUT_MAX 1.05VOUT Factory default -40 125 15 C C Page 13 of 58 RAA210850 2. Specifications VIN = VDD= 12V, fSW = 533kHz, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C. Boldface limits apply across the operating temperature range, -40C to +85C. (Continued) Parameter Symbol Test Conditions Min (Note 13) Typ Max (Note 13) Unit Oscillator and Switching Characteristics fSW_RANGE 296 1067 kHz Switching Frequency Set-Point Accuracy fSW_ACCY -5 5 % Minimum Pulse Width Required from External SYNC Clock EXT_SYNCPW Switching Frequency Range Measured at 50% amplitude 150 EXT_SYNCDRIFT External SYNC Clock equal to 500kHz is not supported -10 10 % Bias Current at the Logic Input Pins ILOGIC_BIAS EN, CFG, PG, SA, SCL, SDA, SALRT, SYNC, UVLO, VMON, VSET_CRS -100 100 nA Logic Input Low Threshold Voltage VLOGIC_IN_LOW 0.8 V Logic Input High Threshold Voltage VLOGIC_IN_HIGH Drift Tolerance for External SYNC Clock ns Logic Input/Output Characteristics 2.0 Logic Output Low Threshold Voltage VLOGIC_OUT_LOW 2mA sinking Logic Output High Threshold Voltage VLOGIC_OUT_HIGH 2mA sourcing V 0.5 2.25 V V PMBus Interface Timing Characteristic PMBus Operating Frequency fSMB 100 400 kHz Notes: 13. Compliance to datasheet limits is assured by one or more methods: Production test, characterization and/or design. Controller is independently tested before module assembly. 14. VOUT measured at the termination of the VSENP and VSENN sense points. 15. The MAX load current is determined by the thermal "Derating Curves" on page 17. 16. "FS" stands for full scale of recommended maximum operation range. 17. "tSW" stands for time period of operation switching frequency. FN9346 Rev.1.00 Mar 15, 2019 Page 14 of 58 RAA210850 3. 3. Typical Performance Curves Typical Performance Curves 3.1 Efficiency Performance Operating condition: TA = +25C, no air flow. COUT = 6x470F POSCAP + 12X100F Ceramic. Typical values used unless otherwise noted. 100 95 94 95 93 Efficiency (%) Efficiency (%) 90 85 0.8Vout_296kHz 1Vout_296kHz 80 1.2Vout_296kHz 90 89 87 2.5Vout_296kHz 70 86 0 10 20 30 Load Current (A) 40 50 0.8Vout 1.2Vout 2.5Vout 1Vout 1.8Vout 300 350 400 450 500 550 600 650 700 750 800 850 900 Frequency (kHz) Figure 5. Efficiency vs Output Current at VIN = 5V for Various Output Voltages Figure 6. Efficiency vs Switching Frequency at VIN = 5V, IOUT = 50A for Various Output Voltages 100 98 95 96 94 Efficiency (%) 90 Efficiency (%) 91 88 1.8Vout_296kHz 75 92 85 0.8Vout_296kHz 1Vout_296kHz 1.2Vout_296kHz 1.8Vout_364kHz 2.5Vout_533kHz 3.3Vout_533kHz 5Vout_571kHz 80 75 70 92 90 88 86 0.8Vout 1.2Vout 2.5Vout 84 65 82 0 10 20 30 Load Current (A) 40 50 1Vout 1.8Vout 3.3Vout 300 350 400 450 500 550 600 650 700 750 800 850 900 Frequency (kHz) Figure 7. Efficiency vs Output Current at VIN = 9V for Various Output Voltages Figure 8. Efficiency vs Switching Frequency at VIN = 9V, IOUT = 50A for Various Output Voltages 100 98 96 95 94 Efficiency (%) Efficiency (%) 90 85 0.8Vout_296kHz 1Vout_296kHz 1.2Vout_296kHz 1.8Vout_364kHz 2.5Vout_533kHz 3.3Vout_533kHz 5Vout_571kHz 80 75 70 10 20 30 Load Current (A) 40 88 86 82 50 Figure 9. Efficiency vs Output Current at VIN = 12V for Various Output Voltages FN9346 Rev.1.00 Mar 15, 2019 90 84 65 0 92 80 0.8Vout 1.2Vout 2.5Vout 5Vout 1Vout 1.8Vout 3.3Vout 300 350 400 450 500 550 600 650 700 750 800 850 900 Frequency (kHz) Figure 10. Efficiency vs Switching Frequency at VIN = 12V, IOUT = 50A for Various Output Voltages Page 15 of 58 RAA210850 3.2 3. Typical Performance Curves Transient Response Performance Operating conditions: VIN = 12V, fSW = 533kHz, IOUT = 0A/25A, IOUT slew rate = 15A/s, TA = +25C, no air flow. Typical values are used unless otherwise noted. VOUT = 50mV/Div VOUT = 50mV/Div IOUT = 10A/Div IOUT = 10A/Div 50s/Div 50s/Div Figure 11. 5VIN to 0.8VOUT Transient Response, fSW = 615kHz, COUT = 10x100F Ceramic + 3x470F POSCAP, ACSR Residual = 90, ASCR Gain = 450 Figure 12. 5VIN to 1.2VOUT Transient Response, fSW = 727kHz, COUT = 8x100F Ceramic + 2x470F POSCAP, ACSR Residual = 90, ASCR Gain = 320 VOUT = 100mV/Div VOUT = 50mV/Div IOUT = 10A/Div IOUT = 10A/Div 50s/Div 50s/Div Figure 13. 12VIN to 1.5VOUT Transient Response, fSW = 471kHz, COUT = 6x100F Ceramic + 2x470F POSCAP, ACSR Residual = 90, ASCR Gain = 160 Figure 14. 12VIN to 1.8VOUT Transient Response, fSW = 471kHz, COUT = 12x100F Ceramic + 1x470F POSCAP, ACSR Residual = 100, ASCR Gain = 160 VOUT = 100mV/Div VOUT = 100mV/Div IOUT = 10A/Div IOUT = 10A/Div 50s/Div 50s/Div Figure 15. 12VIN to 2.5VOUT Transient Response, fSW = 533kHz, COUT = 9x100F Ceramic + 1x470F POSCAP, ACSR Residual = 100, ASCR Gain = 160 Figure 16. 12VIN to 5VOUT Transient Response, fSW = 571kHz, COUT = 9x100F Ceramic + 1x470F POSCAP, ACSR Residual = 90, ASCR Gain = 120 FN9346 Rev.1.00 Mar 15, 2019 Page 16 of 58 RAA210850 3.3 3. Typical Performance Curves Derating Curves All of the following curves were plotted at TJ = +120C. 60 60 50 40 200LFM 30 20 400LFM 0LFM Load Current (A) Load Current (A) 50 400LFM 0LFM 10 40 200LFM 30 20 10 0 0 25 35 45 55 65 75 85 95 Ambient Temperature (C) 105 115 125 25 35 45 55 65 75 85 95 Ambient Temperature (C) 105 60 60 400LFM 400LFM 50 40 Load Current (A) 50 Load Current (A) 125 Figure 18. 5VIN to 1VOUT, fSW = 364kHz Figure 17. 12VIN to 1VOUT, fSW = 364kHz 200LFM 30 0LFM 20 40 200LFM 30 20 0LFM 10 10 0 0 25 35 45 55 65 75 85 95 Ambient Temperature (C) 105 115 25 125 35 45 55 65 75 85 95 Ambient Temperature (C) 105 115 125 Figure 20. 5VIN to 1.5VOUT, fSW = 471kHz Figure 19. 12VIN to 1.5VOUT, fSW = 471kHz 60 60 50 50 400LFM Load Current (A) Load Current (A) 115 40 200LFM 30 20 0LFM 400LFM 40 200LFM 30 0LFM 20 10 10 0 0 25 35 45 55 65 75 85 95 Ambient Temperature (C) 105 115 Figure 21. 12VIN to 1.8VOUT, fSW = 727kHz FN9346 Rev.1.00 Mar 15, 2019 125 25 35 45 55 65 75 85 95 Ambient Temperature (C) 105 115 125 Figure 22. 5VIN to 1.8VOUT, fSW = 727kHz Page 17 of 58 RAA210850 3. Typical Performance Curves All of the following curves were plotted at TJ = +120C. (Continued) 60 60 50 400LFM Load Current (A) Load Current (A) 50 40 30 200LFM 20 0LFM 10 400LFM 40 200LFM 30 0LFM 20 10 0 0 25 35 45 55 65 75 85 95 Ambient Temperature (C) 105 115 125 25 60 60 50 50 40 400LFM 30 200LFM 20 10 0 35 45 55 65 75 85 95 Ambient Temperature & 105 115 Figure 25. 12VIN to 3.3VOUT, fSW = 533kHz FN9346 Rev.1.00 Mar 15, 2019 55 65 75 85 95 Ambient Temperature (C) 105 115 125 40 400LFM 30 200LFM 20 0LFM 10 0LFM 25 45 Figure 24. 5VIN to 2.5VOUT, fSW = 533kHz Load Current (A) Load Current (A) Figure 23. 12VIN to 2.5VOUT, fSW = 533kHz 35 0 25 35 45 55 65 75 85 95 Ambient Temperature (C) 105 115 125 Figure 26. 12VIN to 5VOUT, fSW = 571kHz Page 18 of 58 RAA210850 4. 4. Functional Description Functional Description 4.1 SMBus Communications The RAA210850 provides a SMBus digital interface that enables configuration of the module and monitors the input and output parameters. The RAA210850 can be used with any SMBus host device. The module is compatible with PMBus Power System Management Protocol Specification Parts I and II version 1.2. The RAA210850 accepts most standard PMBus commands. Renesas recommends tying the enable pin to SGND when PMBus commands are issued. The SMBus device address is the only parameter that must be set by external pins. 4.2 Output Voltage Selection The output voltage can be set to a voltage between 0.6V and 5V if the input voltage is higher than the desired output voltage by an amount sufficient to maintain regulation. The VSET_CRS (VOUT Coarse) and VSET_FINE (VOUT Fine) pins set the output voltage. A resistor placed between the VSET_CRS pin and SGND programs the VOUT_CRS (VOUT Coarse) voltage according to the levels shown in Table 5. A standard 1% resistor is required. Table 5. Output Voltage (Coarse) Resistor Settings FN9346 Rev.1.00 Mar 15, 2019 VOUT_CRS (V) RSET (k) 0.600 10 0.675 11 0.700 12.1 0.720 13.3 0.750 14.7 0.800 16.2 0.850 17.8 0.900 19.6 0.930 21.5 0.950 23.7 0.980 26.1 1.000 Connect to SGND 1.030 28.7 1.050 31.6 1.100 34.8 1.120 38.3 1.150 42.2 1.200 OPEN 1.250 46.4 1.300 51.1 1.350 56.2 1.400 61.9 1.500 68.1 1.650 75 1.800 82.5 1.850 90.9 Page 19 of 58 RAA210850 4. Functional Description Table 5. Output Voltage (Coarse) Resistor Settings VOUT_CRS (V) RSET (k) 2.000 100 2.400 110 2.500 Connect to V25 2.800 121 3.000 133 3.300 147 3.600 162 5.000 178 If higher resolution is desired, the VSET_FINE pin can be used to fine-tune the output voltage settings according to the command set below: VOUT_CRS + 5mV * N, if 0.6V VOUT_CRS 1.4V VOUT_CRS + 10mV * N, if 1.5V VOUT_CRS 1.85V VOUT_CRS + 50 mV * N, if 2V VOUT_CRS 3.3V Output voltage = VOUT_CRS + 100 mV * N, if 3.6V VOUT_CRS < 5V VOUT_CRS, if VOUT_CRS = 5V Use the resistors values from Table 6 to set the appropriate value of N for calculating the final output voltage. Table 6. VSET_FINE Resistor Settings FN9346 Rev.1.00 Mar 15, 2019 N RSET (k) 0 10, or OPEN 1 11 2 12.1 3 13.3 4 14.7 5 16.2 6 17.8 7 19.6 8 21.5 9 23.7, or connect to SGND 10 26.1 11 28.7 12 31.6 13 34.8 14 38.3 15 42.2 16 46.4 17 51.1 18 56.2 19 61.9 20 68.1, or connect to V25 Page 20 of 58 RAA210850 4. Functional Description The output voltage can be set to any value between 0.6V and 5V using the pin-strap settings provided in Tables 5 and 6. By default, VOUT_MAX is set 110% higher than VOUT set by the pin-strap resistor, which can be changed to any value up to 5.5V with the PMBus command VOUT_MAX. 4.3 Soft-Start/Stop Delay and Ramp Times The RAA210850 follows an internal start-up procedure after power is applied to the VDD pin. The module requires approximately 60ms to 70ms to check for specific values stored in its internal memory and is programmed by pin-strap resistors. When this process is complete, the device is ready to accept commands from the PMBus interface and the module is ready to be enabled. If the module is synchronizing to an external clock source, the clock frequency must be stable before asserting the EN pin. It may be necessary to set a delay from when an enable signal is received until the output voltage starts to ramp to its target value. In addition, the designer may wish to precisely set the time required for VOUT to ramp to its target value after the delay period expires. These features can be used as part of an overall inrush current management strategy or to precisely control how fast a load IC is turned on. The RAA210850 has several options for precisely and independently controlling both the delay and ramp time periods. The soft-start delay period begins when the EN pin is asserted and ends when the delay time expires. The soft-start delay and ramp up time can be programmed to custom values with the PMBus commands TON_DELAY and TON_RISE. When the delay time is set to 0ms, the device begins its ramp-up after the internal circuitry has initialized (approximately 2ms). When the soft-start ramp period is set to 0ms, the output ramps up as quickly as the output load capacitance and loop settings allow. In general, set the soft-start ramp to a value greater than 1ms to prevent inadvertent fault conditions due to excessive in-rush current. Similar to the soft-start delay and ramp up time, the delay and ramp down time for soft-stop/off can be programmed with the PMBus commands TOFF_DELAY and TOFF_FALL. In addition, the module can be configured as "immediate off" with the command ON_OFF_CONFIG, so that the FETs are turned off immediately after the delay time expires. The SS/UVLO pin can program the soft start/stop delay time and ramp time to some typical values as shown in Table 7. A standard 1% resistor is required. Table 7. UVLO and Soft-Start/Stop Resistor Settings Resistor (k) UVLO (V) Delay Time (ms) Ramp Time (ms) 10 4.5 5 2 11 4.5 5 2 12.1 4.5 5 2 13.3 4.5 5 2 14.7 4.5 5 2 16.2 4.5 5 2 17.8 4.5 5 2 19.6 4.5 5 2 21.5 4.5 10 2 23.7 4.5 5 5 26.1 4.5 10 5 28.7 4.5 20 5 31.6 4.5 5 10 34.8 4.5 10 10 38.3 4.5 20 10 42.2 10.8 5 2 FN9346 Rev.1.00 Mar 15, 2019 Page 21 of 58 RAA210850 4. Functional Description Table 7. UVLO and Soft-Start/Stop Resistor Settings (Continued) 4.4 Resistor (k) UVLO (V) Delay Time (ms) Ramp Time (ms) 46.4 10.8 10 2 51.1 10.8 5 5 56.2 10.8 10 5 61.9 10.8 20 5 68.1 10.8 5 10 75 10.8 10 10 82.5 10.8 20 10 Connect to SGND 4.5 5 2 OPEN 4.2 5 5 Connect to V25 4.5 10 10 Input Undervoltage Lockout (UVLO) The input undervoltage lockout (UVLO) prevents the RAA210850 from operating when the input falls below a preset threshold, indicating the input supply is out of its specified range. The UVLO threshold (VUVLO) can be set between 4.18V and 16V by using the PMBus command VIN_UV_FAULT_LIMIT. Use the pin-strap method (SS/UVLO pin) shown in Table 7 to set the VUVLO to three typical values. A standard 1% resistor is required. The module shuts down immediately when it falls below the UVLO threshold. The fault must be cleared before the module can restart. 4.5 Power-Good The RAA210850 provides a Power-Good (PG) signal that indicates the output voltage is within a specified tolerance of its target level and no fault condition exists. By default, the PG pin asserts if the output is within 10% of the target voltage. This limit can be changed using the PMBus command POWER_GOOD_ON. A PG delay period is defined as the time from when all conditions within the RAA210850 for asserting PG are met to when the PG pin is actually asserted. This feature is commonly used instead of using an external reset controller to control external digital logic. A fixed PG delay of 3ms is programmed for the RAA210850. 4.6 Switching Frequency and PLL The device's switching frequency is configurable between 296kHz to 1067kHz using the pin-strap method shown in Table 8, or by using the PMBus command FREQUENCY_SWITCH. Table 8. Switching Frequency Resistor Settings FN9346 Rev.1.00 Mar 15, 2019 fSW (kHz) RSET (k) 296 14.7, or connect to SGND 300 16.2 320 17.8 364 19.6 400 21.5 421 23.7, or OPEN 471 26.1 533 28.7 571 31.6 615 34.8, or connect to V25 Page 22 of 58 RAA210850 4. Functional Description Table 8. Switching Frequency Resistor Settings (Continued) fSW (kHz) RSET (k) 727 38.3 800 42.2 842 46.4 889 51.1 1067 56.2 The RAA210850 incorporates an internal Phase-Locked Loop (PLL) to clock the internal circuitry. The PLL can also be driven by an external clock source connected to the SYNC pin. Set this configuration by connecting a resistor to the CFG pin. If the clock source is internal, the internal frequency is set according to the SYNC pin resistor settings shown in Table 8. If clock source is external, the internal frequency is set according to the resistor connected to the CFG pin as shown in Table 9. The external clock frequency should be within 10% of the listed options. Table 9. External Frequency Sync Settings Clock Source Internal FREQUENCY_SWITCH (kHz) RSET (k) Internal Determined by SYNC resistor 10, or OPEN External 296 11 External 340 12.1 External 390 13.3 External 444 14.7 External 516 16.2, or connect to SGND External 593 17.8 External 696 19.6 External 800 21.5 External 941 23.7 External 1067 26.1, or connect to V25 The incoming clock signal must be stable when the enable pin is asserted. The external clock signal must not vary more than 10% from its initial value and should have a minimum pulse width of 150ns. A standard 1% resistor is required. 4.7 Loop Compensation The module loop response is programmable using the pin-strap method or by using the PMBus command ASCR_CONFIG according to Table 10. A standard 1% resistor is required. The RAA210850 uses the ChargeMode control algorithm that responds to output current changes within a single PWM switching cycle, achieving a smaller total output voltage variation with less output capacitance than traditional PWM controllers. Table 10. ASCR Resistor Settings ASCR Gain FN9346 Rev.1.00 Mar 15, 2019 ASCR Residual RSET (k) 80 90 10 100 90 11 110 90 12.1 120 90 Connect to SGND 160 90 13.3 Page 23 of 58 RAA210850 4. Functional Description Table 10. ASCR Resistor Settings (Continued) 4.8 ASCR Gain ASCR Residual RSET (k) 200 90 OPEN 220 90 14.7 230 90 16.2 250 90 17.8 280 90 19.6 320 90 21.5 360 90 23.7 400 90 26.1 450 90 28.7 500 90 31.6 550 90 34.8 600 90 38.3 700 90 42.2 800 90 46.4 80 100 51.1 120 100 56.2 160 100 61.9 200 100 68.1 240 100 75 280 100 82.5 320 100 90.9 360 100 100 400 100 110 450 100 121 500 100 Connect to V25 550 100 133 600 100 147 700 100 162 800 100 178 SMBus Module Address Selection Each module must have its own unique serial address to distinguish between other devices on the bus. The module address is set by connecting a resistor between the SA pin and SGND. Table 11 lists the available module addresses. A standard 1% resistor is required. Table 11. SMBus Address Resistor Selection RSA (k) FN9346 Rev.1.00 Mar 15, 2019 SMBus Address 10 19h 11 1Ah 12.1 1Bh 13.3 1Ch Page 24 of 58 RAA210850 4. Functional Description Table 11. SMBus Address Resistor Selection (Continued) 4.9 RSA (k) SMBus Address 14.7 1Dh 16.2 1Eh 17.8 1Fh 19.6 20h 21.5 21h 23.7 22h 26.1 23h 28.7 24h 31.6 25h 34.8, or connect to SGND 26h 38.3 27h 42.2, or Open 28h 46.4 29h 51.1 2Ah 56.2 2Bh 61.9 2Ch 68.1 2Dh 75 2Eh 82.5 2Fh 90.9 30h 100 31h 110 32h 121 33h 133 34h 147 35h 162 36h 178 37h Output Overvoltage Protection The RAA210850 has an internal output overvoltage protection circuit that can protect sensitive load circuitry from being subjected to a voltage higher than its prescribed limits. A hardware comparator compares the actual output voltage (seen at the VSENP and VSENN pins) to a threshold set to 15% higher than the target output voltage. The fault threshold can be programmed to a desired level with the PMBus command VOUT_OV_FAULT_LIMIT. If the VSENP - VSENN voltage exceeds this threshold, the module initiates an immediate shutdown without retry. Internal to the module, two 100 resistors are populated from VOUT to VSENP and SGND to VSENN to protect from overvoltage conditions in case of open at voltage sensing pins and differential remote sense traces due to assembly error. If the differential remote sense traces have low resistance, VOUT regulation accuracy is not sacrificed. FN9346 Rev.1.00 Mar 15, 2019 Page 25 of 58 RAA210850 4.10 4. Functional Description Output Prebias Protection An output prebias condition exists when an externally applied voltage is present on a power supply's output before the power supply's control IC is enabled. Certain applications require that the converter not be allowed to sink current during start-up if a prebias condition exists at the output. The RAA210850 provides prebias protection by sampling the output voltage before initiating an output ramp. If a prebias voltage lower than the target voltage exists after the preconfigured delay period has expired, the target voltage is set to match the existing prebias voltage and both drivers are enabled. The output voltage is then ramped to the final regulation value at the preconfigured ramp rate. The actual time the output takes to ramp from the prebias voltage to the target voltage varies depending on the prebias voltage; however, the total time elapsed from when the delay period expires to when the output reaches its target value matches the preconfigured ramp time (see Figure 27). 9287 'HVLUHG2XWSXW 9ROWDJH 3UHELDV9ROWDJH 7LPH 721'(/$< 7215,6( 935(%,$697$5*(7 9287 3UHELDV9ROWDJH 'HVLUHG2XWSXW 9ROWDJH 7LPH 721'(/$< 7215,6( 935(%,$6!97$5*(7 Figure 27. Output Responses to Prebias Voltages If a prebias voltage is higher than the target voltage after the preconfigured delay period has expired, the target voltage is set to match the existing prebias voltage and both drivers are enabled with a PWM duty cycle that ideally creates the prebias voltage. When the preconfigured soft-start ramp period expires, the PG pin is asserted (assuming the prebias voltage is not higher than the overvoltage limit). The PWM then adjusts its duty cycle to match the original target voltage and the output ramps down to the preconfigured output voltage. If a prebias voltage is higher than the overvoltage limit, the device does not initiate a turn-on sequence and declares an overvoltage fault condition. FN9346 Rev.1.00 Mar 15, 2019 Page 26 of 58 RAA210850 4.11 4. Functional Description Output Overcurrent Protection The RAA210850 can protect the power supply from damage if the output is shorted to ground or if an overload condition is imposed on the output. Average output overcurrent fault threshold can be programmed with the PMBus command IOUT_OC_FAULT_LIMIT. The module automatically programs the peak inductor current fault threshold by calculating the inductor ripple current from the input voltage, switching frequency, and the VOUT_COMMAND. The response from an overcurrent fault is an immediate shutdown with 70ms retry. 4.12 Thermal Overload Protection The RAA210850 includes a thermal sensor that continuously measures the internal temperature of the module and shuts down the controller when the temperature exceeds the preset limit. The default temperature limit is set to +115C in the factory, but can be changed with PMBus command OT_FAULT_LIMIT. The response from an over-temperature fault is an immediate shutdown without retry. 4.13 Phase Spreading When multiple point-of-load converters share a common DC input supply, adjust the clock phase offset of each device so that not all devices start to switch simultaneously. Setting each converter to start its switching cycle at a different point in time can dramatically reduce input capacitance requirements and efficiency losses. Because the peak current drawn from the input supply is effectively spread out over a period of time, the peak current drawn at any given moment is reduced and the power losses proportional to the IRMS2 are reduced dramatically. To enable phase spreading, all converters must be synchronized to the same switching clock. The phase offset between devices will be determined from the lower 4 bits of the SMBus address of each interleaved device. The phase offset of each device can be set to any value between 0 and 360 in 22.5 increments. The internal two phase of the module always maintain a phase difference of 180. This functionality can also be accessed using the PMBus command INTERLEAVE. Table 12. Interleave SMBus Address SMBus Address in Binary Low 4-Bits INTERLEAVE Phase Shift in Rail ID 19h 00011001 1001 9 202.5 25 1Ah 00011010 1010 10 225 26 1Bh 00011011 1011 11 247.5 27 1Ch 00011100 1100 12 270 28 1Dh 00011101 1101 13 292.5 29 1Eh 00011110 1110 14 315 30 1Fh 00011111 1111 15 337.5 31 20h 00100000 0000 0 0 0 21h 00100001 0001 1 22.5 1 22h 00100010 0010 2 45 2 23h 00100011 0011 3 67.5 3 24h 00100100 0100 4 90 4 25h 00100101 0101 5 112.5 5 26h 00100110 0110 6 135 6 27h 00100111 0111 7 157.5 7 28h 00101000 1000 8 180 8 29h 00101001 1001 9 202.5 9 FN9346 Rev.1.00 Mar 15, 2019 Page 27 of 58 RAA210850 4. Functional Description Table 12. Interleave (Continued) SMBus Address SMBus Address in Binary Low 4-Bits INTERLEAVE Phase Shift in Rail ID 2Ah 00101010 1010 10 225 10 2Bh 00101011 1011 11 247.5 11 2Ch 00101100 1100 12 270 12 2Dh 00101101 1101 13 292.5 13 2Eh 00101110 1110 14 315 14 2Fh 00101111 1111 15 337.5 15 30h 00110000 0000 0 0 16 31h 00110001 0001 1 22.5 17 32h 00110010 0010 2 45 18 33h 00110011 0011 3 67.5 19 34h 00110100 0100 4 90 20 35h 00110101 0101 5 112.5 21 36h 00110110 0110 6 135 22 37h 00110111 0111 7 157.5 23 4.14 Monitoring with SMBus The RAA210850 can monitor a wide variety of system parameters with the following PMBus commands: * READ_VIN * READ_VOUT * READ_IOUT * READ_INTERNAL_TEMP * READ_DUTY_CYCLE * READ_FREQUENCY * READ_VMON 4.15 Snapshot Parameter Capture The RAA210850's snapshot feature captures parametric data and some fault status following a fault. A detailed description is provided in the "SNAPSHOT (EAh)" and "SNAPSHOT_CONTROL (F3h)" sections of "PMBus Commands Description" on page 35. FN9346 Rev.1.00 Mar 15, 2019 Page 28 of 58 RAA210850 5. 5. Layout Guidelines Layout Guidelines To achieve stable operation, low losses, and good thermal performance, proper layout (Figure 28) is important. * Establish separate SGND plane and PGND planes, then connect SGND to the PGND plane on the middle layer and underneath PAD6 with a single point connection. For SGND and PGND pin connections, such as small pins H16, J16, M5, and M17..., use multiple vias for each pin to connect to the inner SGND or PGND layer. * Place enough ceramic capacitors between VIN and PGND, VOUT and PGND, and bypass capacitors between VDD, VDRV, and the ground plane, as close to the module as possible to minimize high frequency noise. It is critical to place the output ceramic capacitors as close to the center of the two VOUT pads as possible, to create a low impedance path for the high frequency inductor ripple current. * Use large copper areas for power path (VIN, PGND, VOUT) to minimize conduction loss and thermal stress. Also, use multiple vias to connect the power planes in different layers. Renesas recommends enlarging PAD11 and PAD15 and placing more vias on these pads. The ceramic caps CIN can be put on the bottom layer under these two pads. * Connect remote sensed traces to the regulation points to achieve a tight output voltage regulation and keep them in parallel. Route a trace from VSENN and VSENP to the point of load where the tight output voltage is desired. Avoid routing any sensitive signal traces, such as the VSENN, VSENP sensing point near the SW pins. * The SW1 and SW2 pads are noisy pads, but they are beneficial for thermal dissipation. If the noise issue is critical for the application, Renesas recommends using the top layer only for SW pads. For better thermal performance, use multiple vias on these pads to connect into SW inner and bottom layer. However, be very careful when placing limited SW planes in any layer. The SW planes should avoid the sensing signals and should be surrounded by the PGND layer to avoid noise coupling. * For pins SWD1 (L3) and SWD2 (P10), it is recommended to connect to the related SW1 and SW2 pads with short loop wires. The wire width should be greater than 20 mils. COUT VOUT COUT PGND PGND SGND PGND PGND VSEN- VSEN+ Kelvin Connections VIN VIN CIN CIN PGND Figure 28. Recommended Layout FN9346 Rev.1.00 Mar 15, 2019 Page 29 of 58 RAA210850 5.1 5. Layout Guidelines Thermal Considerations Experimental power loss curves along with JA from thermal modeling analysis can be used to evaluate the thermal consideration for the module. The derating curves are derived from the maximum power allowed while maintaining the temperature below the maximum junction temperature of +125C. In actual applications, other heat sources and design margins should be considered. 5.2 Package Description The RAA210850 uses the High Density Array No-lead package (HDA). This package offers good thermal and electrical conductivity, low weight, and small size. The HDA package is applicable for surface mounting technology and is being more readily used in the industry. The RAA210850 contains several types of devices, including resistors, capacitors, inductors, and control ICs. The RAA210850 is a copper lead-frame based package with exposed copper thermal pads, which have good electrical and thermal conductivity. The copper lead frame and multi component assembly is overmolded with polymer mold compound to protect these devices. The package outline and typical PCB layout pattern design and typical stencil pattern design are shown in the "Package Outline Drawing" starting on page 51. The module has a small size of 18mmx23mmx7.5mm. 5.3 PCB Layout Pattern Design The bottom of the RAA210850 is a lead-frame footprint, which is attached to the PCB by a surface mounting process. The PCB layout pattern is shown on pages 55 to 57. The PCB layout pattern is an array of solder mask defined PCB lands which align with the perimeters of the HDA exposed pads and I/O termination dimensions. The thermal lands on the PCB layout also feature an array of solder mask defined lands and should match 1:1 with the package exposed die pad perimeters. The exposed solder mask defined PCB land area should be 50-80% of the available module I/O area. 5.4 Thermal Vias A grid of 1.0mm to 1.2mm pitch thermal vias, which drops down and connects to buried copper plane(s), should be placed under the thermal land. The vias should be about 0.3mm to 0.33mm in diameter with the barrel plated to about 1.0 ounce copper. Although adding more vias (by decreasing via pitch) improves the thermal performance, diminishing returns are seen as the number of vias increases. Use as many vias as practical for the thermal land size and your board design rules allow. 5.5 Stencil Pattern Design Reflowed solder joints on the perimeter I/O lands should have about a 50m to 75m (2mil to 3mil) standoff height. The solder paste stencil design is the first step in developing optimized, reliable solder joints. The stencil aperture size to solder mask defined PCB land size ratio should typically be 1:1. The aperture width can be reduced slightly to help prevent solder bridging between adjacent I/O lands. A typical solder stencil pattern is shown in the "Package Outline Drawing" starting on page 51. The gap width between pad to pad is 0.6mm. Consider the symmetry of the whole stencil pattern when designing its pads. A laser cut, stainless steel stencil with electropolished trapezoidal walls is recommended. Electropolishing "smooths" the aperture walls, resulting in reduced surface friction and better paste release which reduces voids. Using a Trapezoidal Section Aperture (TSA) also promotes paste release and forms a brick-like paste deposit that assists in firm component placement. A 0.1mm to 0.15mm stencil thickness is recommended for this large pitch HDA. 5.6 Reflow Parameters Due to the HDA's low mount height, "No Clean" Type 3 solder paste per ANSI/J-STD-005 is recommended. Nitrogen purge is recommended during reflow. A system board reflow profile depends on the thermal mass of the entire populated board, so it is not practical to define a specific soldering profile just for the HDA. The profile in Figure 29 is a guideline to be customized for varying manufacturing practices and applications. FN9346 Rev.1.00 Mar 15, 2019 Page 30 of 58 RAA210850 5. Layout Guidelines 300 Peak Temperature ~+245C; Typically 60s-150s Above +217C Keep Less Than 30s Within 5C of Peak Temp. Temperature (C) 250 200 Slow Ramp (3C/s MAX) and Soak from +150C to +200C for 60s~180s 150 100 Ramp Rate 1.5C from +70C to +90C 50 0 0 100 150 200 250 300 350 Duration (s) Figure 29. Typical Reflow Profile FN9346 Rev.1.00 Mar 15, 2019 Page 31 of 58 RAA210850 6. 6. PMBus Command Summary PMBus Command Summary Command Code Command Name Description Type Data Format 01h OPERATION Sets the Enable and Disable settings. R/W Byte Bit 02h ON_OFF_CONFIG Configures the EN pin and PMBus commands to turn the unit ON/OFF R/W Byte Bit 03h CLEAR_FAULTS Clears fault indications. Send Byte 21h VOUT_COMMAND Sets the nominal value of the output voltage. R/W Word 24h VOUT_MAX Sets the maximum possible value of VOUT. 110% of pin-strap VOUT. 33h FREQUENCY_SWITCH 37h Default Value Default Setting Page 35 Hardware Enable, Soft Off 35 L16u VOUT Pin-Strap (set based on VSET_CRS and VSET_FINE) 36 R/W Word L16u 1.1 x VOUT Pin-Strap 36 Sets the switching frequency. R/W Word L11 Pin-Strap 36 INTERLEAVE Configures a phase offset between devices sharing a SYNC clock. R/W Word Bit 40h VOUT_OV_FAULT_LIMIT Sets the VOUT overvoltage fault threshold. R/W Word L16u 1.15 x VOUT Pin-Strap 37 44h VOUT_UV_FAULT_LIMIT Sets the VOUT undervoltage fault threshold. R/W Word L16u 0.85 x VOUT Pin-Strap 37 46h IOUT_OC_FAULT_LIMIT Sets the IOUT average overcurrent fault threshold. R/W Word L11 E3C0h 60A 37 4Bh IOUT_UC_FAULT_LIMIT Sets the IOUT average undercurrent fault threshold. R/W Word L11 E440h -60A 38 4Fh OT_FAULT_LIMIT Sets the over-temperature fault threshold. R/W Word L11 EB98h +115C 38 53h UT_FAULT_LIMIT Sets the under-temperature fault threshold. R/W Word L11 E530h -45C 38 55h VIN_OV_FAULT_LIMIT Sets the VIN overvoltage fault threshold. R/W Word L11 D3A0h 14.5V 38 59h VIN_UV_FAULT_LIMIT Sets the VIN undervoltage fault threshold. R/W Word L11 Pin-Strap 39 5Eh POWER_GOOD_ON Sets the voltage threshold for Power-Good indication. R/W Word L16u 0.9 x VOUT Pin-Strap 39 60h TON_DELAY Sets the delay time from ENABLE to start of VOUT rise. R/W Word L11 Pin-Strap 39 61h TON_RISE Sets the rise time of VOUT after ENABLE and TON_DELAY. R/W Word L11 Pin-Strap 39 64h TOFF_DELAY Sets the delay time from DISABLE to start of VOUT fall. R/W Word L11 Pin-Strap 40 65h TOFF_FALL Sets the fall time for VOUT after DISABLE and TOFF_DELAY. R/W Word L11 Pin-Strap 40 FN9346 Rev.1.00 Mar 15, 2019 16h 35 37 Pin-Strap (set based on SMBus address) Page 32 of 58 RAA210850 Command Code 6. PMBus Command Summary Command Name Description Type Data Format Default Value Default Setting Page Read Byte Bit 00h No Faults 40 78h STATUS_BYTE Returns an abbreviated status for fast reads. 79h STATUS_WORD Returns information with a summary of the unit's fault condition. Read Word Bit 0000h No Faults 41 7Ah STATUS_VOUT Returns the VOUT specific status. Read Byte Bit 00h No Faults 42 7Bh STATUS_IOUT Returns the IOUT specific status. Read Byte Bit 00h No Faults 42 7Ch STATUS_INPUT Returns specific status specific to the input. Read Byte Bit 00h No Faults 43 7Dh STATUS_TEMPERATURE Returns the temperature specific status. Read Byte Bit 00h No Faults 43 7Eh STATUS_CML Returns the Communication, Logic, and Memory specific status. Read Byte Bit 00h No Faults 44 80h STATUS_MFR_SPECIFIC Returns the VMON and External Sync clock specific status. Read Byte Bit 00h No Faults 44 88h READ_VIN Returns the input voltage reading. Read Word L11 44 8Bh READ_VOUT Returns the output voltage reading. Read Word L16u 45 8Ch READ_IOUT Returns the output current reading. Read Word L11 45 8Dh READ_INTERNAL_TEMP Returns the temperature reading internal to the device. Read Word L11 45 94h READ_DUTY_CYCLE Returns the duty cycle reading during the ENABLE state. Read Word L11 45 95h READ_FREQUENCY Returns the measured operating switch frequency. Read Word L11 45 96h READ_IOUT_0 Returns phase 1 current reading. Read Word L11 45 97h READ_IOUT_1 Returns phase 2 current reading. Read Word L11 46 DFh ASCR_CONFIG Configures ASCR control loop. R/W Block CUS Pin-Strap 46 E4h DEVICE_ID Returns the 16-byte (character) device identifier string. Read Block ASC Reads Device Version 46 E5h MFR_IOUT_OC_FAULT_ RESPONSE Configures the IOUT overcurrent fault response. R/W Byte Bit B9h Disable and 70ms Continuous Retry 47 E6h MFR_IOUT_UC_FAULT_ RESPONSE Configures the IOUT undercurrent fault response. R/W Byte Bit B9h Disable and 70ms Continuous Retry 47 FN9346 Rev.1.00 Mar 15, 2019 Page 33 of 58 RAA210850 6. PMBus Command Summary Command Code Command Name Description Data Format Default Value Default Setting Page Read Block Bit 48 R/W Byte Bit 48 Returns the VMON overvoltage threshold. Read Word L11 CB00h 6V 49 MFR_VMON_UV_FAULT_ LIMIT Returns the VMON undervoltage threshold. Read Word L11 CA00h 4V 49 MFR_READ_VMON Returns the VMON voltage reading. Read Word L11 EAh SNAPSHOT Returns 32-byte read-back of parametric and status values. F3h SNAPSHOT_CONTROL Snapshot feature control command. F5h MFR_VMON_OV_FAULT_ LIMIT F6h F7h 6.1 Type 49 PMBus Data Formats * Linear-11 (L11) - The L11 data format uses 5-bit two's complement exponent (N) and 11-bit two's complement mantissa (Y) to represent real world decimal value (X). The relation between real world decimal value (X), N and Y is: X = Y*2N. Data Byte High Data Byte Low 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Exponent (N) Mantissa (Y) * Linear-16 Unsigned (L16u) - The L16u data format uses a fixed exponent (hard-coded to N = -13h) and a 16-bit unsigned integer mantissa (Y) to represent the real world decimal value (X). The relation between the real world decimal value (X), N and Y is: X = Y*2-13. * Linear-16 Signed (L16s) - The L16s data format uses a fixed exponent (hard-coded to N = -13h) and a 16-bit two's complement mantissa (Y) to represent the real world decimal value (X). The relation between the real world decimal value (X), N and Y is: X = Y*2-13. * Bit Field (BIT) - An explanation of the Bit Field is provided in "PMBus Commands Description" on page 35. * Custom (CUS) - An explanation of the Custom data format is provided in "PMBus Commands Description" on page 35. A combination of Bit Field and integer are common type of Custom data format. * ASCII (ASC) - A variable length string of text characters that uses the ASCII data format. 6.2 PMBus Use Guidelines The PMBus is a powerful tool that allows the user to optimize circuit performance by configuring devices for their application. When configuring a device in a circuit, the device should be disabled whenever most settings are changed with PMBus commands. Some exceptions to this recommendation are OPERATION, ON_OFF_CONFIG, CLEAR_FAULTS, VOUT_COMMAND, and ASCR_CONFIG. While the device is enabled any command can be read. Many commands do not take effect until after the device has been re-enabled, hence the recommendation that commands that change device settings are written while the device is disabled. In addition, there should be a 2ms delay between repeated READ commands sent to the same device. When sending any other command, a 5ms delay is recommended between repeated commands sent to the same device. Commands not listed in the PMBus command summary are not allowed for customer use, and are reserved for factory use only. Issuing reserved commands may result in unexpected operation. FN9346 Rev.1.00 Mar 15, 2019 Page 34 of 58 RAA210850 7. 7. PMBus Commands Description PMBus Commands Description OPERATION (01h) Definition: Sets the Enable and Disable settings. Data Length in Bytes: 1 Data Format: BIT Type: R/W Default Value: Units: N/A Settings Actions 00h Immediate off 40h Soft off 80h On ON_OFF_CONFIG (02h) Definition: Configures the interpretation and coordination of the OPERATION command and the ENABLE pin (EN). Data Length in Bytes: 1 Data Format: BIT Type: R/W Default Value: 16h (Device starts from ENABLE pin with soft off) Units: N/A Settings Actions 16h Device starts from ENABLE pin with soft off. 17h Device starts from ENABLE pin with immediate off. 1Ah Device starts from OPERATION command with soft off. 1Bh Device starts from OPERATION command with immediate off. CLEAR_FAULTS (03h) Definition: Clears all fault bits in all registers and releases the SALRT pin (if asserted) simultaneously. If a fault condition still exists, the bit reasserts immediately. This command does not restart a device if it has shut down, it will clears the faults. Data Length in Bytes: 0 Byte Data Format: N/A Type: Write only Default Value: N/A Units: N/A Reference: N/A FN9346 Rev.1.00 Mar 15, 2019 Page 35 of 58 RAA210850 7. PMBus Commands Description VOUT_COMMAND (21h) Definition: Sets or reports the target output voltage. This command cannot set a value higher than either VOUT_MAX or 110% of the pin-strap VOUT setting. Data Length in Bytes: 2 Data Format: L16u Type: R/W Default Value: Pin-strap setting (set based on VSET_CRS and VSET_FINE) Units: Volts Range: 0V to VOUT_MAX VOUT_MAX (24h) Definition: Sets an upper limit on the output voltage the unit can command regardless of any other commands or combinations. The intent of this command is to provide a safeguard against a user accidentally setting the output voltage to a possibly destructive level rather than to be the primary output overprotection. The default value can be changed using PMBus. Data Length in Bytes: 2 Data Format: L16u Type: R/W Default Value: 1.10 x VOUT pin-strap setting Units: Volts Range: 0V to 5.5V FREQUENCY_SWITCH (33h) Definition: Sets the switching frequency of the device. The initial default value is defined by a pin-strap and this value can be overridden by writing this command using PMBus. The output must be disabled when writing this command. Data Length in Bytes: 2 Data Format: L11 Type: R/W Default Value: Pin-strap setting Units: kHz Range: 296kHz to 1067kHz FN9346 Rev.1.00 Mar 15, 2019 Page 36 of 58 RAA210850 7. PMBus Commands Description INTERLEAVE (37h) Definition: Configures the phase offset of a device that is sharing a common SYNC clock with other devices. The phase offset of each device can be set to any value between 0 and 360 in 22.5 increments. The internal two phases of the module always maintain a phase difference of 180. Data Length in Bytes: 2 Data Format: BIT Type: R/W Default Value: Pin-strap (set based on SMBus address) Units: N/A Bits Purpose Value 15:8 Reserved 0 Description 7:4 Group Number 0 to 15 Sets the group number. A value of 0 is interpreted as 16. 3:0 Position in Group 0 to 15 Sets position of the device's rail within the group. These bits are reserved. VOUT_OV_FAULT_LIMIT (40h) Definition: Sets the VOUT overvoltage fault threshold. Data Length in Bytes: 2 Data Format: L16u Type: R/W Default Value: 1.15 x VOUT pin-strap setting Units: V Range: 0V to VOUT_MAX VOUT_UV_FAULT_LIMIT (44h) Definition: Sets the VOUT undervoltage fault threshold. This fault is masked during ramp or when disabled. Data Length in Bytes: 2 Data Format: L16u Type: R/W Default Value: 0.85xVOUT pin-strap setting Units: V Range: 0V to VOUT_MAX IOUT_OC_FAULT_LIMIT (46h) Definition: Sets the IOUT average overcurrent fault threshold. The device automatically calculates the peak inductor overcurrent fault limit for each phase based on the equation: IOUT(PEAK OC LIMIT) = (0.5 * IOUT_OC_FAULT_LIMIT + 0.5 * IRIPPLE(P-P)) * 120%. A hard bound of 42A is applied to the peak overcurrent fault limit per phase. Data Length in Bytes: 2 Data Format: L11 Type: R/W Default Value: E3C0h (60A) Units: A Range: -100A to 100A FN9346 Rev.1.00 Mar 15, 2019 Page 37 of 58 RAA210850 7. PMBus Commands Description IOUT_UC_FAULT_LIMIT (4Bh) Definition: Sets the IOUT average undercurrent fault threshold. The device automatically calculates the valley inductor undercurrent fault limit for each phase based on the equation: IOUT(VALLEY UC LIMIT) = (0.5 * IOUT_UC_FAULT_LIMIT - 0.5 * IRIPPLE(P-P)) * 120%. A hard bound of -42A is applied to the valley undercurrent fault limit per phase. Data Length in Bytes: 2 Data Format: L11 Type: R/W Default Value: -60A Units: A Range: -100A to 100A OT_FAULT_LIMIT (4Fh) Definition: Sets the temperature at which the device should indicate an over-temperature fault. Note that the temperature must drop below the fault limit to clear this fault. Data Length in Bytes: 2 Data Format: L11 Type: R/W Default Value: EB98h (+115C) Units: Celsius Range: 0C to +150C UT_FAULT_LIMIT (53h) Definition: Sets the temperature, in degrees Celsius, of the unit where it should indicate an under-temperature fault. Data Length in Bytes: 2 Data Format: L11 Type: R/W Default Value: E530h (-45C) Units: Celsius Range: -55C to +25C VIN_OV_FAULT_LIMIT (55h) Definition: Sets the VIN overvoltage fault threshold. Data Length in Bytes: 2 Data Format: L11 Type: R/W Default Value: D3A0h (14.5V) Units: V Range: 0V to 16V FN9346 Rev.1.00 Mar 15, 2019 Page 38 of 58 RAA210850 7. PMBus Commands Description VIN_UV_FAULT_LIMIT (59h) Definition: Sets the VIN undervoltage fault threshold. Data Length in Bytes: 2 Data Format: L11 Type: R/W Default Value: Pin-strap setting Units: V Range: 0V to 12V POWER_GOOD_ON (5Eh) Definition: Sets the voltage threshold for Power-good indication. Power-good asserts after the output voltage exceeds POWER_GOOD_ON. Renesas recommends setting POWER_GOOD_ON higher than VOUT_UV_FAULT_LIMIT. Data Length in Bytes: 2 Data Format: L16u Type: R/W Default Value: 0.9 x VOUT pin-strap setting Units: V TON_DELAY (60h) Definition: Sets the delay time from when the device is enabled to the start of VOUT rise. Data Length in Bytes: 2 Data Format: L11 Type: R/W Default Value: Pin-strap setting Units: ms Range: 2 to 300ms TON_RISE (61h) Definition: Sets the rise time of VOUT after ENABLE and TON_DELAY. Data Length in Bytes: 2 Data Format: L11 Type: R/W Default Value: Pin-strap setting Units: ms Range: 0 to 120ms FN9346 Rev.1.00 Mar 15, 2019 Page 39 of 58 RAA210850 7. PMBus Commands Description TOFF_DELAY (64h) Definition: Sets the delay time from DISABLE to the start of VOUT fall. Data Length in Bytes: 2 Data Format: L11 Type: R/W Default Value: Pin-strap setting Units: ms Range: 2 to 300ms TOFF_FALL (65h) Definition: Sets the soft-off fall time for VOUT after DISABLE and TOFF_DELAY. Data Length in Bytes: 2 Data Format: L11 Type: R/W Default Value: Pin-strap setting Units: ms Range: 0 to 120ms STATUS_BYTE (78h) Definition: Returns one byte of information with a summary of the most critical faults. Data Length in Bytes: 1 Data Format: BIT Type: Read-only Default Value: 00h Units: N/A Bit Number Status Bit Name Meaning 7 BUSY A fault was declared because the device was busy and unable to respond. 6 OFF This bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being enabled. 5 VOUT_OV_FAULT An output overvoltage fault has occurred. 4 IOUT_OC_FAULT An output overcurrent fault has occurred. 3 VIN_UV_FAULT An input undervoltage fault has occurred. 2 TEMPERATURE A temperature fault has occurred. 1 CML 0 None of the Above FN9346 Rev.1.00 Mar 15, 2019 A communications, memory or logic fault has occurred. A fault not listed in Bits 7:1 has occurred. Page 40 of 58 RAA210850 7. PMBus Commands Description STATUS_WORD (79h) Definition: Returns two bytes of information with a summary of the unit's fault condition. Based on the information in these bytes, the host can get more information by reading the appropriate status registers. The low byte of the STATUS_WORD is the same register as the STATUS_BYTE (78h) command. Data Length in Bytes: 2 Data Format: BIT Type: Read-only Default Value: 0000h Units: N/A Bit Number Status Bit Name 15 VOUT 14 IOUT/POUT 13 INPUT Meaning An output voltage fault has occurred. An output current or output power fault has occurred. An input voltage, input current, or input power fault has occurred. 12 MFG_SPECIFIC A manufacturer specific fault has occurred. 11 POWER_GOOD# The POWER_GOOD signal, if present, is negated. 10 Reserved 9 OTHER This bit is reserved. A bit in STATUS_OTHER is set. 8 UNKNOWN 7 BUSY 6 OFF 5 VOUT_OV_FAULT An output overvoltage fault has occurred. 4 IOUT_OC_FAULT An output overcurrent fault has occurred. 3 VIN_UV_FAULT An input undervoltage fault has occurred. 2 TEMPERATURE A temperature fault has occurred. 1 CML 0 None of the Above FN9346 Rev.1.00 Mar 15, 2019 A fault type not given in bits 15:1 of the STATUS_WORD has been detected. A fault was declared because the device was busy and unable to respond. This bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being enabled. A communications, memory, or logic fault has occurred. A fault not listed in Bits 7:1 has occurred. Page 41 of 58 RAA210850 7. PMBus Commands Description STATUS_VOUT (7Ah) Definition: Returns one data byte with the status of the output voltage. Data Length in Bytes: 1 Data Format: BIT Type: Read-only Default Value: 00h Units: N/A Bit Number Status Bit Name 7 VOUT_OV_FAULT 6:5 Reserved 4 VOUT_UV_FAULT 3:0 N/A Meaning Indicates an output overvoltage fault. These bits are reserved. Indicates an output undervoltage fault. These bits are not used. STATUS_IOUT (7Bh) Definition: Returns one data byte with the status of the output current. Data Length in Bytes: 1 Data Format: BIT Type: Read-only Default Value: 00h Units: N/A Bit Number Status Bit Name 7 IOUT_OC_FAULT 6:5 Reserved 4 IOUT_UC_FAULT 3:0 N/A FN9346 Rev.1.00 Mar 15, 2019 Meaning An output overcurrent fault has occurred. These bits are reserved. An output undercurrent fault has occurred. These bits are not used. Page 42 of 58 RAA210850 7. PMBus Commands Description STATUS_INPUT (7Ch) Definition: Returns input voltage and input current status information. Data Length in Bytes: 1 Data Format: BIT Type: Read-only Default Value: 00h Units: N/A Bit Number Status Bit Name 7 VIN_OV_FAULT 6:5 Reserved 4 VIN_UV_FAULT 3:0 N/A Meaning An input overvoltage fault has occurred. These bits are reserved. An input undervoltage fault has occurred. These bits are not used. STATUS_TEMPERATURE (7Dh) Definition: Returns one byte of information with a summary of any temperature related faults. Data Length in Bytes: 1 Data Format: BIT Type: Read-only Default Value: 00h Units: N/A Bit Number Status Bit Name 7 OT_FAULT 6:5 Reserved 4 UT_FAULT 3:0 N/A FN9346 Rev.1.00 Mar 15, 2019 Meaning An over-temperature fault has occurred. These bits are reserved. An under-temperature fault has occurred. These bits are not used. Page 43 of 58 RAA210850 7. PMBus Commands Description STATUS_CML (7Eh) Definition: Returns one byte of information with a summary of any communications, logic, and/or memory errors. Data Length in Bytes: 1 Data Format: BIT Type: Read-only Default Value: 00h Units: N/A Bit Number Meaning 7 Invalid or unsupported PMBus command was received. 6 The PMBus command was sent with invalid or unsupported data. 5 Packet error was detected in the PMBus command. 4 Memory/logic fault. 3:2 These bits are reserved. 1 A PMBus command tried to write to a read-only or protected command, or a communication fault other than the ones listed in this table has occurred. 0 This bit is reserved. STATUS_MFR_SPECIFIC (80h) Definition: Returns one byte of information providing the status of the device's voltage monitoring and clock synchronization faults. Data Length in Bytes: 1 Data Format: BIT Type: Read only Default Value: 00h Units: N/A Bit Number Field Name Meaning 7:4 Reserved 3 External Switching Period Fault These bits are reserved. 2 Reserved 1 VMON UV Fault The voltage on the VMON pin has dropped below the level set by VMON_UV_FAULT_LIMIT. 0 VMON OV Fault The voltage on the VMON pin has risen above the level set by VMON_OV_FAULT_LIMIT. Loss of external clock synchronization has occurred. This bit is reserved. READ_VIN (88h) Definition: Returns the input voltage reading. Data Length in Bytes: 2 Data Format: L11 Type: Read-only Units: V FN9346 Rev.1.00 Mar 15, 2019 Page 44 of 58 RAA210850 7. PMBus Commands Description READ_VOUT (8Bh) Definition: Returns the output voltage reading. Data Length in Bytes: 2 Data Format: L16u Type: Read-only Units: V READ_IOUT (8Ch) Definition: Returns the output current reading. Data Length in Bytes: 2 Data Format: L11 Type: Read-only Default Value: N/A Units: A READ_INTERNAL_TEMP (8Dh) Definition: Returns the controller junction temperature reading from internal temperature sensor. Data Length in Bytes: 2 Data Format: L11 Type: Read-only Units: C READ_DUTY_CYCLE (94h) Definition: Reports the actual duty cycle of the converter during the enable state. Data Length in Bytes: 2 Data Format: L11 Type: Read only Units: % READ_FREQUENCY (95h) Definition: Reports the actual switching frequency of the converter during the enable state. Data Length in Bytes: 2 Data Format: L11 Type: Read only Units: kHz READ_IOUT_0 (96h) Definition: Returns the Phase 1 current reading. Data Length in Bytes: 2 Data Format: L11 Type: Read-only Default Value: N/A Units: A FN9346 Rev.1.00 Mar 15, 2019 Page 45 of 58 RAA210850 7. PMBus Commands Description READ_IOUT_1 (97h) Definition: Returns the Phase 2 current reading. Data Length in Bytes: 2 Data Format: L11 Type: Read-only Default Value: N/A Units: A ASCR_CONFIG (DFh) Definition: Allows user configuration of ASCR settings. ASCR Gain is analogous to bandwidth and ASCR Residual is analogous to damping. To improve load transient response performance, increase ASCR Gain. To lower transient response overshoot, increase ASCR Residual. Increasing ASCR gain can result in increased PWM jitter and should be evaluated in the application circuit. Excessive ASCR gain can lead to excessive output voltage ripple. Increasing ASCR Residual to improve transient response damping can result in slower recovery times, but does not affect the peak output voltage deviation. Typical ASCR Gain settings range from 50 to 1000 and ASCR Residual settings range from 10 to 100. Data Length in Bytes: 4 Data Format: CUS Type: R/W Default Value: Pin-strap setting Bit 31:25 24 Purpose Data Format Unused Value Description 0000000h Unused Reserved This bit is reserved 23:16 ASCR Residual Setting Integer ASCR residual 15:0 ASCR Gain Setting Integer ASCR gain DEVICE_ID (E4h) Definition: Returns the 16-byte (character) device identifier string. Data Length in Bytes: 16 Data Format: ASCII Type: Block Read Default Value: Part number/Die revision/Firmware revision FN9346 Rev.1.00 Mar 15, 2019 Page 46 of 58 RAA210850 7. PMBus Commands Description MFR_IOUT_OC_FAULT_RESPONSE (E5h) Definition: Configures the IOUT overcurrent fault response as defined by the following table. The command format is the same as the PMBus standard fault responses except that it sets the overcurrent status bit in STATUS_IOUT. Data Length in Bytes: 1 Data Format: BIT Type: R/W Default Value: B9h (Disable and 70ms continuous retry) Units: N/A Settings Actions 80h Disable with no retry. B9h Disable and continuous retry with 70ms delay. MFR_IOUT_UC_FAULT_RESPONSE (E6h) Definition: Configures the IOUT undercurrent fault response as defined by the following table. The command format is the same as the PMBus standard fault responses except that it sets the undercurrent status bit in STATUS_IOUT. Data Length in Bytes: 1 Data Format: BIT Type: R/W Default Value: B9h (Disable and 70ms continuous retry) Units: N/A Settings Actions 80h Disable with no retry. B9h Disable and continuous retry with 70ms delay. FN9346 Rev.1.00 Mar 15, 2019 Page 47 of 58 RAA210850 7. PMBus Commands Description SNAPSHOT (EAh) Definition: A 32-byte read-back of parametric and status values. It allows monitoring and status data to be stored to flash following a fault condition. In case of a fault, the last updated values are stored to the flash memory. When the SNAPSHOT STATUS bit is set stored, the device will no longer automatically capture parametric and status values following fault until stored data are erased. Use the SNAPSHOT_CONTROL command to erase store data and clear the status bit before next ramp up. Data erased is not allowed when the module is enabled. Data Length in Bytes: 32 Data Format: Bit field Type: Block Read Byte Number 31:23 Value PMBus Command Format Reserved These bits are reserved 00h 22 Flash Memory Status Byte FF - Not Stored 00 - Stored N/A BIT 21 Manufacturer Specific Status Byte STATUS_MFR_SPECIFIC (80h) Byte 20 CML Status Byte STATUS_CML (7Eh) Byte 19 Temperature Status Byte STATUS_TEMPERATURE (7Dh) Byte 18 Input Status Byte STATUS_INPUT (7Ch) Byte 17 IOUT Status Byte STATUS_IOUT (7Bh) Byte 16 VOUT Status Byte STATUS_VOUT (7Ah) Byte 15:14 Switching Frequency READ_FREQUENCY (95h) L11 13:12 Reserved These bits are reserved 00h 11:10 Internal Temperature READ_INTERNAL_TEMP (8Dh) L11 Duty Cycle READ_DUTY_CYCLE (94h) L11 9:8 7:6 Reserved These bits are reserved L11 5:4 Output Current READ_IOUT (8Ch) L11 3:2 Output Voltage READ_VOUT (8Bh) L16u 1:0 Input Voltage READ_VIN (88h) L11 SNAPSHOT_CONTROL (F3h) Definition: Writing a 01h causes the device to copy the current SNAPSHOT values from NVRAM to the 32-byte SNAPSHOT command parameter. Writing a 02h causes the device to write the current SNAPSHOT values to NVRAM, and writing a 03h erases all SNAPSHOT values from NVRAM. Write (02h) and Erase (03h) can only be used when the device is disabled. All other values are ignored. Data Length in Bytes: 1 Data Format: Bit field Type: R/W byte Value Description 01h Read SNAPSHOT values from NVRAM 02h Write SNAPSHOT values to NVRAM 03h Erase SNAPSHOT values stored in NVRAM. FN9346 Rev.1.00 Mar 15, 2019 Page 48 of 58 RAA210850 7. PMBus Commands Description MFR_VMON_OV_FAULT_LIMIT (F5h) Definition: Reads the VMON OV fault threshold. Data Length in Bytes: 2 Data Format: L11 Type: Read only Default Value: CB00h (6V) Units: V Range: 4V to 6V MFR_VMON_UV_FAULT_LIMIT (F6h) Definition: Reads the VMON UV fault threshold. Data Length in Bytes: 2 Data Format: L11 Type: Read only Default Value: CA00h (4V) Units: V Range: 4V to 6V MFR_READ_VMON (F7h) Definition: Reads the VMON voltage. Data Length in Bytes: 2 Data Format: L11 Type: Read only Default Value: N/A Units: V Range: 4V to 6V FN9346 Rev.1.00 Mar 15, 2019 Page 49 of 58 RAA210850 8. 8. Revision History Revision History 8.1 Firmware Firmware Revision Code RAA210850--G0100 8.2 Change Description Note Initial Release Recommended for new designs. Datasheet Rev Date 1.00 Mar 15, 2019 Updated pin configuration to show correct location for M5, N5, and N6. Updated description for pin D5. Changed PMBus to SMBus in the SMBus Communications section. Changed On-Nominal to On in the table under the OPERATION section on page 35. Updated Disclaimer. 0.00 Sep 12, 2018 Initial release. FN9346 Rev.1.00 Mar 15, 2019 Change Page 50 of 58 Package Outline Drawing For the most recent package outline drawing, see Y58.18x23. Y58.18x23 58 I/O 18mmx23mmx7.5mm Custom HDA Module Rev 4, 4/18 18.00 A Datum A B 1817 16 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 Terminal #A1 Index Area (9x11.5) 12.00 23.00 0.10 M C A B 22.60 0.15 0.10 C 2X 0.40 Ref A B C D E F G H J K L M N P R T U V W Y AA AB AC Pin A1 Indicator C = 0.35 See Detail A RAA210850 FN9346 Rev.1.00 Mar 15, 2019 9. Datum B 16.00 17.20 0.10 C 2X 0.10 M C A B Top View Bottom View 0.10 C 7.50 Max 7.30 Min 2 0.20 Ref 1.00 0.20 Ref Seating Plane 0.08 C C Max 0.025 Side View Page 51 of 58 1. All dimensions are in millimeters. 2. Represents the basic land grid pitch. 3. These 42 I/Os are centered in a fixed row and column matrix at 1.0mm pitch BSC. 4. Dimensioning and tolerancing per ASME Y14.5-2009. 5. Tolerance for exposed PAD edge location dimension on page 3 is 0.1mm. 3 42x0.60 0.05 42x0.60 0.05 3 0.10 M C A B 0.05 M C Terminal Tip 0.100 R Ref 1.00 Detail A 2 9. Package Outline Drawing Notes: 8.20 8.80 6.80 7.20 7.80 5.80 6.20 4.20 4.80 5.20 3.20 3.80 2.20 2.80 0.50 1.20 1.80 0.80 0.20 2.80 2.20 1.80 1.20 0.50 0.20 0.80 4.20 3.80 3.20 5.20 4.80 5.80 7.80 1.00 (2X) 7.20 8.80 1.00 (2X) 11.30 11.30 1.60 (2X) 4.80 (2X) 8.70 2.60 9.70 9.30 9.10 9.70 9.30 9.10 7.70 6.70 6.50 6.30 5.50 5.70 4.70 5.30 4.30 3.70 3.30 2.70 2.00 2.30 1.70 1.30 0.70 0.30 0.30 0.70 1.30 1.70 2.30 2.70 2.90 3.30 4.00 7.70 6.70 7.30 6.30 6.50 5.70 5.50 5.30 4.70 6.00 6.00 8.10 8.10 7.30 4.40 3.50 (2X) 4.60 1.00 (2X) 2.30 1.30 1.60 (2X) 3.40 3.60 2.20 1.10 1.10 (2X) 4.40 4.30 3.70 2.00 1.30 1.00 2.30 5.00 (2X) 9.30 2.00 (2X) 1.60 (2X) 9.30 9.70 SIZE DETAILS FOR THE 16 EXPOSED PADS TERMINAL AND PAD EDGE DETAILS BOTTOM VIEW 8.60 6.40 6.00 6.50 5.20 4.40 3.60 2.40 2.00 1.80 1.20 0.80 0.20 0.40 0.00 3.00 2.60 4.60 3.80 0.60 8.50 9.70 Page 52 of 58 9. Package Outline Drawing 6.40 8.60 5.60 5.40 6.20 7.40 6.60 7.20 2.20 7.00 5.60 6.30 11.30 11.30 4.00 (2X) 1.40 (2X) 2.90 4.00 0.80 (2X) 5.30 (2X) 0.70 0.00 5.10 4.20 2.10 (2X) RAA210850 FN9346 Rev.1.00 Mar 15, 2019 8.30 (2X) 6.20 Stencil opening edge Stencil Opening Edge Position - 1 5.470 3.910 3.590 3.910 3.590 2.030 2.030 0.000 0.000 6.330 6.330 7.510 7.830 8.640 8.960 9.730 9.770 10.090 11.270 11.500 7.790 8.110 9.490 9.730 9.810 11.270 11.500 11.500 9.285 8.715 8.285 7.715 7.285 6.715 6.285 5.715 5.285 4.715 4.285 3.715 1.285 0.715 0.285 0.000 0.285 0.715 1.285 2.715 3.285 11.500 Page 53 of 58 9. Package Outline Drawing Stencil Opening Edge Position - 2 9.000 6.530 5.470 6.215 6.785 7.215 7.785 6.530 1.215 1.785 8.130 7.810 0.000 8.130 7.810 1.785 1.215 9.730 9.410 4.785 4.215 3.785 3.215 9.730 9.410 9.000 8.785 8.215 9.000 0.000 0.230 0.770 1.230 1.910 2.230 2.910 3.230 3.910 4.230 4.910 5.230 5.910 6.230 6.910 7.660 7.340 6.430 5.970 5.240 4.920 4.190 3.870 3.140 2.820 2.090 11.500 11.270 9.000 5.785 5.215 4.785 4.215 3.785 3.215 2.785 2.215 1.785 1.215 0.785 0.215 0.000 0.215 0.785 1.215 1.785 2.215 2.785 3.215 3.785 4.215 4.785 5.215 5.785 6.215 6.785 7.785 7.215 6.785 6.215 9.000 1.390 1.710 2.500 2.820 3.895 4.215 5.290 5.610 6.400 6.720 7.510 7.830 8.770 9.000 9.000 8.770 8.450 7.830 7.510 6.720 6.400 5.610 5.290 4.215 3.895 2.820 2.500 1.710 1.390 0.530 0.000 0.530 RAA210850 9.000 8.570 FN9346 Rev.1.00 Mar 15, 2019 11.500 11.270 11.500 9.285 8.715 8.285 7.715 7.285 6.715 6.285 5.715 5.285 4.715 4.285 3.715 3.285 2.715 2.285 1.715 1.285 0.715 0.285 0.000 0.285 0.715 1.285 1.715 2.285 2.715 3.285 11.500 9.000 7.170 6.230 0.000 6.230 7.170 9.000 9.000 2.770 1.875 1.555 0.660 0.340 0.000 0.555 0.875 1.770 9.000 RAA210850 FN9346 Rev.1.00 Mar 15, 2019 11.500 11.500 11.500 11.500 9.070 9.070 6.670 5.825 5.505 4.660 4.340 3.495 3.175 2.330 0.000 0.000 7.960 7.960 7.640 6.530 7.640 6.530 0.000 0.000 2.930 3.840 4.030 4.160 5.070 2.930 3.840 4.160 5.070 6.030 6.890 7.210 8.070 6.030 6.705 6.330 11.500 11.500 7.025 8.020 Stencil Opening Edge Position - 4 8.570 9.000 6.970 7.230 3.770 4.090 4.570 5.430 1.840 2.160 0.000 0.230 3.430 3.110 2.430 8.570 7.060 6.740 6.110 5.430 5.230 5.110 4.430 4.110 9.280 9.600 10.275 10.595 11.270 11.500 9.000 9.000 6.570 4.890 5.570 5.890 0.000 1.160 1.670 1.990 2.570 2.890 3.570 3.890 4.570 5.970 5.240 4.920 4.430 4.190 3.870 3.140 2.820 2.090 9.000 Page 54 of 58 Stencil Opening Edge Position - 3 8.530 9.270 7.700 9. Package Outline Drawing 11.500 7.640 7.960 8.530 9.270 Page 55 of 58 STENCIL OPENING EDGE POSITION - 5 6.030 6.705 7.025 7.700 8.020 6.030 6.890 7.210 8.070 9.280 9.600 10.275 10.595 11.270 11.500 11.500 11.500 10.950 9.700 9.440 9.700 9.440 8.100 7.840 8.100 7.840 6.500 6.500 5.500 5.500 3.880 3.620 3.880 3.620 2.000 2.000 0.000 6.300 6.300 7.540 7.800 8.670 8.930 9.700 9.800 10.060 11.300 11.500 7.820 8.080 9.520 9.700 9.780 11.300 11.500 9. Package Outline Drawing PCB LAND PATTERN - 1 (FOR REFERENCE) 9.000 0.000 0.000 0.200 0.800 1.200 1.940 2.200 2.940 3.200 3.940 4.200 4.940 5.200 5.940 6.200 6.940 0.000 7.630 7.370 6.400 6.000 5.210 4.950 4.160 3.900 3.110 2.850 2.060 11.500 9.000 8.600 9.000 3.760 4.080 4.810 5.130 5.860 6.180 6.910 3.030 2.030 1.770 0.430 0.000 4.910 4.430 3.570 6.530 7.810 7.490 9.000 8.770 5.320 5.580 6.430 6.690 7.540 7.800 8.800 9.000 3.925 4.185 4.185 3.925 2.790 2.530 1.680 1.420 0.500 0.000 0.500 1.420 1.680 2.530 2.790 9.000 8.800 8.450 7.800 7.540 6.690 6.430 5.580 5.320 9.000 0.000 9.000 RAA210850 FN9346 Rev.1.00 Mar 15, 2019 11.500 11.500 11.300 1.030 0.000 2.270 4.030 5.070 11.500 9.300 8.700 8.300 7.700 7.300 6.700 6.300 5.700 5.300 4.700 4.300 3.700 3.300 2.700 2.300 1.700 1.300 0.700 0.300 0.000 0.300 0.700 1.300 1.700 2.300 2.700 3.300 9.300 8.700 8.300 7.700 7.300 6.700 6.300 5.700 5.300 4.700 4.300 3.700 1.300 0.700 0.300 0.000 0.300 0.700 1.300 2.700 3.300 9.000 2.800 1.845 1.585 0.630 0.370 0.000 0.585 0.845 1.800 9.000 0.000 9.000 6.800 6.200 5.800 5.200 4.800 4.200 3.800 3.200 2.800 2.200 1.800 1.200 0.800 0.200 0.200 0.800 1.200 1.800 2.200 2.800 3.200 3.800 4.200 4.800 5.200 5.800 6.200 6.800 7.800 7.200 9.000 8.800 8.200 RAA210850 FN9346 Rev.1.00 Mar 15, 2019 11.500 11.500 11.500 6.700 5.795 5.535 4.630 4.370 3.465 3.205 2.300 0.000 0.000 6.000 6.920 7.180 8.100 6.300 7.670 7.930 8.500 9.300 Page 56 of 58 PCB LAND PATTERN - 2 (FOR REFERENCE) 11.500 PCB LAND PATTERN - 3 (FOR REFERENCE) 9.000 0.000 1.060 1.700 1.960 2.600 2.860 3.600 3.860 4.600 4.860 5.600 5.860 6.600 6.000 5.210 4.950 4.160 3.900 3.110 2.850 2.060 11.500 9.000 9.000 6.200 6.800 7.200 7.800 3.200 3.800 4.200 4.800 0.000 0.200 0.800 1.200 1.800 1.800 1.200 4.800 4.200 3.800 3.200 9.000 11.500 9. Package Outline Drawing 11.500 11.500 9.100 9.100 7.930 7.670 7.930 7.670 6.500 6.500 0.000 0.000 9.000 0.000 9.000 7.200 6.200 0.000 6.200 7.200 9.000 RAA210850 FN9346 Rev.1.00 Mar 15, 2019 11.500 11.500 11.500 0.000 0.000 1.000 9.310 9.570 10.305 10.565 11.300 11.500 8.100 PCB LAND PATTERN - 5 (FOR REFERENCE) 9.000 3.000 3.790 4.050 4.840 5.100 5.890 6.150 6.940 0.400 0.000 11.500 2.000 1.800 8.600 9.000 7.000 7.200 3.800 4.060 4.600 5.400 1.870 2.130 0.000 0.200 7.030 6.770 6.140 5.400 5.200 5.140 4.400 4.140 3.400 3.140 2.400 9.000 8.600 Page 57 of 58 PCB LAND PATTERN - 4 (FOR REFERENCE) 9.310 9.570 10.305 10.565 11.300 11.500 6.000 6.920 7.180 9. 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