IRMCF188
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High Performance Sensorless Motor Con t rol IC
Description
IRMCF188 is a high performance Flash based motion control IC designed and optimized for complete air
conditioner control which contains two computation engines integrated into one monolithic chip. One is the
Flexible Motion Control Engine (MCETM) for sensorless control of permanent magnet motors or induction motors;
the other is an 8-bit high-speed microcontroller (8051). The user can program a motion control algorithm by
connecting these control elements using a graphic compiler. Key components of the complex sensorless control
algorithms, such as the Angle Estimator, are provided as complete pre-defined control blocks. A unique
analog/digital circuit and algorithm fully supports single shunt or leg shunt current reconstruction. IRMCF188
performs a PFC (Power Factor Correction) function in addition to the motor control. IRMCF188 comes in a 64 pin
QFP package.
Features
• MCETM (Flexible Motion Control Engine) -
Dedicated computation engine for high efficiency
sinusoidal sensorless motor control
• Built-in hardware peripheral for single or two shunt
current feedback reconstruction and analog
circuits
• Supports induction machine and both interior and
surface permanent magnet motor sensorless
control
• Dedicated PFC PWM for digital PFC control
• Loss minimizat ion S pace Vector PWM
• Three-channel analog output (PWM )
• Embedded 8-bit high speed microcontroller (8051)
for flexible I/ O and m an -machine control
• JTAG programmi ng port for emulatio n/debugger
• Serial communicati on interface (UART)
• I2C/SPI serial interface
• Three general purpo se t i mers/counters
• Two special timer s: periodic timer, capture timer
• Watchdog timer wit h independent int ernal clock
• Internal 64 Kbyte flash memory
• 3.3V single supply
Product Summary
Maximum clock input (fcrystal) 60 MHz
Maximum Internal clock (SYS CLK) 120MHz
Maximum 8051 clo ck (8051CLK) 30MHz
MCETM computat i on data range 16 bit signed
8051 Program Fl ash 52KB
8051/MCE Data RAM 4KB
MCE Progra m RAM 12KB
GateKill laten cy (digi tal filtered) 2 μsec
PWM carrier frequen cy 20 bits/ SYSCLK
A/D input channel s 10
A/D converter resolution 12 bits
A/D converter conv ersion speed 2 μsec
Analog output (P WM ) resolution 8 bits
UART baud rate (typ) 57.6 Kbps
Number of digital I/O (max) 24
Package (lead free) QFP64
Typical 3.3V operat ing current 30mA
Base Part Number Package Type
Standard Pack
Orderable Part Number
Form
Quantity
IRMCF188
LQFP64
Tape and Reel
1500
IRMCF188TR
IRMCF188 LQFP64 Tray 1600 IRMCF188TY
IRMCF188
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Table of Contents
1 Overview ................................................................................................................................ 5
2 Pinout ..................................................................................................................................... 6
3 IRMCF188 Block Diagram and Main Functions ..................................................................... 7
4 Application connection and Pin function ................................................................................. 9
4.1 8051 Peripheral Interface Group .......................................................................................... 10
4.2 Motion Peripheral Interface Group ....................................................................................... 11
4.3 Analog Interface Group ........................................................................................................ 12
4.4 Power Interface Group ......................................................................................................... 12
4.5 Test Interface Group ............................................................................................................ 12
5 DC Characteristics ............................................................................................................... 14
5.1 Absolute Maximum Ratings .................................................................................................. 14
5.2 System Clock Frequency and Power Consumption ............................................................. 14
5.3 Digital I/O DC Characteristics ............................................................................................... 15
5.4 Analog I/O DC Characteristics ............................................................................................. 16
5.5 Under Voltage Lockout DC characteristics ........................................................................... 17
5.6 Itrip comparator DC characteristics ...................................................................................... 17
5.7 CMEXT and AREF Characteristics ...................................................................................... 17
6 AC Characteristics ................................................................................................................ 18
6.1 Digital PLL AC Characteristics ............................................................................................. 18
6.2 Analog to Digital Converter AC Characteristics .................................................................... 19
6.3 Op amp AC Characteristics .................................................................................................. 20
6.4 SYNC to SVPWM and A/D Conversion AC Timing .............................................................. 21
6.5 GATEKILL to SVPWM AC Timing ........................................................................................ 22
6.6 Itrip AC Timing ...................................................................................................................... 22
6.7 Interrupt AC Timing .............................................................................................................. 23
6.8 I2C AC Timing ...................................................................................................................... 24
6.9 SPI AC Timing ...................................................................................................................... 25
6.10 UART AC Timing ................................................................................................................ 27
6.11 CAPTURE Input AC Timing ................................................................................................ 28
6.12 JTAG AC Timing ................................................................................................................. 29
7 I/O Structure ......................................................................................................................... 30
8 Pin List .................................................................................................................................. 34
9 Package Dimensions ............................................................................................................ 36
10 Part Marking Information ...................................................................................................... 37
11 Qualification Information ....................................................................................................... 37
IRMCF188
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List of Tables
Table 1. Analog channel sensin g f unc t ions in Leg and Single Shunt Modes ........................... 12
Table 2. Absolute Maximum Ratings ....................................................................................... 14
Table 3. System Clock Frequency ........................................................................................... 14
Table 4. Digital I/O DC Characteristics .................................................................................... 15
Table 6. Analog I/O DC Characteristics ................................................................................... 16
Table 7. UVcc DC Characterist ics ........................................................................................... 17
Table 8. Itrip DC Characteristics .............................................................................................. 17
Table 9. CMEXT and AREF DC Characteris t ics ...................................................................... 17
Table 10. PLL AC Characterist ics ............................................................................................ 18
Table 11 . A/D Converter AC Charact er istics .......................................................................... 19
Table 12 Current Sensing OP Amp AC Character istics ........................................................... 20
Table 13. SYNC AC Characteristics ........................................................................................ 21
Table 14. GATEKILL to SVPWM AC Timing ........................................................................... 22
Table 15. Itrip AC Timing ......................................................................................................... 22
Table 16. Interrupt AC Timing .................................................................................................. 23
Table 17. I2C AC Timing ......................................................................................................... 24
Table 18. SPI Write AC Timing ................................................................................................ 25
Table 19. SPI Read AC Timing ................................................................................................ 26
Table 20. UART AC Timing ..................................................................................................... 27
Table 21. CAPTUR E AC Timing .............................................................................................. 28
Table 22. JTAG AC Timing ...................................................................................................... 29
Table 23. Pin List ..................................................................................................................... 35
IRMCF188
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List of Figures
Figure 1. Typical A ppl ication Block Diag ram Using IRMCF188 ................................................................................ 5
Figure 2. Pinout of IRMCF188 ................................................................................................................................... 6
Figure 3. IRMCF188 Block Diagram .......................................................................................................................... 7
Figure 4. IRMCF188 Leg Shunt Connection Diagram ............................................................................................... 9
Figure 5. IRMCF188 Single Shunt Connection Diagram ......................................................................................... 10
Figure 6. Crystal circuit example ............................................................................................................................. 18
Figure 7. Voltage droop and S/H hol d time ............................................................................................................. 19
Figure 8 Op amp out put capacitor ........................................................................................................................... 20
Figure 9. SYNC tim i ng ............................................................................................................................................. 21
Figure 10. Gat ekill timing ......................................................................................................................................... 22
Figure 11. ITRIP timing ............................................................................................................................................ 22
Figure 12. Interr upt timing ....................................................................................................................................... 23
Figure 13. I2C Timing ............................................................................................................................................... 24
Figure 14. SPI write timing ...................................................................................................................................... 25
Figure 15. SPI read timing ....................................................................................................................................... 26
Figure 16. UART timing ........................................................................................................................................... 27
Figure 17. CAPTURE timing .................................................................................................................................... 28
Figure 18. JTAG timing ............................................................................................................................................ 29
Figure 19. PWMUL/PWMUH/PWMVL/PWMVH/PWMWL/PWMWH output ............................................................ 30
Figure 20. All digital I/O except motor PWM output ................................................................................................ 30
Figure 21. RESET, GATEKILL I/O .......................................................................................................................... 31
Figure 22. Analog input ........................................................................................................................................... 31
Figure 23. ADCL pin i nput structure ........................................................................................................................ 31
Figure 24 Analog operat i onal amplifier output and AREF I/O structure ................................................................. 32
Figure 25. VSS,AVSS pin I/O structure ................................................................................................................... 32
Figure 26. VDD1,VDDCAP pin I/ O st ructure ........................................................................................................... 32
Figure 27. XTAL0/ X T A L1 pins structure .................................................................................................................. 33
IRMCF188
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1 Overview
IRMCF188 is a new generation International Rectifier integrated circuit device primarily designed as a one-chip
solution for complete inverterized appliance motor control applications. Unlike a traditional microcontroller or
DSP, the IRMCF188 provides a built-in closed loop sensorless control algorithm using the unique Flexible Motion
Control Engine (MCETM) for permanent magnet motors as well as induction motors. The MCETM consists of a
collection of control elements, motion peripherals, a dedicated motion control sequencer and dual port RAM to
map internal signal nodes. IRMCF188 also employs a unique single shunt current reconstruction circuit to
eliminate additional analog/digital circuitry and enables a direct shunt resistor interface to the IC, while still
supporting leg shunt current sensing. Motion control programming is achieved using a dedicated graphical
compiler integrated into the MATLAB/SimulinkTM development environment. Sequencing, user interface, host
communication, and upper layer control tasks can be implemented in the 8051 high-speed 8-bit microcontroller.
The 8051 microcontroller is equipped with a JTAG port to facilitate emulation and debugging. Figure 1 shows a
typical applicat i on schematic using the IRMCF188 in l eg shunt mode.
IRMCF188 contai ns 64K bytes of Fl ash program memory and comes in a 64-pi n QF P package.
IRMCF188
Power
Supply
IRS2630D
Digial I/O
Appliance Inverter
With PFC
3.3V
Passive
EMI
Filter
Host
communication
Motor
(PMSM or IM)
Galvanic
isolation
Analog Input
22
6
2
PFC gate drive
UART interface
to Front Panel
Figure 1. Typical Application Block Diagram Using IRMCF188
IRMCF188
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2 Pinout
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
15
14
13
16
3
12
4
11
5
6
7
8
9
10
2
1
P1.1/RXD
P1.2/TXD
VDD1
VSS
VDDCAP
P1.3/SYNC/SCK
P1.4/CAP
P3.2/INT0
34
35
36
33
46
37
45
38
44
43
42
41
40
39
47
48
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AIN2
OP1O
VDCBUS
P2.7/AOPWM1
P2.6/AOPWM0
PWMUH
PWMVH
PWMWH
PWMUL
PWMVL
PWMWL
GATEKILL
VDD1
VSS
OP2O
OP2-
OP2+
XTAL0
T3.5/T1
RESET
P1.5
TCK
TDI/P5.1
TDO/P5.3
TMS/P5.2
SDA/CS0
SCL/SDI-SDO
PFCGKILL
PFCPWM
P2.1
IRMCF188
(Top View)
AIN4
AIN3
OP3O
OP3+
OP3-
P2.0/NMI
P2.2
AIN1
P3.3/INT1
P1.7
P1.6
P1.0/T2
P3.1/AOPWM2
P3.0/CS1
XTAL1
P2.3
OP1-
OP1+
VDDCAP
T3.4/T0
AVSS
AREF
CMEXT
P3.7
ADCH
ADCL
Figure 2. Pinout of IRMCF188
IRMCF188
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3 IRMCF188 Block Diagram and Main Functions
IRMCF188 block diagram for leg shunt mode is shown in Figure 3.
Motion Control
Sequencer
Dual Port
RAM
2kbyte
MCE
Program
RAM
12kbyte
Program
Flash
64kB
8bit uP Address/data bus
Motion Control Bus
S/H
A/D
MUX
D/A
(PWM)
Timer
Counnter0,1,2
Watchdog
Timer Motion
Control
Modules
UART
I2C
SND
RCV
6
Low Loss
SVPWM
VDCBUS
GATEKILL
To IGBT
gate drive
Mini- Motion
Control
Engine
(MiniMCE)
Monitoring
Host
Interface
Digital
I/Os
8bit (8051)
microcontroller
AIN1
AIN2
JTAG
Emulator
Debugger 4
Freq
Synthesizer
2
Ceramic
Resonator
(4MHz)
30MHz
AIN3
Analog
Input
2
Capture
Interrupt
Control
Motor
Current
Reconstruct
Speed
command
PORT 1
SCL
SDA
PORT
2
PORT
3
AIN4
PFC PWM
PFC
Current
Sense
8bit
CPU
Core
Local
RAM
2kbyte
120MHz
OP2
OP3
OP1
3
3
3
ADCH
ADCL
GATEKILL
To IGBT
gate drive
Figure 3. IRMCF188 Block Diagram
IRMCF188 contai ns the following funct ions for sensorles s A C m otor control applications:
Motion Control Engine (MCETM)
• Sensorless FOC (complete sensorless field
oriented contr ol )
• Proportional plus Integ ral block
• Low pass filter
• Differentiator and lag (high pass f i l ter)
• Ramp
• Limit
• Angle estimate (sensorless control)
• Inverse Clark transformat io n
• Vector rotator
• Bit latch
• Peak detect
• Transition
• Multiply-divide (signed and unsigned)
• Adder
8051 microcontroller
• Two 16 bit timer/counters
• One 16 bit periodic timer
• One 16 bit watchdog timer
• One 16 bit capture timer
• Up to 24 discrete digital I/Os
• Ten-channel 12 bit A /D
o Buffered (curr ent sensing) three
channels (0 – 1.2V i nput)
o Unbuffered seven channels (0 –
1.2V input)
• JTAG port (4 pins )
• Up to three chann el s of analog output (8 bi t
PWM)
• UART
• I2C/SPI port
IRMCF188
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• Divide (signed and unsigned)
• Subtractor
• Comparator
• Counter
• Accumulator
• Switch
• Shift
• ATAN (arc tangent)
• Function block (any curve fitt i ng, nonlinear
function)
• 16 bit wide Logic oper ations (AND, OR,
XOR, NOT, NEGATE)
• MCETM program memory and dual port RAM
(6K byte)
• MCETM control seq uencer
• 64K byte Flash mem ory
• 2K byte data RAM
IRMCF188
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4 Application connection and Pin f unction
Figure 4 shows the application co nnections in leg shunt mode. Figure 5 shows the application connections in
single shunt mode.
P1.2/TXD
P1.1/RXD
XTAL0 PWMUH
PWMUL
PWMVH
PWMVL
PWMWH
PWMWL
GATEKILL
AIN2 – AIN4
Host
Microcontroller
(RS232C)
Digital I/O
Control
System
Clock
4MHz
Crystal
P2.6/ AOPWM0
Analog Output
XTAL1
P3.0/INT2
RESET
TDI
JTAG Control
( OTP programming
& Emulation)
TCLK
TSM
TDO
0.6V
OP2+
OP2- -
OP2O
Other analog input (0 – 1,2V)
AVDD
1.8V
AVSS
VDD1
3.3V VSS
CMEXT
OP3+
OP3- -
OP3O
OP1+
OP1- -
OP1O
Optional External Voltage
Reference (0.6V)
P2.7/ AOPWM1
SCL
SDA
Other Communication
(I
2
C)
Frequency
Synthesizer
RS232C
I
2
C/SPI
PORT1
PORT2
RESET
PWM0
PWM1
JTAG
Interface
Low Loss
Space
Vector
PWM
S/H
8051
CPU
Dual
Port
Memory
(2kB)
&
MCE
Memory
(12kB)
Motion
Control
Modules
Motion
Control
Sequencer
12-bit
A/D &
MUX
System
clock
Local
RAM
(2kByte)
Program
Flash
(64kByte)
System
Reset
Watchdog
Timer
Timers
IRMCF188
AREF
PWM2
P3.1/ AOPWM2
PORT3
P1.5
P1.6
P1.7
P2.2
P2.0/NMI
P2.3
P3.2/INT0
3
1.8V
Voltage
Regulator
VDDCAP
3.3V
Motor shunt
resistors
P3.3
P3.4
P3.5
P2.1
Motor
HVIC
Gate Drive
IRS2336D
0.6V
Motor
Current
Reconstruct
0.2V
From PFC
shunt
AC 230V
PFCPWM
PFC GATEKILL
PFC shunt
resistor
P1.3/SYNC
P1.0/T2
P1.4/CAP
S/H
ADCH, ADCL
2A/D Calibration Reference
Voltages
From AC
Voltage
VDCBUS
VAC+
VAC-
VACO
0.2V
AIN1
Figure 4. IRMCF188 Leg Shunt Connection Diagram
IRMCF188
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P1.2/TXD
P1.1/RXD
XTAL0 PWMUH
PWMUL
PWMVH
PWMVL
PWMWH
PWMWL
GATEKILL
AIN1 – AIN4
Host
Microcontroller
(RS232C)
Digital I/O
Control
System
Clock
4MHz
Crystal
P2.6/ AOPWM0
Analog Output
XTAL1
P3.0/INT2
RESET
TDI
JTAG Control
( OTP programming
& Emulation)
TCLK
TSM
TDO
0.6V
OP2+
OP2-
OP2O
Other analog input (0 – 1,2V)
AVDD
1.8V
AVSS
VDD1
3.3V VSS
CMEXT
OP3+
OP3-
OP3O
OP1+
OP1-
OP1O
Optional External Voltage
Reference (0.6V)
P2.7/ AOPWM1
SCL
SDA
Other Communication
(I
2
C)
Frequency
Synthesizer
RS232C
I
2
C/SPI
PORT1
PORT2
RESET
PWM0
PWM1
JTAG
Interface
Low Loss
Space
Vector
PWM
S/H
8051
CPU
Dual
Port
Memory
(2kB)
&
MCE
Memory
(12kB)
Motion
Control
Modules
Motion
Control
Sequencer
12-bit
A/D &
MUX
System
clock
Local
RAM
(2kByte)
Program
Flash
(64kByte)
System
Reset
Watchdog
Timer
Timers
IRMCF188
AREF
PWM2
P3.1/ AOPWM2
PORT3
P1.6
P1.7
P2.2
P2.0/NMI
P2.3
P3.2/INT0
4
3.3V
1.8V
Voltage
Regulator
VDDCAP
3.3V
Motor
shunt
resistor
P3.3
P3.4
P3.5
P2.1
Motor
HVIC
Gate Drive
IRS2336D
0.6V
Motor
Current
Reconstruct
0.2V
From PFC
shunt
AC 230V
PFCPWM
PFC GATEKILL
PFC shunt
resistor
P1.3/SYNC
P1.0/T2
P1.4/CAP
S/H
ADCH, ADCL
2A/D Calibration Reference
Voltages
From AC
Voltage
VDCBUS
P1.5
Figure 5. IRMCF188 Single Shunt Connection Diagram
4.1 8051 Peripheral Interface Group
UART Interface
P1.2/TXD Output, Transmit data from IRMCF188
P1.1/RXD Input, Receive data to IRMCF188
Discrete I/O In terface
P1.0/T2 Input/output port 1. 0, can be configured as Timer/Counter 2 input
P1.1/RXD Input/output port 1.1, can be configured as RXD input
P1.2/TXD Input/output port 1.2, can be configure d as TX D output
P1.3/SYNC/SCK Input/output port 1.3, can be configured as SYNC output or SPI clock output
P1.4/CAP Input/output port 1.4, can be configured as Capture Tim er i nput
P1.5 Input/output port 1.5
P1.6 Input/output port 1.6
P1.7 Input/output port 1.6
P2.0/NMI Input/output port 2. 0, can be configured as non-maskable int errupt input
P2.2 Input/output port 2.2
P2.3 Input/output port 2.3
P2.6/AOPWM0 Input/output port 2.6, can be configure d as A OPWM0 output
IRMCF188
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P2.7/AOPWM1 Input/output port 2.7, can be configure d as A OPWM1 output
P3.0/INT2/CS1 Input/output port 3.0, can be configured as INT2 input or SPI chip select 1
P3.1/AOPWM2 Input/output port 3.1, can be configured as AOP WM2 output
P3.2/NINT0 Input/output port 3.2, can be configured as I NT0 input
P3.3/NINT1 Input/output port 3.3, can be configured as I NT1 input
P3.4/T0 Input/output port 3. 4, can be configured as T0 i nput for counter mode
P3.5/T1 Input/output port 3. 5, can be configured as T1 i nput for counter mode
P3.7 Input/output port 3.7
P5.1/TDI Input port 5.1, configur ed as JTAG port by default
P5.2/TMS Input port 5.2, configured as JTAG port by default
Analog Output Interface
P2.6/AOPWM0 Input/output, can be configured as 8-bit PWM output 0 with programmable carrier
frequency
P2.7/AOPWM1 Input/output, can be configured as 8-bit PWM output 1 with programmable carrier
frequency
P3.1/AOPWM2 Input/output, can be configured as 8-bit PWM output 2 with programmable carrier
frequency
Crystal Interface
XTAL0 Input, connected to cry st al
XTAL1 Output, connected to crystal
Reset Inter face
RESET Input and Output, sy st em reset, doesn’t require external RC t im e constant
I2C Interface
SCL/SO-SI Output, I2C clock output, or SPI data
SDA/CS0 Input/output, I2C Dat a l ine or SPI chip select 0
I2C/SPI Interface
SCL/SO-SI Output, I2C clock output, or SPI data
SDA/CS0 Input/output, I2C data line or SPI chip select 0
P1.3/SYNC/SCK Input/output port 1.3, can be configured as SYNC output or SPI clock output
P3.0/INT2/CS1 Input/output port 3.0, can be configured as INT2 input or SPI chip select 1
4.2 Motion Peripheral Interf ace Group
PWM
PWMUH Output, PWM phase U hig h side gate signal, internally pulled down by 58kΩ,
configured high true at a power up
PWMUL Output, PWM phase U low side gate signal, internally pulled down by 58kΩ,
configured high true at a power up
PWMVH Output, PWM phas e V hi gh side gate signal, i nternally pulled down by 58kΩ,
configured high true at a power up
PWMVL Output, PWM phase V low side gate signal, internally pulled down by 58kΩ,
configured high true at a power up
PWMWH Output, PWM phase W high side gate signal, internally pulled down by 58kΩ,
configured high true at a power up
PWMWL Output, PWM phase W low side gate signal, internally pulled down by 58kΩ,
configured high true at a power up
PFCPWM Output, PFCPWM output signal, internally pulled up by 70kΩ, configured low true at a
power up
IRMCF188
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Fault
GATEKILL Input, upon assertion this negates all six PWM signals, activ e l ow, internally pull ed up
by 70kΩ
PFCGKILL Input, upon assertion, this negates PFCP WM signal, active low, internally pulled up by
70kΩ
4.3 Analog Interface Gr oup
AVSS Analog power return, (analog internal 1.8V power is share d with VDDCAP)
AREF 0.6V buffered out put
CMEXT Unbuffered 0.6V , input to the AREF buffer, capacitor needs to be connect ed.
OP1+ Input, Operational amplifie r positive input for application sensing
OP1- Input, Operati onal am pl i fier negative input for application sensing
OP1O Output, Operational amplif ier output for application sensing
OP2+ Input, Operational amplifie r positive input for application sensing
OP2- Input, Operati onal am pl i fier negative input for applicati on sensing
OP2O Output, Operational amplif ier output for application sensing
OP3+ Input, Operational amplifie r positive input for application sensing
OP3- Input, Operati onal am pl i fier negative input for applicati on sensing
OP3O Output, Operational amplif ier output for appli cat ion sensin g
VDCBUS Input , Analog input channel (0 – 1.2V), allocated for DC bus voltage input
AIN1 Input, Analog input channel 1 (0 – 1.2V), needs to be pulled down to AVSS if unused
AIN2 Input, Analog input channel 2 (0 – 1.2V), needs to be pulled down to AVSS if unused
AIN3 Input, Analog input channel 3 (0 – 1.2V), needs to be pulled down to AVSS if unused
AIN4 Input, Analog input channel 4 (0 – 1.2V), needs to be pulled down to AVSS if unused
ADCH Input, Analog input channel dedicated for A/D compensation (0 – 1.2V), needs to be
pulled down to AV SS if unused
ADCL Input, A nal og input channel dedic ated for A/D compensation (0 – 1.2V), internally
biased to 0.6V , see Figure 23 for internal structure
Analog Channel
Leg Shunt Mode
Single Shunt Mode
Pin number(s)
OP1
PFC Current
AC Voltage
19, 20, 21
OP2
Motor U Phase Current
Motor Shunt Current
28, 29, 30
OP3
Motor V Phase Current
PFC Current
34, 35, 36
AIN1
AC Voltage
Unallocated
23
Table 1. Analog channel sensing functions in Leg and Single S hunt Modes
4.4 Power Interface Group
VDD1 Digital power (3.3V)
VDDCAP Internal 1.8V output, requires capacit ors to the pin. Share d with analog power pad
internally
Note: The internal 1.8V supply is not designed to power any external circuits or
devices. Only capacitors should be co nnected to this pi n.
VSS Digital common
4.5 Test Interface Group
P5.2/TMS JTAG test mode input or in put digital port
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5 DC Characteristics
5.1 Absolute Maximum Ratings
Symbol
Parameter
Min
Typ
Max
Condition
VDD1
Supply Voltage
-0.3 V
-
3.6 V
Respect to VSS
VIA
Analog Input Voltage
-0.3 V
-
1.98 V
Respect to AVSS
VID
Digital Input Voltage
-0.3 V
-
6.0 V
Respect to VSS
TA
Ambient Temperature
-40 ˚C
-
85 ˚C
TS
Storage Temperat ure
-65 ˚C
-
150 ˚C
Table 2. Absolute Maximum Ratings
Caution: Stresses beyond those listed in “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and function of the device at these or any other conditions beyond those
indicated in the ope rational sections of the specificati ons are not implied.
5.2 System Clock Frequenc y and Power Consumption
CAREF = 1nF, CMEXT= 100nF. VDD1=3.3V, Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
Unit
SYSCLK
System Clock
32
-
120
MHz
PD
Power consumption
1001)
-
mW
Table 3. System Clo ck F requency
Note 1) The value is b ased on the condition of MCE clock=100M Hz, 8051 clock 20MHz with a actual motor and
PFC running by a ty pical M CE application program and 8051 code.
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5.3 Digital I/O DC Characteristics
Symbol
Parameter
Min
Typ
Max
Condition
VDD1
Supply Voltage
3.0 V
3.3 V
3.6 V
Recommended
VIL
Input Low Voltage
-0.3 V
-
0.8 V
Recommended
VIH
Input High Voltage
2.0 V
3.6 V
Recommended
CIN
Input capacitance
-
3.6 pF
-
(1)
IL
Input leakage cur rent
±10 nA
±1 μA
VO = 3.3 V or 0 V
I
OL1
(2)
Low level output cur rent
8.9 mA
13.2 mA
15.2 mA
V
OL
= 0.4 V
(1)
I
OH1
(2)
High level output
current
12.4 mA
24.8 mA
38 mA
V
OH
= 2.4 V
(1)
I
OL2
(3)
Low level output cur rent
17.9 mA
26.3 mA
33.4 mA
V
OL
= 0.4 V
(1)
I
OH2
(3)
High level output
current
24.6 mA
49.5 mA
81 mA
V
OH
= 2.4 V
(1)
Table 4. Digital I/O DC Characteristics
Note:
(1) Data guaranteed by design.
(2) Applied to SCL/SO-SI, SDA/CS0 pins.
(3) Applied to all digit al I/O pins except SCL/SO-SI and SDA/CS0 pins.
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5.4 Analog I/O DC Characteristics
- OP amps for application sensing (OP1+, OP1-, OP1O, OP2+, OP2-, OP2O, OP3+, OP3-, OP3O)
CAREF = 1nF, CMEXT= 100nF. VDD1=3.3V, Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
Condition
VOFFSET
Input Offset Vol tage
-
-
26 mV
VAVDD = 1.8 V
VI
Input Voltage Range
0 V
1.2 V
Recommended
V
OUTSW
OP amp output
operating range
50 mV
(1)
-
1.2 V
V
AVDD
= 1.8 V
CIN
Input capacitance
-
3.6 pF
-
(1)
R
FDBK
OP amp feedback
resistor
5 kΩ
-
20 kΩ
Requested
between IFBO and
IFB-
OP
GAINCL
Operating Close lo op
Gain
80 db
-
-
(1)
CMRR
Common Mode
Rejection Ratio
-
80 db
-
(1)
I
SRC
Op amp output source
current
-
1 mA
-
V
OUT
= 0.6 V
(1)
I
SNK
Op amp output sink
current
-
100 μA
-
V
OUT
= 0.6 V
(1)
Table 5. Analog I/O DC Characteristics
Note:
(1) Data guaranteed by design.
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5.5 Under Voltage Lockout DC characteristics
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
Condition
UV
CC+
UVcc positive going
Threshold
2.78 V
3.04 V
3.23 V
(1)
UV
CC-
UVcc negative going
Threshold
2.78 V
2.97 V
3.23 V
UVCCH
UVcc Hysteresys
-
73 mV
-
(1)
Table 6. UVcc DC Charac ter isti c s
Note:
(1) Data guaranteed by design.
5.6 Itrip comparator DC characteristics
Unless specified, VDD1=3.3V, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
Condition
Itrip
+
Itrip positive going
Threshold
-
1.22V
-
V
DD1
= 3.3 V
Itrip
-
Itrip negative going
Threshold
-
1.10V
-
V
DD1
= 3.3 V
ItripH
Itrip Hysteresys
-
120mV
-
Table 7. Itrip DC Characteristics
5.7 CMEXT and AREF C h aracteristics
CAREF = 1nF, CMEXT= 100nF. Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
Condition
VCM
CMEXT voltage
495 mV
600 mV
700 mV
VVDD1 = 3.3 V
VAREF
Buffer Output V ol tage
495 mV
600 mV
700 mV
VVDD1 = 3.3 V
∆Vo
Load regulation (VDC-0.6)
-
1 mV
-
(1)
PSRR
Power Supply Reject ion Ratio
-
75 db
-
(1)
Table 8. CMEXT and AREF DC Characteris ti cs
Note:
(1) Data guaranteed by design.
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6 AC Characteristics
6.1 Digital PLL AC Characteristics
Symbol
Parameter
Min
Typ
Max
Condition
F
CLKIN
Crystal input
frequency
3.2 MHz
4 MHz
60 MHz
(1)
(see figure below)
F
PLL
Internal clock
frequency
32 MHz
50 MHz
128 MHz
(1)
F
LWPW
Sleep mode output
frequency
F
CLKIN
÷ 256
-
-
(1)
JS
Short time jitter
-
200 psec
-
(1)
D
Duty cycle
-
50 %
-
(1)
TLOCK
PLL lock time
-
-
500 μsec
(1)
Table 9. PLL AC Characteristics
Note:
(1) Data guaranteed by design.
Xtal
R
1
=1MΩ
R
2
=1KΩ
C
1
=15PF
C
2
=15PF
XTAL0
XTAL1
Figure 6. Crystal circu it example
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6.2 Analog to Digital Converter AC Characteristics
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
Condition
TCONV
Conversion time
-
-
2.05 μsec
(1)
T
HOLD
Sample/Hold maximum
hold time
-
-
10 μsec
Voltage droop ≤ 15
LSB
(see figure below)
Table 10 . A/D Conv erter AC Char act e ri sti cs
Note:
(1) Data guaranteed by design.
T
HOLD
Voltage droop
t
SAMPLE
S/H Voltage
Input Voltage
Figure 7. Voltage droop and S / H hol d ti m e
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6.3 Op amp AC Characteristics
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
Condition
OP
SR
OP amp slew rate
-
10 V/μsec
-
VDD1 = 3.3 V, CL
= 33 pF
(1)
OPIMP
OP input impedan ce
-
108 Ω
-
(1) (2)
T
SET
Settling time
-
400 ns
-
VDD1 = 3.3 V, CL
= 33 pF
(1)
Table 11 Current Sensing OP Amp AC Characteristics
Note: (1) Data guaranteed by design.
(2) To guarantee st abi li ty of the operational amplifier, it is recommended t o l oad the output pin b y a
capacitor of 47pF, see Figure 8. Here only Op-amp 1 is shown but all op amp outputs should be loaded
with this capacitor value.
AVREF
OP1+
OP1-
OP1O
IRMCF188 IC External
components
47pF
Figure 8 Op amp output capacitor
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6.4 SYNC to SVPWM and A/D Conversion AC Timing
SYNC
IU,IV,IW
t
wSYNC
t
dSYNC1
AINx
t
dSYNC2
PWMUx,PWMVx,PWMWx
t
dSYNC3
Figure 9. SYNC timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
Unit
twSYNC
SYNC pulse width
-
32
-
SYSCLK
t
dSYNC1
SYNC to current f eedback
conversion time
-
-
100
SYSCLK
t
dSYNC2
SYNC to AIN0-4, ADCH,
ADCL analog input
conversion time
-
-
200
SYSCLK
(1)
t
dSYNC3
SYNC to PWM output delay
time
-
-
2
SYSCLK
Table 12. SYNC AC Char acte ri sti cs
Note:
(1) AIN2 – AIN4, ADCH, ADCL channels are converted once ever y 5 SYNC events
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6.5 GATEKILL to SVPWM AC Timing
GATEKILL
PWMUx,PWMVx,PWMWx
t
wGK
t
dGK
Figure 10. Gatekill timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
Unit
twGK
GATEKILL pulse width
32
-
-
SYSCLK
t
dGK
GATEKILL to PWM
output delay
-
-
100
SYSCLK
Table 13. GATEKILL to SVPWM AC Timing
6.6 Itrip AC Timing
Itrip
PWMUH,PWMUL,
PWMVH,PWMVH,
PWMWH,PWMWL
tItrip
Figure 11. ITRIP timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
Unit
tITRIP
Itrip propagati on del ay
-
-
100(sysclk)+1.0usec
SYSCLK+usec
Table 14. Itrip AC Timing
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6.7 Interrupt AC Timing
P3.2/INT0
P3.3/INT1
Internal
Program
Counter
Internal Vector Fetch
twINT
tdINT
Figure 12. Interrupt timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
Unit
t
wINT
INT0, INT1 Interrupt
Assertion Time
4
-
-
SYSCLK
tdINT
INT0, INT1 latency
-
-
4
SYSCLK
Table 15. Interrupt AC Timing
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6.8 I2C AC Timing
SCL
SDA
t
I2ST1
t
I2ST2
t
I2WSETUP
T
I2CLK
t
I2WHOLD
t
I2RSETUP
t
I2RHOLD
T
I2CLK
t
I2EN1
t
I2EN2
Figure 13. I2C Timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
Unit
TI2CLK
I2C clock period
10
-
8192
SYSCLK
tI2ST1
I2C SDA start time
0.25
-
-
TI2CLK
tI2ST2
I2C SCL start time
0.25
-
-
TI2CLK
tI2WSETUP
I2C write setup time
0.25
-
-
TI2CLK
tI2WHOLD
I2C write hold time
0.25
-
-
TI2CLK
tI2RSETUP
I2C read setup tim e
I2C filter time(1)
-
-
SYSCLK
tI2RHOLD
I2C read hold tim e
1
-
-
SYSCLK
Table 16. I2C AC Timing
Note:
(1) I2C read setup time is det ermined by the programmable fil ter time applied to I2C communi cat ion.
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6.9 SPI AC Timing
6.9.1.1 SPI Write AC timing
P1.3/SYNC/SCK
SCL/SO-SI
T
SPICLK
t
WRDELAY
t
CSHOLD
SDA/CS0
P3.0/INT2/CS1
t
CSHIGH
Bit7(MSB) Bit0(LSB)
t
SPICLKHT
t
SPICLKLT
t
CSDELAY
Figure 14. SPI write timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
Unit
TSPICLK
SPI clock period
4
-
-
SYSCLK
tSPICLKHT
SPI clock high time
-
1/2
-
TSPICLK
tSPICLKLT
SPI clock low time
-
1/2
-
TSPICLK
tCSDELAY
CS to data delay time
-
-
10
nsec
t
WRDELAY
CLK falling edge to data
delay time
-
-
10
nsec
t
CSHIGH
CS high time between two
consecutive by te transfer
1
-
-
T
SPICLK
tCSHOLD
CS hold time
-
1
-
TSPICLK
Table 17. SPI Write AC Timing
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6.9.1.2 SPI Read AC Timing
P1.3/SYNC/SCK
SCL/SO-SI
T
SPICLK
t
RDSU
t
CSHOLD
SDA/CS0
P3.0/INT2/CS1
t
CSHIGH
Bit7(MSB) Bit0(LSB)
t
SPICLKHT
t
SPICLKLT
t
CSRD
t
RDHOLD
Figure 15. SPI read timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
Unit
TSPICLK
SPI clock period
4
-
-
SYSCLK
tSPICLKHT
SPI clock high time
-
1/2
-
TSPICLK
tSPICLKLT
SPI clock low time
-
1/2
-
TSPICLK
tCSRD
CS to data delay time
-
-
10
nsec
tRDSU
SPI read data setup time
10
-
-
nsec
tRDHOLD
SPI read data hold time
10
-
-
nsec
t
CSHIGH
CS high time between two
consecutive by te transfer
1
-
-
T
SPICLK
tCSHOLD
CS hold time
-
1
-
TSPICLK
Table 18. SPI Read AC Timing
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6.10 UART AC Timing
TXD
RXD
Data and Parity Bit
Start Bit
T
BAUD
Stop Bit
T
UARTFIL
Figure 16. UART timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
Unit
TBAUD
Baud Rate Period
-
57600
-
bit/sec
T
UARTFIL
UART sampling filter
period
(1)
-
1/16
-
T
BAUD
Table 19. UART AC Timing
Note:
(1) Each bit includi ng st art and stop bit i s sa m pl ed three times at cent er of a bit at an interv al of 1/16 TBAUD. If
three sample d values do not agree, then UART noise err or is generated.
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6.11 CAPTURE Input AC Timing
P1.4/CAP
CREV(H,L)
Internal
register
t
CAPHIGH
T
CAPCLK
t
CRDELAY
t
CAPLOW
t
CLDELAY
CLAST(H,L)
Internal
register
t
INTDELAY
Interrupt
Vector Fetch
Interrupt
Figure 17. CAPTURE timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
Unit
TCAPCLK
CAPTURE input period
8
-
-
SYSCLK
tCAPHIGH
CAPTURE input hi gh time
4
-
-
SYSCLK
tCAPLOW
CAPTURE input low time
4
-
-
SYSCLK
t
CRDELAY
CAPTURE falling edge to
capture register latch time
-
-
4
SYSCLK
t
CLDELAY
CAPTURE rising edg e to
capture register latch time
-
-
4
SYSCLK
t
INTDELAY
CAPTURE input interrupt
latency time
-
-
4
SYSCLK
Table 20. CAPTURE AC Timing
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6.12 JTAG AC Timing
TCK
TDO
t
JHIGH
T
JCLK
t
CO
t
JLOW
t
JSETUP
t
JHOLD
TDI/TMS
Figure 18. JTAG timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
Unit
TJCLK
TCK Period
-
-
50
MHz
tJHIGH
TCK High Period
10
-
-
nsec
tJLOW
TCK Low Period
10
-
-
nsec
t
CO
TCK to TDO propagat i on delay
time
0
-
5
nsec
tJSETUP
TDI/TMS setup time
4
-
-
nsec
tJHOLD
TDI/TMS hold time
0
-
-
nsec
Table 21. JTAG AC Timing
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7 I/O Structure
The following f i gure shows the PWM out put (PWMUH/P WM UL/ PWMVH/PWMVL/PWMWH/PWMWL/PFCPWM)
270 Ω
6.0V
6.0V
Internal digital circuit
High true logic
VDD1
(3.3V)
VSS
58k Ω
PIN
Figure 19. PWMUL/PWMUH/PWMVL/PWMVH/PWMWL/PWMWH/PFCPWM output
The following f i gure shows the digital I/O structure ex cept the PWM output
6.0V
6.0V
Internal digital circuit
Low true logic
VDD1
(3.3V)
70k Ω
PIN
VSS
270 Ω
Figure 20. All digital I/O except PWM output
The following f i gure shows RESET and GA T E KILL I/O structure.
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270 Ω
6.0V
6.0V
RESET
GATEKILL
circuit
VDD1
(3.3V)
70k Ω
PIN
VSS
Figure 21. RESET, GATEKILL I/O
The following f i gure shows the analog in put structure, ex cept for ADCL.
1Ω
6.0V
6.0V
Analog input
PIN
AVSS
Analog Circuit
VDDCAP(1.8V)
Figure 22. Analog input
The following f i gure shows the ADCL input structure.
1Ω
6.0V
6.0V
Analog input
PIN
AVSS
Analog Circuit
VDDCAP(1.8V)
8.4 kΩ
37.8 kΩ
VDD1 (3.3V)
Figure 23. ADCL pin input structure
The following f i gure sh ows all analog op erat i onal amplifier out put pins and AREF pin I/O structure.
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6.0V
6.0V
Analog output
PIN
AVSS
Analog Circuit
VDDCAP(1.8V)
Figure 24 Analog operational am plifier output and AREF I/O struc ture
The following f i gure shows the VSS,AVSS pin I/O structure
PIN
VDD1
AVDD
6.0V
Figure 25. VSS,AVSS pin I/O structure
The following f i gure shows the VDD1,VDDCAP pin I/O st ructure
PIN
VSS
6.0V
Figure 26. VDD1,VDDCAP pin I/O structure
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8 Pin List
Pin
Number
Pin Name
Internal Pull-
up /Pull-down
Pin
Type
Description
1
XTAL0
I
Crystal input
2
XTAL1
O
Crystal output
3
P1.0/T2
I/O
Discrete programm able I/O or Tim er/Counter 2 input
4
SCL/SO-SI
I/O
I2C clock output (ope n drain, need pull up) or SPI data
5
SDA/CS0
I/O
I2C data (open drain, need pull up) or SP I Chip Select
0
6
P1.3/SYNC/SCK
I/O
Discrete programm able I/O or S Y NC output or SPI
clock output
7
P1.4/CAP
I/O
Discrete programm able I/O or Capt ure timer input
8
P1.6
I/O
Discrete programm able I/O
9
P1.7
Discrete programm able I/O
10
VDD1
P
3.3V digital power
11
VSS
P
Digital common
12
VDDCAP
P
Internal 1.8V output, Capacitor(s) to be conne ct ed
13
P2.0/NMI
I/O
Discrete programm able I/O or Non-maskable Inter rupt
input
14
P3.2/INT0
I/O
Discrete programm able I/O or I nterrupt 0 input
15
P2.2
I/O
Discrete programm able I/O
16
P2.3
I/O
Discrete programm able I/O
17
P2.6/AOPWM0
I/O
Discrete programm able I/O or P WM 0 digital output
18
P2.7/AOPWM1
I/O
Discrete programm able I/O or P WM 1 digital output
19
OP1O
O
Op amp output for appl i cation sensing, 0-1.2V range
20
OP1-
I
Op amp negative input for applicati on sensing, 0-1.2V
range, needs t o be pul l ed down to AVSS if unused
21
OP1+
I
Op amp positiv e input for application sensing, 0-1.2V
range, needs t o be pul l ed down to AVSS if unused
22
VDCBUS
I
Analog input channel (0 – 1.2V), allocated for DC bus
voltage input, needs to be pulled down to A VSS if
unused
23
AIN1
I
Analog input channel 1, 0-1.2V range, need s to be
pulled down to AV SS if unused
24
AIN2
I
Analog input channel 2, 0-1.2V range, need s to be
pulled down to AV SS if unused
25
AIN3
I
Analog input channel 3, 0-1.2V range, need s to be
pulled down to AV SS if unused
26
AIN4
I
Analog input channel 4, 0-1.2V range, need s to be
pulled down to AV SS if unused
27
ADCH
I
Input, Analog i nput channel dedicated f or A/D
compensation (0 – 1.2V), needs to be pulled down to
AVSS if unused
28
OP2-
I
Op amp negative input for applicati on sensing, 0-1.2V
range, needs t o be pul l ed down to AVSS if unused
29
OP2+
I
Op amp positiv e input for application sensing, 0-1.2V
range, needs t o be pul l ed down to AVSS if unused
30
OP2O
O
Op amp output for appl i cation sensing, 0-1.2V range
31
CMEXT
O
Unbuffered 0.6V output. Capacitor needs to be
connected.
32
AREF
O
Analog reference voltage output (0. 6V)
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Pin
Number
Pin Name
Internal Pull-
up /Pull-down
Pin
Type
Description
33
ADCL
I
Input, Analog i nput channel dedicated f or A/D
compensation (0 – 1.2V), internall y biased to 0.6V , see
Figure 23 for internal st ruct ure
34
OP3-
I
Op amp negative input for applicati on sensing, 0-1.2V
range, needs t o be pul l ed down to AVSS if unused
35
OP3+
I
Op amp positiv e input for application sensing, 0-1.2V
range, needs t o be pul l ed down to AVSS if unused
36
OP3O
O
Op amp output for appl i cation sensing, 0-1.2V range
37
AVSS
P
Analog common
38
VDDCAP
P
Internal 1.8V output, Capacitor(s) to be conne ct ed
39
VDD1
P
3.3V digital power
40
VSS
P
Digital common
41
P3.1/AOPWM2
I/O
Discrete programm able I/O or PWM 2 digital output
42
PWMWL
58 kΩ Pull
down
O
PWM gate driv e for phase W low side, conf i gurable
either high or low t rue.
43
PWMVL
58 kΩ Pull
down
O
PWM gate driv e for phase V low side, configurable
either high or low t rue
44
PWMUL
58 kΩ Pull
down
O
PWM gate driv e for phase U low side, configurable
either high or low t rue
45
PWMWH
58 kΩ Pull
down
O
PWM gate driv e for phase W high side, conf i gurable
either high or low t rue
46
P3.7
I/O
Discrete programm able I/O
47
P2.1
I/O
Discrete programm able I/O
48
PWMVH
58 kΩ Pull
down
O
PWM gate driv e for phase V high side, confi gurable
either high or low t rue
49
PWMUH
58 kΩ Pull
down
O
PWM gate driv e for phase U high side, conf igurable
either high or low t rue
50
P1.5
I/O
Discrete programm able I/O.
51
PFCPWM
I/O
PFC PWM gate drive , configurable either high or low
52
PFCGKILL
70 kΩ Pull up
I
PFCPWM shutdow n i nput, active low input.
53
GATEKILL
70 kΩ Pull up
I
PWM shutdown inp ut, configurable digital f ilter, active
low input.
54
P3.0/INT2/CS1
70 kΩ Pull up
I/O
Discrete programm able I/O or ex ternal interrupt 2 input
or SPI Chip Select 1
55
P5.2/TMS
I
JTAG test mode sel ect or digital input port
56
TDO
O
JTAG test data out put
57
P5.1/TDI
I
JTAG test data input or digital input port
58
TCK
I
JTAG test clo ck
59
RESET
I
Reset, low true, S chmi tt trigger input
60
P1.1/RXD
I/O
UART receiver input or Discrete prog rammable I/O
61
P1.2/TXD
I/O
UART transmi tter output or Discret e programmable I/O
62
P3.4/T0
I/O
Discrete programm able I/O or Tim er/Counter 2 input
63
P3.5/T1
I/O
Discrete programm able I/O or Tim er/Counter 2 input
64
P3.3/INT1
I/O
Interrupt 1 input or Discrete I/O
Table 22. Pin List
IRMCF188
37 www.irf.com © 2014 International Rectifier Submit Dat as heet Feedback M ay 28, 2014
10 Part Marking Information
IRMCF188
YWWP XXXXXX
IR Logo
Production Lot
Date Code
Part Number
Pin 1
Indentifier
11 Qualificati on Information
Qualification Level Industrial
††
(per JEDEC JESD 47E)
Moisture Sensitivity Level MSL3
†††
(per IPC/JEDEC J-STD-020C)
ESD Machine Model Class B
(per JEDEC standar d JE SD22-A114D)
Human Body Model Class 2
(per EIA/JEDEC standard EIA/JESD22-A115-A)
RoHS Compliant Yes
†
Qualificat ion standards can be found at I nternational Rectifier’s web site http://www.irf.com/
††
Higher qualif icat ion rat ings ma y be avail able should the user h ave suc h r equireme nts. Pleas e cont act
your International Rectif i er sales represent ative for further information.
†††
Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further inform ation.
Note: Test condition for Temperat ure Cycling test is -40C t o 125C.
IRMCF188
38 www.irf.com © 2014 International Rectifier Submit Dat as heet Feedback M ay 28, 2014
Data and Specifications are subject to change without notice
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, C ali fornia 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at ww w.irf.com for sales contact information
