1
®
FN8169.5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9259
Single Supply/Low Power/256-Tap/2-Wire bus
Quad Digitally-Controlled (XDCP™)
Potentiometers
The X9259 integrates four digitally controlled potentiometers
(XDCP) on a monolithic CMOS integrated circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
2-wire bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and four
non-volatile Data Registers that can be directly written to and
read by the user. The content of the WCR controls the
position of the wiper. At power-up, the device recalls the
content of the default Data Registers of each DCP (DR00,
DR10, DR20, and DR30) to the corres ponding WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Features
• Four Separate Potentiometers in One Package
• 256 Resistor Taps–0.4% Resolution
• 2-Wire Serial Interface for Write, Read, and
Transfer Operations of the Potentiometer
• Wiper Resistance: 100Ω typical @ VCC = 5V
• 4 Non-volatile Data Registers for Each Potentiometer
• Non-volatile S torage of Multiple Wiper Positions
• Standby Current <5µA Max
•V
CC: 2.7V to 5.5V Operation
•50kΩ, 100kΩ versions of Total Resistance
• Endurance: 100,000 Data Changes per Bit per Register
• 100 year Data Retention
• Single Supply Version of X9258
• 24 Ld SOIC, 24 Ld TSSOP
• Low Power CMOS
• Pb-Free Plus Anneal Available (RoHS Compliant)
Functional Diagram
POWER UP,
INTERFACE
CONTROL
AND
VCC
VSS
2-Wire
RH0
RL0
DCP0
RW0
A1
SDA
SCL
A3
A2
WP
WCR0
DR00
DR01
DR02
DR03
RH1
RL1
DCP1
RW1
WCR1
DR10
DR11
DR12
DR13
RH2
RL2
DCP2
RW2
WCR2
DR20
DR21
DR22
DR23
RH3
RL3
DCP3
RW3
WCR3
DR30
DR31
DR32
DR33
A0
Interface
STATUS
Data Sheet April 13, 2007
2FN8169.5
April 13, 2007
Ordering Information
PART
NUMBER PART MARKING VCC LIMITS
(V) RTOTAL
(kΩ)
TEMPERATURE
RANGE
(°C) PACKAGE PKG. DWG. #
X9259TS24 X9259TS 5 ±10% 100 0 to +70 24 Ld SOIC M24.3
X9259TS24Z (Note) X9259TS Z 0 to +70 24 Ld SOIC (Pb-free) M24.3
X9259TS24I X9259TS I -40 to +85 24 Ld SOIC M24.3
X9259TS24IZ (Note) X9259TS ZI -40 to +85 24 Ld SOIC (Pb-free) M24.3
X9259TV24I X9259TV I -40 to +85 24 Ld TSSOP MDP0044
X9259TV24IZ (Note) X9259TV ZI -40 to +85 24 Ld TSSOP (Pb-free) MDP0044
X9259US24* X9259US 50 0 to +70 24 Ld SOIC M24.3
X9259US24Z* (Note) X9259US Z 0 to +70 24 Ld SOIC (Pb-free) M24.3
X9259US24I X9259US I -40 to +85 24 Ld SOIC M24.3
X9259US24IZ (Note) X9259US ZI -40 to +85 24 Ld SOIC (Pb-free) M24.3
X9259UV24I* X9259UV I -40 to +85 24 Ld TSSOP MDP0044
X9259UV24IZ* (Note) X9259UV Z I -40 to +85 24 Ld TSSOP (Pb-free) MDP0044
X9259TS24-2.7* X9259TS F 2.7 to 5.5 100 0 to +70 24 Ld SOIC M24.3
X9259TS24Z-2.7* (Note) X9259TS ZF 0 to +70 24 Ld SOIC (Pb-free) M24.3
X9259TS24I-2.7 X9259TS G -40 to +85 24 Ld SOIC M24.3
X9259TS24IZ-2.7 (Note) X9259TS ZG -40 to +85 24 Ld SOIC (Pb-free) M24.3
X9259TV24-2.7 X9259TV F 0 to +70 24 Ld TSSOP MDP0044
X9259TV24Z-2.7 (Note) X9259TV ZF 0 to +70 24 Ld T SSOP (Pb-free) MDP0044
X9259US24-2.7 X9259US F 50 0 to +70 24 Ld SOIC M24.3
X9259US24Z-2.7 (Note) X9259US ZF 0 to +70 24 Ld SOIC (Pb-free) M24.3
X9259US24I-2.7 X9259US G -40 to +85 24 Ld SOIC M24.3
X9259US24IZ-2.7 (Note) X9259US ZG -40 to +85 24 Ld SOIC (Pb-free) M24.3
X9259UV24-2.7* X9259UV F 0 to +70 24 Ld TSSOP MDP0044
X9259UV24Z-2.7 (Note) X9259UV ZF 0 to +70 24 Ld TSSOP (Pb-free) MDP0044
X9259UV24I-2.7* X9259UV G -40 to +85 24 Ld TSSOP MDP0044
X9259UV24IZ-2.7* (Note) X9259UV ZG -40 to +85 24 Ld TSSOP (Pb-free) MDP0044
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
*Add "T1" suffix for tape and reel.
X9259
3FN8169.5
April 13, 2007
Circuit Level Applications
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier
circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback
circuits
System Level Applications
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless
systems
• Set the operating points in te mperature control
systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
Pin Configuration
Pin Assignments
PIN
(SOIC/
TSSOP) SYMBOL FUNCTION
2 A0 Device Address for 2-Wire bus. (See Note 1)
3R
W3 Wiper Terminal of DCP3
4R
H3 High Terminal of DCP3
5R
L3 Low Terminal of DCP3
6 NC1 Must be left unconnected
7V
CC System Supply Voltage
8R
L0 Low Terminal of DCP0
9R
H0 High Terminal of DCP0
10 RW0 Wiper Terminal of DCP0
1 1 A2 Device Address for 2-Wire bus. (See Note 1)
12 WP Hardware Write Protect – Active Low
13 SDA Serial Data Input/Output for 2-Wire bus.
14 A1 Device Address for 2-Wire bus. (See Note 1)
15 RL1 Low Terminal of DCP1
16 RH1 High Terminal of DCP1
17 RW1 Wiper Terminal of DCP1
18 VSS System Ground
20 RW2 Wiper Terminal of DCP2
21 RH2 High Terminal of DCP2
22 RL2 Low Terminal of DCP2
23 SCL Serial Clock for 2-Wire bus.
24 A3 Device Address for 2-Wire bus. (See Note 1)
6, 19 NC No Connect
1 DNC Do Not Connect
Note 1: A0 through A3 Device address pins must be tied to a logic
level.
DNC
A0
RW3
NC
VCC
RL0
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
A3
SCL
RL2
RH2
RW2
NC
VSS
RW1
RH1
RL1
SOIC/TSSOP
X9259
RH3
14
13
11
12
RL3
RH0
RW0
A2 A1
SDA
WP
X9259
4FN8169.5
April 13, 2007
Pin Descriptions
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for a 2-
Wire slave device and is used to transfer data into and out of
the device. It receives device address, opcode, wiper
register address and data sent from a 2-Wire master at the
rising edge of the serial clock SCL, and it shifts out data af ter
each falling edge of the serial clock SCL.
It is an open drain output and may be wire-ORed with any
number of open drain or open collector outputs. An open
drain output requires the use of a pull-up resistor.
SERIAL CLOCK (SCL)
This input is used by 2-Wire master to supply 2-Wire serial
clock to the X9259.
DEVICE ADDRESS (A3 THROUGH A0)
The Address inputs are used to set the least significant 4 bits
of the 8-bit slave address. A match in the slave address
serial data stream must be made with the Address input in
order to initiate communication with the X9259. A maximum
of 16 devices may occupy the 2-Wire serial bus. Device pins
A3 through A0 must be tied to a logic level which speci fie s
the external address of the device, see Figures 3, 4, and 5.
Potentiometer Pins
RH, RL
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer. Since there are
4 potentiometers, there are 4 sets of RH and RL such that
RH0 and RL0 are the terminal s of DCP0 and so on.
RW
The wiper pin are equivalent to the wipe r terminal of a
mechanical potentiometer . Since there are 4 potentiometers,
there are 4 sets of RW such that RW0 is the terminal of
DCP0 and so on.
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (VSS)
The VCC pin is the system supply voltage. The VSS pin is
the system ground.
Other Pins
NO CONNECT
No connect pins should be left open. This pins are used for
Intersil manufacturing and testing purposes.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents non-volatile writes to the
Data Registers.
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
DR#0
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
COUNTER
REGISTER
INC/DEC
LOGIC
UP/DN
CLK
MODIFIED SCK
UP/DN
8 8
COUNTER
IF WCR = 00[H] then RW is closest to RL
IF WCR = FF[H] then RW is closest to RH
WIPER
(WCR#)
#: 0, 1, 2, or 3
One of Four Potentiometers
DR#2
DR#1
DR#3
- - -
DECODE
DCP
CORE RW
RH
RL
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
X9259
5FN8169.5
April 13, 2007
Principles of Operation
The X9259 is an integrated circuit incorporating four DCPs
and their associated registers and counters, and the serial
interface providing direct communication between a host
and the potentiometers.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanica l
potentiometer (RH and RL pins). The RW pin is an
intermediate node, equivalent to the wiper terminal of a
mechanical potentiometer.
The position of the wiper terminal within the DCP is
controlled by an 8-bit volatile Wip er Counter Register
(WCR).
Power Up and Down Recommendations
There are no restrictions on the power-up or power-down
conditions of VCC and the voltages applied to the
potentiometer pins provid ed that VCC is always more
positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL,
VW. The VCC ramp rate specification is always in effect.
Wiper Counter Register (WCR)
The X9259 contains four Wiper Counter Registers, one for
each potentiometer. The Wiper Counter Register can be
envisioned as a 8-bit parallel and serial load counter with its
outputs decoded to select one of 256 wiper positions along
its resistor array. The contents of the WCR can be altered in
four ways: it may be written directly by the host via the Write
Wiper Counter Register instruction (se rial load); it may be
written indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register
instruction (parallel load); it can be modified one step at a
time by the Inc rement/Decrement i nstruction (see Inst ruction
section for more details). Finally, it is loaded with the
contents of its data register zero (DR#0) upon power-up.
(See Figure 1)
The Wiper Counter Register is a volatile register; that is, its
contents are lost when the X9259 is powered-down.
Although the register is automatically loaded with th e value
in DR#0 upon power-up, this may be different from the value
present at power-down. Power-up guidelines are
recommended to ensure proper loadings of the DR#0 value
into the WCR# (See Design Considerations Section).
Data Registers (DR)
Each of the four DCPs has four 8-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four data
registers and the associated Wiper Counte r Register. All
operations changing data in one of the data registers is a
non-volatile operation and takes a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.
Bit [7:0] are used to store one of the 256 wiper positions
(0 ~ 255).
TABLE 1. WIPER COUNTER REGISTER, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile).
TABLE 2. DATA REGISTER, DR (8-BIT), BIT [7:0]: Used to store wiper positions or data (Non-volatile).
WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0
(MSB) (LSB)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(MSB) (LSB)
X9259
6FN8169.5
April 13, 2007
Serial Interface
The X9259 supports a bidirectio nal bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver .
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provide the clock for both
transmit and receive operations. Therefore, the X9259
operates as a slave device in all applications.
All 2-wire interface operations must begin with a START,
followed by an Identification Byte, that selects the X9259. All
communication over the 2-wire interface is conducted by
sending the MSB of each byte of data first.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions. See
Figure 2. On power up of the X9259 the SDA pin is in the
input mode.
START Condition
All commands to the X9259 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The X9259 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met. See
Figure 2.
STOP Condition
All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH. See Figure 2. The STOP condition is also
used to place the device into the Standby Power mode after
a Read sequence. A STOP condition can only be issued
after the transmitting device has released the bus.
Acknowledge
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data. See Figure 3.
The X9259 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Instruction Byte.
The X9259 also responds with an ACK after receiving a Data
Byte after a Write Instruction.
A valid Identification Byte contains the Device T ype Identifier
0101, as the four MSBs, and the Device Address bits
matching the logic states of pins A3, A2, A1, and A0, as the
four LSBs. See Figure 4.
In the Read mode, the device transmits eight bits of data,
releases the SDA line, and then monito rs the line for an
ACK. The device continues transmitting data if an ACK is
detected. The device terminates further data transmissions if
an ACK is not detected. The master must then issue a STOP
condition to place the device into a known state.
During the internal non-volatile Write operation, the X9259
ignores the inputs at SDA and SCL, and does not issue an
ACK after Identification bytes.
X9259
7FN8169.5
April 13, 2007
Identification Byte
The first byte sent to the X9259 from the host is called the
Identification Byte. The most significan t four bits are a
Device Type Identifier, ID[3:0] bits, which must be 0101.
Refer to Tab le 3.
Only the device which Slave Address matches the incoming
device address sent by the master executes the instruction.
The A3 - A0 inputs can be actively driven by CMOS input
signals or tied to VCC or VSS.
INSTRUCTION BYTE (I)
The next byte sent to the X9259 contains the instruction and
register pointer information. The four most significant bits are
used provide the instruction opcode I [3:0]. The RB and RA
bits point to one of the four data registers of each associated
XDCP. The least two significant bits point to one of four
Wiper Counte r Re gisters or DCPs. The format is sh ow n in
Table 4.
Data Register Selection
#: 0, 1, 2, or 3
The least significant four bits of the Identification Byte are
the Slave Address bits, AD[3:0]. To access the X9259, these
four bits must match the logic values of pins A3, A2, A1, and
A0.
SDA
SCL
START DATA DATA STOP
STABLE CHANGE
DATA
STABLE
FIGURE 2. VALID DATA CHANGES, START, AND STOP CONDITIONS
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
81 9
START ACK
SCL FROM
MASTER
FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER
REGISTER RB RA
DR#0 0 0
DR#1 0 1
DR#2 1 0
DR#3 1 1
X9259
8FN8169.5
April 13, 2007
TABLE 3. IDENTIFICATION BYTE FORMAT
TABLE 4. INSTRUCTION BYTE FORMAT
Note: 1/0 = data is one or zero
ID3 ID2 ID1 ID0 A3 A2 A1 A0
0 1 0 1 Logic value of pins A3, A2, A1, and A0
(MSB) (LSB)
Device Type
Identifier Slave Address
I3 I2 I1 I0 RB RA P1 P0
(MSB) (LSB)
Instruction Register DCP Selection
Opcode Selection (WCR Selection)
TABLE 5. INSTRUCTION SET
INSTRUCTION
INSTRUCTION SET
OPERATIONI3 I2 I1 I0 RB RA P1 P0
Read Wiper Counter
Register 1 0 0 1 0 0 1/0 1/0 Read the contents of the Wiper Counter Register
pointed to by P1 - P0
Write Wiper Counter Register 1 0 1 0 0 0 1/0 1/0 Write new value to the Wiper Counter
Register pointed to by P1 - P0
Read Data Register 1 0 1 1 1/0 1/0 1/0 1/0 Read the contents of the Data Register pointed to by
P1 - P0 and RB - RA
Write Data Register 1 1 0 0 1/0 1/0 1/0 1/0 Write new value to the Data Register
pointed to by P1 - P0 and RB - RA
XFR Data Register to Wiper
Counter Register 1 1 0 1 1/0 1/0 1/0 1/0 T ra nsfer t he con tents of the Dat a Re gist er po in ted to
by P1 - P0 and RB - RA to its
associated Wip e r C o u n t e r R e g i s t e r
XFR Wiper Counter Register to
Data Register 1 1 1 0 1/0 1/0 1/0 1/0 Transfer the contents of the Wiper Counter Register
pointed to by P1 - P0 to the Data Register pointed to
by RB - RA
Global XFR Data Registers to Wiper
Counter Registers 0 0 0 1 1/0 1/0 0 0 T ransfer the contents of the Data Registers pointed to
by RB - RA of all four pots to their respective Wiper
Counter Registers
Global XFR Wiper Counter
Registers to Data Register 1 0 0 0 1/0 1/0 0 0 Transfer the contents of both Wiper Counter
Registers to their respective data Registers pointed to
by RB - RA of all four DCPs
Increment/Decrement Wiper
Counter Register 0 0 1 0 0 0 1/0 1/0 Enable Increment/decrement of the Control Latch
pointed to by P1 - P0
X9259
9FN8169.5
April 13, 2007
Instructions
Four of the nine instructions are three bytes in length. These
instructions are:
•Read Wiper Counter Register – read the current wiper
position of the selected potentiometer,
•Write Wiper Counter Register – change current wiper
position of the selected potentiometer,
•Read Data Register – read the contents of the selected
Data Register;
•Write Data Register – write a new value to the selected
Data Register.
The basic sequence of the three byte instructions is
illustrated in Figure 5. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper to
this action is delayed by tWRL. A transfer from the WCR
(current wiper position), to a Data Register is a write to non-
volatile memory and takes a minimum of tWR to complete.
The transfer can occur between one of the four
potentiometer’s WCR, and one of its associated registers,
DRs; or it may occur globally, where the transfer occurs
between all potentiometers and one associated registe r.
Four instructions require a two-byte sequence to complete.
These instructions transfer data between the host and the
X9259; either between the host and one of the data registers
or directly between the host and the Wiper Counter Register .
These instructions are:
•XFR Data Register to Wiper Counter Register – This
transfers the contents of one specified Data Register to
the associated Wiper Counter Register.
•XFR Wip er Co un ter Register to Da ta Register – This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.
•Global XFR Data Register to Wiper Counter
Register – This transfers the contents of all specified Data
Registers to the associated Wiper Counter Registers.
•Global XFR Wiper Counter Register to Data
Register – This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.
Increment/Decrement Command
The final command is Increment/Decrement (Figure 6 and
7). The Increment/Decrement command is different from the
other commands. Once the command is issued and the
X9259 has responded with an Acknowledge, the master can
clock the selected wiper up and/or down in one segment
steps; thereby, providing a fine tuning capability to the host.
For each SCL clock pulse (tHIGH) while SDA is HIGH, the
selected wiper moves one wiper position towards the RH
terminal. Similarly, for each SCL clock pulse while SDA is
LOW, the selected wiper moves one resistor wiper position
towards the RL terminal.
See Instruction format for more details.
S
T
A
R
T
0101
A2 A0 A
C
K
I2 I1 I0 RB RA P1 A
C
K
SCL
SDA
S
T
O
P
ID3 ID2 ID1 ID0 P0
Device ID External Instruction
Opcode
Address Register
Address
DCP/WCR
Address
A1
A3 I3
FIGURE 4. TWO-BYTE INSTRUCTION SEQUENCE
I3 I2 I1 I0 RB RA
ID3 ID2
ID1
ID0
Device ID External Instruction
Opcode
Address Register
Address
Pot/WCR
Address
Data for WCR[7:0] or DR[7:0]
S
T
A
R
T
0101
A2 A1 A0 A
C
K
P1 P0 A
C
K
SCL
SDA
S
T
O
P
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
A3
FIGURE 5. THREE-BYTE INSTRUCTION SEQUENCE 2-WIRE INTERFACE
X9259
10 FN8169.5
April 13, 2007
I3 I2 I1 I0
ID3 ID2 ID1 ID0
Device ID External Instruction
Opcode
Address
Register
Address Pot/WCR
Address
S
T
A
R
T
0101
A2 A1 A0 A
C
K
RA P1 P0 A
C
K
SCL
SDA
S
T
O
P
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
RB
A3
FIGURE 6. INCREMENT/DECREMENT INSTRUCTION SEQUENCE 2-WIRE INTERFACE
SCL
SDA
RW
INC/DEC
CMD
Issued
Voltage Out
tWRID
FIGURE 7. INCREMENT/DECREMENT TIMING SPEC
X9259
11 FN8169.5
April 13, 2007
Instruction Format
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Write Data Register (DR)
Global XFR Data Register (DR) to Wiper Counter Register (WCR)
Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the Master/Slave.
(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/WCR
Addresses S
A
C
K
Wiper Position
(Sent by X9259 on SDA) M
A
C
K
S
T
O
P
0101A3A2A1A0 100100P1 P0
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/WCR
Addresses S
A
C
K
Wiper Position
(Sent by Master on SDA) S
A
C
K
S
T
O
P
0101A3A2A1A0 101000P1 P0
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/WCR
Addresses S
A
C
K
Wiper Position
(Sent by X9259 on SDA) M
A
C
K
S
T
O
P
01 0 1A3A2A1A0 1011RBRAP1 P0
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/WCR
Addresses S
A
C
K
Wiper Position
(Sent by Master on SDA) S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0101A3A2A1A0 1100RBRAP1 P0
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/WCR
Addresses S
A
C
K
S
T
O
P
0 1 0 1 A3 A2 A1 A0 0 0 0 1 RB RA 0 0
X9259
12 FN8169.5
April 13, 2007
Global XFR Wiper Counter Register (WCR) to Data Register (DR)
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Increment/Decrement Wiper Counter Register (WCR)
Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the Master/Slave.
(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/WCR
Addresses S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0 1 0 1A3A2A1A0 1000RBRA00
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/WCR
Addresses S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0 1 0 1A3A2A1A0 1110RBRAP1 P0
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/WCR
Addresses S
A
C
K
S
T
O
P
0 1 0 1 A3 A2 A1 A0 1 1 0 1 RB RA P1 P0
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/WCR
Addresses S
A
C
K
Increment/Decrement
(Sent by Master on SDA) S
T
O
P
0101A3A2A1A0 001000 P1 P0 I/DI/D. . . .I/DI/D
X9259
13 FN8169.5
April 13, 2007
NOTES:
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
3. MI = RTOT / 255 or (RH – RL) / 255, single pot
4. During power up VCC > VH, VL, and VW.
5. n = 0, 1, 2, …,255; m =0, 1, 2, …, 254.
Absolute Maximum Ratings Recommended Operating Conditions
Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on SCL, SDA, any address input, VCC
with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
ΔV = | (VH–VL) |. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . .300°C
IW (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Temperature (Commercial) . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Temperature (Industrial). . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (VCC) (Note 4) Limits
X9259. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ± 10%
X9259-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Wiper current ...........................................................................±3mA
Power rating (each pot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50mW
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. E xposure to ab solute maxim um
rating conditio ns for ext e nded pe rio ds may a ffe ct d evice reli abi lit y.
Analog Specificatio n s Over recommended industrial (2.7V) operating conditions unless otherwise stated.
SYMBOL PARAMETER TEST CONDITIONS
LIMITS
MIN TYP MAX UNITS
RTOTAL End to End Resistance T version 100 kΩ
RTOTAL End to End Resistance U version 50 kΩ
End to End Resistance Tolerance ±20 %
RWWiper Resistance IW = @ VCC = 3V 300 Ω
IW = @ VCC = 5V 220 Ω
VTERM Voltage on any RH or RL Pin VSS = 0V VSS VCC V
Noise (Note 6) Ref: 1V -120 dB/√Hz
Resolution 0.4 %
Absolute Linearity (Note 1) Rw(n)(actual) - Rw(n)(expected) (Note 5) -1 +1 MI (Note 3)
Relative Linearity (Note 2) Rw(n + 1) - [Rw(n) + MI] (Note 5) -0.6 +0.6 MI (Note 3)
Temperature Coefficient of RTOTAL
(Note 6) ±300 ppm/°C
Ratiometric Temp. Coefficient (Note 6) ±20 ppm/°C
CH/CL/CWPotentiometer Capacitances (Note 6) See Macro model 10/10/25 pF
V(VCC)
RTOTAL
V(VCC)
RTOTAL
X9259
14 FN8169.5
April 13, 2007
NOTES:
6. This parameter is not 100% tested
7. tPUR and tPUW are the delays required from the time the power supply (VCC) is stable until the specific instruction can be issued. These
parameters are periodically sampled and not 100% tested.
DC Electrical Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL PARAMETER TEST CONDITIONS
LIMITS
MIN TYP MAX UNITS
ICC1 VCC supply current
(active) fSCL = 400kHz; VCC = +6V;
SDA = Open; (for 2-Wire, Active, Read and
Volatile Write States only)
3mA
ICC2 VCC supply current
(non-volatile write) fSCL = 400kHz; VCC = +6V;
SDA = Open; (for 2-Wire, Active,
Non-volatile Write State only)
5mA
ISB VCC current (standby) VCC = +6V; VIN = VSS or VCC; SDA = VCC;
(for 2-Wire, Standby State only) 5μA
ILI Input leakage current VIN = VSS to VCC 10 μA
ILO Output leakage current VOUT = VSS to VCC 10 μA
VIH Input HIGH voltage VCC x 0.7 V
VIL Input LOW voltage VCC x 0.3 V
VOL Output LOW voltage IOL = 3mA 0.4 V
VOH Output HIGH voltage IOH = -1mA, VCC ≥ +3V VCC - 0.8 V
VOH Output HIGH voltage IOH = -0.4mA, VCC ≤ +3V VCC - 0.4 V
Endurance and Data Retention
PARAMETER MIN UNITS
Minimum endurance 100,000 Data changes per bit per register
Data retention 100 years
Capacitance
SYMBOL TEST MAX UNITS TEST CONDITIONS
CIN/OUT (Note 6) Input / Output capacitance (SDA) 8 pF VOUT = 0V
CIN (Note 6) Input capacitance (SCL, WP, A2, A1 and A0) 6 pF VIN = 0V
Power-up Timing
SYMBOL PARAMETER MIN MAX UNITS
tr VCC (Note 6) VCC Power-up rate 0.2 V/ms
tPUR (Note 7) Power-up to initiation of read operation 1 ms
tPUW (Note 7) Power-up to initiation of write operation 50 ms
A.C. Test Conditions
Input Pulse Levels VCC x 0.1 to VCC x 0.9
Input rise and fall times 10ns
Input and output timing level VCC x 0.5
X9259
15 FN8169.5
April 13, 2007
Equivalent A.C. Load Circuit
5V
1533Ω
100pF
SDA pin
RH
10pF
CLCL
RW
RTOTAL
CW
25pF
10pF
RL
SPICE Macromodel
AC Timing
SYMBOL PARAMETER MIN MAX UNITS
fSCL Clock Frequency 400 kHz
tCYC Clock Cycle Time 2500 ns
tHIGH Clock High Time 600 ns
tLOW Clock Low Time 1300 ns
tSU:STA Start Setup Time 600 ns
tHD:STA Start Hold Time 600 ns
tSU:STO Stop Setup Time 600 ns
tSU:DAT SDA Data Input Setup Time 100 ns
tHD:DAT SDA Data Input Hold Time 30 ns
tRSCL and SDA Rise Time 300 ns
tF SCL and SDA Fall Time 300 ns
tAA SCL Low to SDA Data Output Valid Time 0.9 μs
tDH SDA Data Output Hold Time 0 ns
TINoise Suppression Time Constant at SCL and SDA inputs 50 ns
tBUF Bus Free Time (Prior to Any Transmission) 1200 ns
tSU:WPA A0, A1 Setup Time 0 ns
tHD:WPA A0, A1 Hold Time 0 ns
High-Voltage Write Cycle Timing
SYMBOL PARAMETER TYP MAX UNITS
tWR High-voltage write cycle time (store instructions) 5 10 ms
XDCP Timing
SYMBOL PARAMETER MIN MAX UNITS
tWRPO Wiper response time after the third (last) power supply is stable 5 10 μs
tWRL Wiper response time after instruction issued (all load instructions) 5 10 μs
X9259
16 FN8169.5
April 13, 2007
Symbol Table .
Timing Diagrams
Start and Stop Timing
Input Timing
Output Timing
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
tSU:STA tHD:STA tSU:STO
SCL
SDA
tR
(START) (STOP)
tF
tRtF
SCL
SDA
tHIGH
tLOW
tCYC
tHD:DAT
tSU:DAT tBUF
SCL
SDA
tDH
tAA
X9259
17 FN8169.5
April 13, 2007
XDCP Timing (for All Load Instructions)
Write Protect and Device Address Pins Timing
SCL
SDA
VWx
(STOP)
LSB
tWRL
SDA
SCL
...
...
...
WP
A0, A1
tSU:WPA tHD:WPA
(START) (STOP)
(Any Instruction)
X9259
18 FN8169.5
April 13, 2007
Applications Information
Basic Configurations of Electronic Potentiometers
Application Circuits
VR
RW
+VR
I
Three terminal
Potentiometer;
Variable voltage divider Two terminal Variable
Resistor;
Variable current
Non inverting Amplifier Voltage Regulator
Offset Voltage Adjustment Comparator with Hysteresis
+
–
VS
VO
R2
R1
VO = (1+R2/R1)VS
R1
R2
Iadj
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
VO (REG)VIN 317
+
–
VS
VO
R2
R1
VUL = {R1/(R1+R2)} VO(max)
RLL = {R1/(R1+R2)} VO(min)
100kΩ
10kΩ10kΩ
10kΩ
-12V+12V
TL072
+
–
VSVO
R2
R1
}
}
X9259
19 FN8169.5
April 13, 2007
Application Circuits (continued)
Attenuator Filter
Inverting Amplifier Equivalent L-R Circuit
+
–
VS
VO
R3
R1
VO = G VS
-1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1
fc = 1/(2πRC)
+
–
VS
VO
R2
R1
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
+
–
VS
Function Generator
R2
R4R1 = R2 = R3 = R4 = 10kΩ
+
–
VS
R2
R1
R
C
}
}
VO = G VS
G = - R2/R1
R2
C1
R1
R3
ZIN
+
–R2
+
–
R1
}
}
RA
RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
C
VO
X9259
20 FN8169.5
April 13, 2007
X9259
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or prot rusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H0.25(0.010) BM M
α
M24.3 (JEDEC MS-013-AD ISSUE C)
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.020 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.5985 0.6141 15.20 15.60 3
E 0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N24 247
α0° 8° 0° 8° -
Rev. 1 4/06
21
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third pa rties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Intersil or its subsidiari es.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8169.5
April 13, 2007
X9259
Thin Shrink Small Outline Package Family (TSSOP)
N(N/2)+1
(N/2)
TOP VIEW
AD
0.20 C
2X B A
N/2 LEAD TIPS
B
E1
E
0.25 CAB
M
1
H
PIN #1 I.D.
0.05
e
C
0.10 C
N LEADS SIDE VIEW
0.10 CABM
b
c
SEE DETAIL “X”
END VIEW
DETAIL X
A2
0° - 8°
GAUGE
PLANE
0.25
L
A1
A
L1
SEATING
PLANE
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
SYMBOL
MILLIMETERS
TOLERANCE14 LD 16 LD 20 LD 24 LD 28 LD
A 1.20 1.20 1.20 1.20 1.20 Max
A1 0.10 0.10 0.10 0.10 0.10 ±0.05
A2 0.90 0.90 0.90 0.90 0.90 ±0.05
b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06
c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06
D 5.00 5.00 6.50 7.80 9.70 ±0.10
E 6.40 6.40 6.40 6.40 6.40 Basic
E1 4.40 4.40 4.40 4.40 4.40 ±0.10
e 0.65 0.65 0.65 0.65 0.65 Basic
L 0.60 0.60 0.60 0.60 0.60 ±0.15
L1 1.00 1.00 1.00 1.00 1.00 Reference
Rev. F 2/07
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
