TSL210 640 x 1 LINEAR SENSOR ARRAY TAOS039 - AUGUST 2002 640 x 1 Sensor-Element Organization 200 Dots-Per-Inch (DPI) Sensor Pitch High Linearity and Uniformity Wide Dynamic Range . . . 2000:1 (66 dB) Output Referenced to Ground Low Image Lag . . . 0.5% Typ Operation to 5 MHz Single 5-V Supply PACKAGE (TOP VIEW) 1 VDD 2 CLK 3 SI1 4 AO1 5 SO1 6 SI2 7 AO2 8 SO2 9 GND 10 SI3 11 AO3 12 SO3 13 SI4 14 AO4 15 SO4 16 SI5 17 AO5 18 SO5 Description The TSL210 linear sensor array consists of five sections of 128 photodiodes, each with associated charge amplifier circuitry, running from a common clock. These sections can be connected to form a contiguous 640 x 1 pixel array. Device pixels measure 120 m (H) by 70 m (W) with 125-m center-to-center pixel spacing. Operation is simplified by internal logic that requires only a serial input (SI1 through SI5) for each section and a common clock for the five sections. The device is intended for use in a wide variety of applications including contact imaging, mark and code reading, bar-code reading, edge detection and positioning, OCR, level detection, and linear and rotational encoding. Functional Block Diagram (each section) Pixel 1 Pixel 2 Integrator Reset Pixel 3 Pixel 128 Analog Bus VDD Output Amplifier _ + Sample/ Output AO GND RL (External 330 Load) Switch Control Logic Gain Trim Q1 Q2 Q3 Q128 SO CLK 128-Bit Shift Register SI The LUMENOLOGY Company Copyright 2002, TAOS Inc. Texas Advanced Optoelectronic Solutions Inc. 800 Jupiter Road, Suite 205 Plano, TX 75074 (972) 673-0759 www.taosinc.com 1 TSL210 640 x 1 LINEAR SENSOR ARRAY TAOS039 - AUGUST 2002 Terminal Functions TERMINAL NAME AO1 NO. I/O DESCRIPTION 4 O Analog output of section 1. AO2 7 O Analog output of section 2. AO3 11 O Analog output of section 3. AO4 14 O Analog output of section 4. AO5 17 O Analog output of section 5. CLK 2 I Clock input for all sections. The clock controls the charge transfer, pixel output, and reset. GND 9 SI1 3 I SI1 defines the start of the data out sequence for section 1. SI2 6 I SI2 defines the start of the data out sequence for section 2. SI3 10 I SI3 defines the start of the data out sequence for section 3. SI4 13 I SI4 defines the start of the data out sequence for section 4. SI5 16 I SI5 defines the start of the data out sequence for section 5. SO1 5 O SO1 provides the signal to drive the SI2 input in serial mode or end of data for section 1 in parallel mode. SO2 8 O SO2 provides the signal to drive the SI3 input in serial mode or end of data for section 2 in parallel mode. SO3 12 O SO3 provides the signal to drive the SI4 input in serial mode or end of data for section 3 in parallel mode. SO4 15 O SO4 provides the signal to drive the SI5 input in serial mode or end of data for section 4 in parallel mode. SO5 18 O SO5 provides the signal to drive the SI input of another device for cascading or as an end of data indication. VDD 1 Ground (substrate). All voltages are referenced to the substrate. Supply voltage for both analog and digital circuits. Detailed Description The device consists of five sections of 128 photodiodes (called pixels -- 640 total in the device) arranged in a linear array. Each section has its own signal input and output lines, and all five sections are connected to a common clock line. Light energy impinging on a pixel generates photocurrent that is then integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity on that pixel and the integration time. The voltage output developed for each pixel is according to the following relationship: Vout = Vdrk + (Re) (Ee) (tint) where: Vout Vdrk Re Ee tint is is is is is Copyright 2002, TAOS Inc. the analog output voltage for white condition the analog output voltage for dark condition the device responsivity for a given wavelength of light given in V/(J/cm2) the incident irradiance in W/cm2 integration time in seconds The LUMENOLOGY Company 2 www.taosinc.com TSL210 640 x 1 LINEAR SENSOR ARRAY TAOS039 - AUGUST 2002 The output and reset of the integrators in each section are controlled by a 128-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI. As the SI pulse is clocked through the shift register, the charge stored on the sampling capacitors of each pixel is sequentially connected to a charge-coupled output amplifier that generates a voltage on analog output AO (given above). After being read, the pixel integrator is then reset, and the next integration period begins for that pixel. On the 129th clock rising edge, the SO pulse is clocked out on SO signifying the end of the read cycle. The section is then ready for another read cycle. The SO of each section can be connected to SI on the next section in the array (Figure 4). SO can be used to signify the read is complete. AO is driven by a source follower that requires an external pulldown resistor (330- typical). The output is nominally 0 V for no light input, 2 V for normal white-level, and 3.4 V for saturation light level. When the device is not in the output phase, AO is in a high impedance state. A 0.1 F bypass capacitor should be connected between VDD and ground as close as possible to the device. The LUMENOLOGY Company Copyright 2002, TAOS Inc. www.taosinc.com 3 TSL210 640 x 1 LINEAR SENSOR ARRAY TAOS039 - AUGUST 2002 Absolute Maximum Ratings Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3V Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA to 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 mA to 25 mA Voltage range applied to any output in the high impedance or power-off state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3V Continuous output current, IO (VO = 0 to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 mA to 25 mA Continuous current through VDD or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -100 mA to 100 mA Analog output current range, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 mA to 25 mA Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25C to 85C Lead temperature on connection pad for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C ESD tolerance, human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Recommended Operating Conditions (see Figure 1 and Figure 2) Supply voltage, VDD MIN NOM 4.5 5 MAX UNIT 5.5 V Input voltage, VI 0 VDD V High-level input voltage, VIH Low-level input voltage, VIL 2 VDD V Wavelength of light source, Clock frequency, fclock Sensor integration time, serial, tint 0 0.8 400 1000 V nm 5 5000 kHz 0.128 100 ms Sensor integration time, parallel, tint Load capacitance, CL 0.026 100 ms 330 pF Load resistance, RL 300 4700 0 70 C Operating free-air temperature, TA NOTE 1: SI must go low before the rising edge of the next clock pulse. Copyright 2002, TAOS Inc. The LUMENOLOGY Company 4 www.taosinc.com TSL210 640 x 1 LINEAR SENSOR ARRAY TAOS039 - AUGUST 2002 Electrical Characteristics at fclock = 200 kHz, VDD = 5 V, TA = 25C, p = 640 nm, tint = 5 ms, RL = 330 , Ee = 18W/cm2 (unless otherwise noted) (see Note 3) PARAMETER TEST CONDITIONS MIN TYP MAX 1.6 2 2.4 0 0.05 0.15 V 20 % VOUT Analog output voltage (white, average over 640 pixels) See Note 2 VDRK Analog output voltage (dark, average over 640 pixels) Ee = 0 PRNU Pixel response nonuniformity See Note 4 Nonlinearity of analog output voltage See Note 5 0.4% Output noise voltage See Note 6 1 Re Responsivity SE Saturation exposure VSAT Analog output saturation voltage DSNU Dark signal nonuniformity IL Image lag IDD Supply current IIH High-level input current IIL Low-level input current 16 See Note 7 22 2.5 mVrms 28 V/ (J/ cm2) nJ/cm 2 3.4 0.04 V FS 155 All pixels, Ee = 0, See Note 8 See Note 9 UNIT V 0.12 V 160 mA VI = VDD 10 A VI = 0 10 A 0.5 125 IO = 50 A 4.5 % 4.95 VOH O High level output voltage High-level voltage, SO1 - SO5 VOL O Low level output voltage, Low-level voltage SO1 - SO5 Ci(SI) Input capacitance, SI 20 pF Ci(CLK) Input capacitance, CLK 50 pF IO = 4 mA 4.6 IO = 50 A 0.01 IO = 4 mA 0.4 V 0.1 V NOTES: 2. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm. 3. Clock duty cycle is assumed to be 50%. 4. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the device under test when the array is uniformly illuminated. 5. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent of analog output voltage (white). 6. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period. 7. Minimum saturation exposure is calculated using the minimum Vsat, the maximum Vdrk, and the maximum Re. 8. DSNU is the difference between the maximum and minimum output voltage in the absence of illumination. 9. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after a pixel is exposed to a white condition followed by a dark condition: IL V out (IL) V drk V out (white) V drk 100 Timing Requirements (see Figure 1 and Figure 2) MIN tsu(SI) Setup time, serial input (see Note 10) th(SI) Hold time, serial input (see Note 10 and Note 11) tw tr, tf NOM MAX UNIT 20 ns 0 ns Pulse duration, clock high or low 50 ns Input transition (rise and fall) time 0 500 ns NOTES: 10. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns. 11. SI must go low before the rising edge of the next clock pulse. The LUMENOLOGY Company Copyright 2002, TAOS Inc. www.taosinc.com 5 TSL210 640 x 1 LINEAR SENSOR ARRAY TAOS039 - AUGUST 2002 Dynamic Characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figure 2) PARAMETER TEST CONDITIONS Analog output settling time to 1% ts MIN CL = 10 pF TYP 185 MAX UNIT ns TYPICAL CHARACTERISTICS CLK SI1 IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIII IIIIIII 129 Clock Cycles AO Hi-Z Hi-Z Figure 1. Timing Waveforms (each section) tw 1 2 128 129 5V 2.5 V CLK 0V tsu(SI) 5V SI 50% 0V th(SI) ts AO ts Pixel 1 Pixel 128 Figure 2. Operational Waveforms (each section) Copyright 2002, TAOS Inc. The LUMENOLOGY Company 6 www.taosinc.com TSL210 640 x 1 LINEAR SENSOR ARRAY TAOS039 - AUGUST 2002 TYPICAL CHARACTERISTICS PHOTODIODE SPECTRAL RESPONSIVITY 1 TA = 25C Normalized Responsivity 0.8 0.6 0.4 0.2 0 300 400 500 600 700 800 900 1000 1100 - Wavelength - nm Figure 3 The LUMENOLOGY Company Copyright 2002, TAOS Inc. www.taosinc.com 7 TSL210 640 x 1 LINEAR SENSOR ARRAY TAOS039 - AUGUST 2002 APPLICATION INFORMATION TSL210 TSL210 SERIAL PARALLEL 1 VDD 1 VDD 2 CLK 2 CLK Input 3 SI1 3 SI1 Output 4 AO1 Input 4 AO1 5 SO1 5 SO1 6 SI2 6 SI2 7 AO2 7 AO2 8 SO2 8 SO2 9 GND 9 GND 10 SI3 10 SI3 11 AO3 11 AO3 12 SO3 12 SO3 13 SI4 13 SI4 14 AO4 14 AO4 15 SO4 15 SO4 16 SI5 16 SI5 17 AO5 17 AO5 18 SO5 18 SO5 Output 1 Output 2 Output 3 Output 4 Output 5 RL 330 RL 330 Figure 4. Connection Diagrams Copyright 2002, TAOS Inc. The LUMENOLOGY Company 8 www.taosinc.com TSL210 640 x 1 LINEAR SENSOR ARRAY TAOS039 - AUGUST 2002 MECHANICAL INFORMATION SIDE VIEW 22.30 21.80 TOP VIEW 4.01 3.81 Pin 1 17 18 2.54 0.69 0.53 2 2.29 12.95 12.45 6.15 5.64 89.92 89.66 47.46 47.20 Pixel 1 94.125 93.875 Pixel 640 SIDE VIEW CROSS SECTION Cover Glass 0.69 3.30 3.05 1.22 0.97 Bonded Die NOTES: A. B. C. D. Bypass Capacitor All linear dimensions are in millimeters. Pixel centers are located along the center line of the mounting holes. Cover glass index of refraction is 1.52. This drawing is subject to change without notice. Figure 5. TSL210 Mechanical Specifications The LUMENOLOGY Company Copyright 2002, TAOS Inc. www.taosinc.com 9 TSL210 640 x 1 LINEAR SENSOR ARRAY TAOS039 - AUGUST 2002 PRODUCTION DATA -- information in this document is current at publication date. Products conform to specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard warranty. Production processing does not necessarily include testing of all parameters. NOTICE Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems. TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER'S RISK. LUMENOLOGY is a registered trademark, and TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are trademarks of Texas Advanced Optoelectronic Solutions Incorporated. Copyright 2002, TAOS Inc. The LUMENOLOGY Company 10 www.taosinc.com