UPC CMOS LSI SM8210S Signal Processor for Paging Receivers NIPPON PRECISION CIRCUITS LTD. OVERVIEW PINOUT The SM8210S is a signal processor for paging ~ receivers using the POCSAG (Post Office Code xt 9] vob Standardization Advisory Group) coding system. asi [2 [17] SywvAL The POCSAG coding system conforms to CCIR ps2 [3 18] AXCLK . recommendation 584 concerning standard interna- asa [a fis] apover tional wireless calling codes. rest [s| SMez10S [ra] vss The SM8210S can receive messages containing Testa | [13] stein tone, numeric and character data, and supports both mxeik [7 12] BACKUP 512 and 1200 bps data rates. TxoaTa [a [11] RXDATA The SM8210S uses an intermittent reception tech- BREAK | jie] ST nique that reduces power consumption, extending battery life. The SM8210S operates from a 3 V supply and is available in 18-pin SOPs. FEATURES * POCSAG coding system support * Battery saving mode Six main addresses * 2A extension addresses * Tone, numeric and character data capability * Automatic correction of one- or two-bit burst errors 512 and 1200 bps data rates 25 to 75% duty cycle data capability when preamble pattern is detected - Low-power Molygate CMOS process * 5 pA (typ) current consumption in preamble mode, and 3 WA (typ) in lock, idle and switch ON modes * 3 V supply 18-pin SOPs PACKAGE DIMENSIONS Unit: mm SOP18 41.4240.3 eer RRARRRARBEA T O HHEHEEHEE } oot yp | bom 0.4 #0.1 _. 4.27402 NIPPON PRECISION CIRCUITS1CMOS LSI SM8210S BLOCK DIAGRAM RST BACKUP BREAK BS1 BS2 BS3 XT _+ Timing control +l AXCLK TXCLK H> Flag and /}-+ll ADDDET address register | Data comparator TXDATA BbH> [+> SYNVAL Received data Preamble, synchronization register and idle codes SIGIN | Digital PLL Error correction t-Ph -RXDATA VDD , VSS i. | | TESTI TEST2 PIN DESCRIPTION Number Name Description 1 XT External 76.8 kHz clock input 2 BSt RF circuitry battery control signal output 1 3 BS2 RF circuitry battery control signal output 2 4 BS3 PLL lock-up stabilization signal output 5 TEST Test input. This pin should be left open for normal! operation. 6 TEST2 Test inpul. This pin should be left open for normal operation. 7 TXCLK ID data read clock input 8 TXDATA ID data input 9 BREAK Message transfer halt input 10 RST Reset input 11 RXDATA Reosive daia output 12 BACKUP Power-save mode control input 13 SIGIN NRZ signal input 14 VSS Ground 15 ADDDET Address received detecior output 16 RXCLK Receive data clock output NIPPON PRECISION CIRCUITS2CMOS LS! SM8210S Number Name Description 17 SYNVAL Sync word received detector output 18 VDD 3 V supply SPECIFICATIONS Absolute Maximum Ratings Parameter Symbo] Rating Unit Supply voltage range Vpp 0.3 to 7.0 V Input voltage range vi 0.3 to Vpp + 0.3 V Power dissipation Pp . 250 mW Operating temperature range Top 20 to 70 deg. C Storage temperature range Tatg 40 to 125 _ deg. C Soldering temperature Tsip 260 deg. C Soldering time tsip 10 s Recommended Operating Conditions T. = 25 deg. C Parameter Symbol} Rating Unit Supply voltage / Vpp 3 V Supply voltage range Vop 25 to 35 V Electrical Characteristics Vop = 2.5 to 3.5 V, Vss = 0 V, Ti = 20 to 70 deg. C Rating Parameter Symbol Condition Unit min typ max XT = 76.8 kHz. Lock, idle and switch ON modes - 3.0 6.0 Supply current lbp pA XT = 76.8 kHz, preamble _ mode 5.0 10.0 Standby supply current loos Ta = 25 deg. C - - 1.0 pA LOW-ievel input voltage Vit - - 0.2Vpp V HiGH-level input voltage Vin 0.8Vpo - _ V LOW-level output voliage Vor lo. = 20 pA - - 0.4 V HiGH-level output voltage Vou lon = -20 pA Vop 0.1 - - V Input leakage current lu Vi = Von or Vss - - +1.0 pA NIPPON PRECISION CIRCUITS3Timing Characteristics CMOS LSI SM8210S Vpop = 2.5 to 3.5 V, Vss = 0 V, T. = 20 to 70 deg. C Rating Parameter Symbol Condition Unit min typ max Transmit clock pulsewidth ipwrx 13 - 100 HS Transmit clock cycle time tovrx 450 - - ps Transmit data setup time tstx 1.0 - - ps Transmit data hold time turx 1.0 - ~ ps 76.8 250 76.8 +250 XT pulse f 76.8 kHz pulse frequency toyxt ppm ppm XT pulse duty cycle Dx 25 - 75 % BREAK pulsewidth tewor 13 - - us Receive clock cycle time. 512 bps 7 1953 7 See note leynx ys , 1200 bps _ 833 - Receive clock pulsewidth, 512 bps a 124 ~ See note tex us , 1200 bps - 52 - 512 bps - 1341 - Receive data lead time. See note. tsrx us 1200 bps - 573 - 512 bps - 488 - Receive data hold time. See note. turx ps , 1200 bps - 208 - Note Values vary slightly due to the operation of the intemal, digital PLL. tewrx teyrx TXCLK | | | istx-+4 bo tiitx TXDATA = L xX tpwrx RXCLK tovax RXDATA = NIPPON PRECISION CIRCUITS4CMOS LSI SM8210S FUNCTIONAL DESCRIPTION Operating Flow The overall operation of the SM8210S is outlined and 3. The main features and functions are dis- in the operating flow chart shown in figures 1, 2 cussed below. { Switch on ) { Preamble ) { idle Bit clock counter reset (T=0) BSs3 F Output timing Br clock count, T=T+1 BS3="HIGH" BS1t=BS3="HIGH" After 51/67/82 ms BS1=BS2="HIGH I After 15.6 (15.0) ms BS2="LOW* RST = "HIGH" T Preamble pattern detection NO BS1=BS3="LOW, Synchronization TXCLK counter code detection teset (T=0) YES NO Just after transfer from lock mode TXCLK count, ; T=T+1, Rate error ID code flag NO YES Preamble pattem detection YES YES ID code flag set BS3="HIGH After 51/67/82 ms BS1=BS2="HIGH* 1 i After 15.6 (15,0) ms BsostoWw BS1=BS3="LOW" | Synchronization code detection SYNVAL="HIGH" \ Preamble Ne Lock Preamble Figure 1. Switch ON, preamble and idle mode flow Note Data given refers to a baud rate of 512 bps. Data given in parentheses () refers to a baud rate of 1200 bps. NIPPON PRECISION CIRCUITSS5CMOS LSI SM8210S Rete: trame & "0" NO Reterence frame = "0" Reference BS1={BS3="LOW" 15.6 (15.0) ms belore reference trame BS1={"HIGH", 51/67/82 ms betore that BS3={"HIGH" frame = "1" of 2* -+J Yes BS1=<LOW 15.6 (15.0) ms before reference trame BS1="HIGH" Reference address NO Message received flag = "0" Synchronization code timing Frame timing > reference frame detection YES Message received flag = "1" ADDDET="HIGH address information transmitted Synchronization code YES Reference frame = "7" 512 bps timing NO Reterence trame timing Message/address. BS1={8S3={"LOW" 15.6 (15.0) ms before synchronization code timing, BS1="HIGH", 1/67/82 ms before that BS3="HIGH" Reference frame = 6 Frame timing = "6" of 7* YES BS1="LOW" 15.6 (15.0) ms before synchronizat timing, BS1={"HIGH" lon code Message transmission Figure 2, Lock mode flowchart NIPPON PRECISION CIRCUITS6CMOS LS! SM8210S (| BREAK input } 5 12 bps 1200 bps Within 2 bits of BREAK detection, message received flag = 0, message transmission Ans Baud rate 12/1200 Frame timing = Frame timing = teterence frame reference trame YES Frame timing = reference frame Frame timing > reference frame 2 Wait for the next code word NO Synchronization code detection NO YES | SYNVAL="HIGH" | SYNVAL="HIGH" Preamble pattem detection Message received Tha 4" Message received flag Oo *o BS1=8S3="LOW" Figure 3. Lockmode flowchart (continued) NIPPON PRECISION CIRCUITS7CMOS LSI SM8210S Data Format The format of the received data is as per CCIR prises preamble and synchronization code words RPC No. 1 (POCSAG). The received data com- and data frames as shown in figure 4. Preamble First batch Succeeding sc sc t syne code word 1 frame (2 code words) 11010101010... | sc | 1 | 2 | 3 | 4 | 5 | 6 | 7 8 it I | J { I i I Alternating *1" and "0 ; for the lowest 576 bis { code word (32 vo | a Figure 4. Data format Synchronization code word The synchronization code word allows the consists of a 31-bit M-type pattern followed by a synchronization of the succeeding data words. Jt single even-parity bit as shown in table 1. Table 1. Synchronization code word Bit No. i Data 0 Bit No. 17 Data 0 Address and message signal code words Each code word comprises 32 bits, divided into * A message field several fields as shown in table 2. The fields com- A BCH (31, 21) check code, in the form BCH prise the following. (n, k) where n is the code length and k is the * One bit (msb) to distinguish between the address number of data bits word and the message word An even-parity bit An address corresponding to the call number _ assigned to the subscribers receiver Two function bits Table 2. Data frame configuration Bit number Data type 1 (msb) 2 to 19 20 to 21 22 to 3t 32 (Isb) Address code word 0 Address field Function bits Check bits Even-parity bit Message code word 1 Message field Check bits Even-parity bit Table 3. Function bits Table 3. Function bitscontinued Function Bit 20 Bit 21 Function Bit 20 Bit 21 A call 0 0 C call 1 0 B call 0 1 D call 1 | NIPPON PRECISION CIRCUITS8CMOS LSI SM8210S Call number and code conversion The call number is converted into an address signal (call code) by expanding the 7-digit decimal call number into a 21-bit binary call code. The frame type is defined by the three least-significant bits of the call code, Fl to F3. The call code is then written into the ID-ROM. 7-digil decimal call number (cap code) msb PEEEEET Binary conversion i 2 3 Tele EEE 17 | 18 | 19 | 20 | 21 Frame discriminator pattern | 1 Bits 2 to 19 (18 bits) 20 | 241 | Bits 22 to 34 (10 bits) ia Flag 4? Address 1: Message Function bits ->] _ Parity check bits for bits 1 to 24 _| Even parity bit (determined by bits 1 to 31) Figure 5, Call number and call code The identifier flag (bit 1) is set to zero to indicate that this is an address word. Bits 2 to 19 are the Table 4. Frame type codes Frame type Frame 0 Frame 1 Frame Frame Frame Frame Frame Frame idie word An idle word can be inserted into either the address or message word to indicate that the word contams no information. The idle word bit pattern is shown in table 5. Message reception is halted when the receiver detects an idle word. Table 5. Idle code word Bit No. Data Bit No. Data 18-bit call code, and bits 20 and 21 are the function bits. Frame code F2 0 0 In pager systems that send numeric data, the num- ber of frames varies with the type of message being sent. In this case, an idle signal is transmitted to indicate completion of the message. NIPPON PRECISION CIRCUITS9CMOS LSI SM8210S Received signal duty cycie The preamble signal, an alternating pattern of 0 and 1 bits, is received if the duty cycle is between 25 and 75%. Battery Saving Operation Battery consumption is reduced by controlled inter- mittent receive operation using BS1, BS2 and BS3. The functions of BS1, BS2 and BS3 are determined by the operating mode. BS1 Main RF control output signal. RF turns ON when BS1 goes HIGH. RF discharge output control signal. BS2 goes HIGH with BS1 and then goes LOW again 15.8 ms later (15.0 ms at 1200 bps). In lock mode, BS2 remains LOW. PLL start control output signal, when a PLL is used. BS3 goes HIGH before BS1 and then goes LOW with BS1. The BS3 to BS1 BS2 BS3 Operating Modes Switch ON mode After power ON, the internal registers are reset by taking RST LOW. The registers can then be initial- ized by writing six addresses comprising 18 bits and 7-bit flag data synchronized with TXCLK and TXDATA. The data on TXDATA is transmitted over 32 x 7 + 1 TXCLK cycles. The operating mode changes to preamble mode after 225 TXCLK cycles, setting BS1, BS2 and BS3. Flag Function PL, PL2 PLL lock-up time select INV Input signal invert select LBO 512 or 1200 bps select lead time is set by a CPU operation using Ft, Fe, FB [Frame select flags PL1 and PL2. mr | ins sama > ae TXCLK PL Al AL f] i] f| bee eee TepaTa Toe X XFS Br 18.6 ms (18.0 ms) +4 fb Bee BS3 , re TT | 2 me. Figure 6. Switch ON mode timing Preamble mode Preamble operating mode continues for a length of 544 bits and then changes to idle mode if none of the following are detected. * A preamble pattern. If detected, preamble mode continues for a further 544 bits. * A rate error. A rate error occurs if two SIGIN edges occur within a single bit period. If two such errors occur consecutively, the operating mode changes to idle mode immediately. e A synchronization code. A synchronization code is detected if two bit errors or less occur. If detected, the operating mode changes to lock mode, setting SYNVAL to HIGH. During preamble mode, BS1 and BS3 remain HIGH. NIPPON PRECISION CIRCUITS10CMOS LSI SM8210S Idle mode When BS1-BS2 is HIGH during idle mode, the SM8210S checks for the presence of a preamble signal. If detected, the operating mode changes to preamble mode. If not detected, intermittent opera- tion continues. A preamble signal is detected when the 6-bit pat- tern 101010 occurs. This detection method ensures that incorrect mode switching does not occur due to BS1 weak electric fields or noise. This pattern can also be included in other transmitted signals to facilitate easier mode switching. When the operating mode changes from lock mode to idle mode, the SM8210S checks for a synchronization code without setting BS2. If a synchronization code is detected, the operating mode returns to lock mode. pL br ms (41.7 i 1062.5 ms (453.3 ms) _ BS2 _ 15.6 ms (15.0 ms) [| __.| 51,67 or 82 ms Figure 7. Idle mode timing Error bit Preamble signal Preamble detection Preamble detection begins begins again 707010101708 2% *# + & [| Preambie setup Figure 8. Preamble code sequence Lock mode If a synchronization code is detected during pream- ble mode, the operating mode changes to lock mode and BSI goes LOW. When the frame specified by the flag data occurs, BS1 goes HIGH and the received data is compared with the 24 addresses. Note that if the frame number is zero, BS1 remains HIGH. A match occurs if there are two bit errors or less. The comparison is made twice since each frame comprises two code words. BS1 goes LOW if there is no match and the synchronization code detect. state is reset. If the synchronization code cannot be detected twice consecutively, the operating mode changes to idle mode and remains in lock mode during message reception. If the synchronization code is not detected a second time but instead the preamble pattern is detected, the operating mode changes to preamble mode. If one of the 24 addresses compared matches, ADDDET goes HIGH during the next code word, and the data in that address is sent to the CPU on RXDATA, which is synchronized to RXCLK. If the data following an address is confirmed to be a message, BS1 is held HIGH and the message is then received. After error correction, the received message is sent to the CPU on RXDATA, again synchronized with RXCLK, as a 23-bit word com- prising 20-bit data, 2-bit error correction code and 1-bit even parity check. If a message spans two or more batches, then a synchronization code detec- tion is carried out during reception. Message recep- tion terminates when another address or idle code is detected, or when an interrupt occurs on BREAK. When reception terminates, BS1 goes LOW and the 5M8210S waits for the synchronization code or an address for the next reference frame. NIPPON PRECISION CIRCUITS11CMOS LSI SM8210S Mode change summary : Preamble PN OE Figure 9. Operating mode switching Notes A The ID code, synchronized to TXCLK, is read after RST goes LOW. B A rate error is detected, or neither a preamble pattern nor synchronization code is detected within a fixed time. C Preamble pattern is detected. D_ Synchronization code is detected during the first cycle after changing from lock mode. E Synchronization code is not detected twice F Preamble pattern is detected instead of a second synchronization code. G = Synchronization code is detected. Address/Flag Data Transfer After initialization (RST goes LOW), | the address/fiag data is transferred from the CPU to the SM8210S on TXDATA on the falling edge of each of the 225 TXCLK pulses. The SM8210S supports six, independent, 18-bit addresses (A, B, C, D, E and F) for handling various group calls. Each address is expanded into four extension addresses by adding two function bits to each address. Also, one 0 bit (most sig- nificant bit) to indicate that it is an address, ten parity bits for BCH (31, 21) format and one even-parity bit are added. These addresses are then stored in RAM as twenty-four 32-bit addresses to be compared with the received data. Data is input into each address, most significant bit first. If less than the six addresses are used, data for the address used last should be copied into the remaining addresses. The data corresponding to each TXCLK pulse is shown in table 6, PLL lock-up time in table 7, and the baud rate and inverting selection in table 8. consecutively. Table 6. ID and fiag format TX clock Data TX clock Data TX clock Data TX clock Data TX clock Data 1 0 46 AAS 91 0 136 ADIO 181 0 2 0 47 AAS $2 0 137 x ADS 182 0 3 0 48 AA2 93 0 138 ADs 183 0 4 0 49 AAI 94 0 139 AD? 184 0 0 50 AAO 95 0 140 : AD6 185 0 6 0 51 0 96 0 141 ADS 186 0 7 0 52 0 97 ACI7 142 AD4 187 0 8 0 53 0 98 ACIE 143 AD3 188 0 9 ) 54 0 99 ACI5 144 AD2 189 0 10 0 55 0 100 AC14 145 ADI 190 0 of 0 56 0 101 ACI3 146 ADO 194 0 12 0 7 0 102 ACI2 147 0 192 0 13 0 58 0 103 ACit 148 0 193 AFi7 14 0 9 0 104 ACi0 149 0 194 AFI6 NIPPON PRECISION CIRCUITS12CMOS LSI SM8210S Table 6. ID and flag formatcontinued TX clock Data TX clock Data TX clock Data TX clock Data TX clock Data 16 0 60 0 105 ACS 150 0 195 AFI5 16 0 61 0 106 AC8 154 0 196 AFI4 7 0 62 0 107 ACT 182 0 197 AFI3 18 0 63 0 108 AC6 153 0 198 AFi2 19 0 64 0 109 AC5 154 0 199 AFI 20 0 65 ABI7 110 AC4 165 0 200 AF10 ai 1 66 ABi6 Wi AC3 156 0 201 AF9 22 0 67 AB15 12 AC2 157 0 202 AF8 23 0 68 ABI4 413 ACI 158 0 203 AF7 24 0 69 AB13 114 ACO 189 0 204 AF6 25 PL1 70 ABI2 115 0 160 0: 205 AF5 26 PL2 71 ABI 116 0 161 - AEI7 206 AF4 27 INV 72 ABI10 117 0 162 AE16 207 AFS 28 LBO 73 AB9 118 0 163 AE15 208 AF2 29 Fi 74 ABS 119 0 164 AE14 209 AF1 30 F2 78 AB7 4120 0 165 AE13 210 AFO 31 F3 76 AB6 421 0 166 AE12 2ii 0 32 0 71 ABS 122 0 167 AE 212 0 . 88 AAI? 78 AB4 123 0 168 AE10 213 0 34 AAI6 79 ABS 124 0 169 AES 214 0 35 AAI5 80 AB2 125 0 170 AE8 215 0 36 AAI4 84 ABI 126 0 171 AE7 216 Q 37 AAI3 82 ABO 127 0 172 AE6 217 0 38 AAI2 83 0 128 0 173 AE5 218 0 39 AAtI 84 0 129 AD17 174 AE4 219 0 40 AAIO 85 0 130 ADIG 175 AES 220 0 41 AAS 86 0 131 ADI5 176 AE2 221 0 42 AA8 87 9 132 ADi4 _ VT AE1 222 0 43 AAT 88 0 133 ADI3 178 AEO 223 0 44 AAG 89 0 134 AD12 179 0 224 0 45 AAS 90 0 135 ADi1 180 0 225 0 Table 7. PLL lock-up time selection PLn flag Lock-up time 51 67 82 NIPPON PRECISION CIRCUITS13CMOS LS! SM8210S Table 8. Baud rate and signal inversion selection LBO INV Baud rate input 0 0 1200 bps Non-inverting input 0 j 1200 bps {averting input j 0 12 bps Non-inverting input 1 1 512 bps inverting input Received Data Transfer In lock mode, if the received data in the frame specified by the frame flags contains two or less bit length and the 5-bit data in that address will be sent on TXDATA to the CPU, synchronized with errors and matches one of the 24 addresses, then RXCLK. ADDDET will go HIGH during the next code word Address detect code word 1 code word internal | | | clock 26 27 2828303110 123 4 6 6 7 & 9 101112191415 1617 18 19 20 21 22 23 24 25 26 27 28 28 30 31 1 RXCLK PUL RXDATA faojasfaz|as|aa] ADD-DET Figure 10. Received address data timing Table 9. Address flags AO At A2 A3 A4 Address Function bit | AO Ai A2 A3 A4 Address Function bit 0 0 1 0 0 A call 0 0 0 0 1 A call 1 0 1 0 0 B call 1 0 0 0 1 B call A D 0 1 1 0 0 C call 0 1 0 0 1 C cail 1 i 1 0 0 D call 1 1 0 0 1 D call 0 0 0 1 0 A call 0 0 1 0 1 A call 1 0 0 j 0 B call { 0 1 0 1 B call B E 0 1 0 1 0 C call 0 1 1 0 1 C call 1 1 0 1 0 D call 1 1 1 0 1 D call 0 0 1 | 0 A call 0 0 0 j 1 A call 1 0 1 1 0 B call 1 0 0 1 1 B call C F 0 1 1 1 0 C call 0 1 0 1 1 C call 1 1 1 1 0 D call 1 1 0 1 1 D call NIPPON PRECISION CIRCUITS14CMOS LS! SM8210S When an address is detected, the 32-bit data for the next code word is received. An error check is made using BCH (31, 21) format, and single-bit and two consecutive bit errors are corrected. Random 2-bit errors and 3-bit or more errors are not corrected. After correction, if the most significant bit is a 1, Message received code word the data is a message and is sent to the CPU together with an error check flag. If the most Significant bit is a 0, the data is an address or idle code, and data reception and data transfer to the CPU are stopped. 1 code word Intemal clock 26 27 28 293031}0 123 4 5 6 7 B 9 1011121914 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 o a pac UU RXDATA LEP ETT EEE EE ET TTT TT lected 20-bit message after error correction Figure 11. Received message transfer timing Table 10. Error flags Table 11. Parity flag Error flags Flag Error count Parity check Eo Et PE None 0 0 No error 0 One error 1 0 Error before BCH correction 1 Two consecutive bits 0 1 Two or more random bils, or three or 1 1 more consecutive bits NIPPON PRECISION CIRCUITS15CMOS LS! SM8210S peddojs yndino Bysp 0) papelsp yeeiq wd) Age | j 4.300q XBW SU 2 / oul) year peidwewunel M07 . Li] . en / | AWANAS _ i [or mai orT sa San] cov wor]@an San] San 3" cov Aba FeRAM Feat [Paaleaa SNA SANT AN SAR a8 BEY mal] wor] wor] os [san san} i | 7 | waaaay MO1 wae THOT sq o0zs 18 SW O'S} sdq 2}g Ww Blu g's, 0081) 18 ew O"g} a: zigieswggh "| [ | ye | tsa 4N990 JOU BGOP SsalPpe USL, C aw [aay mot mot wot] san] sai] san/ san] aay moTsan{sanl aay] worl wor} { $ y g z kL 0 2 Te wy | N fend San] san| cove 3. Z 9 Mo | moi [sa /s3n| san isan} N E 2 \ 0 4 L 8 NIPPON PRECISION CIRCUITS16 Figure 12. Interface timingCMOS LSI SM8210S CPU Interfaces Synchronization word detection When a synchronization code is detected, if there are two or less exror bits, SYNVAL goes HIGH during the next 544-bit cycle. Address detection In lock mode, if the data received in the frame matches an address with two or less bit errors, then ADDDET remains HIGH during the next code word. If . consecutive matching addresses are detected, ADDDET is HIGH for two code words. rt Receive data interrupt The CPU halts data transmission from the SM8210S when BREAK goes HIGH. The SM8210S then stops receiving data and changes to the synchronization code detect state. Extended Reset If RST is held LOW for more than 1 or 2 ms, then BS1 and BS3 go HIGH and stay HIGH until 1 or 2 ms after RST goes HIGH again. This period is used to check the RF circuit operation. After RST goes HIGH, the ID code input state is active. See figure 6. | _ t 1to2ms | Figure 13. Power Saving Control When BACKUP goes LOW, internal operation halts and all outputs become high impedance. To recover, it is necessary to sct the ID code and initialize the device. Reset timing Transmitting data If BACKUP goes LOW while transmitting data on TXDATA, TXCLK should not be halted until the ID code has been read. Similarly, the XT clock should not be halted until at least one bit period (150 cycles at 512 bps or 64 cycles at 1200 bps) after reading the ID code. TXCLK BACKUP Backup enable (internal) One bit time _4 bpm Figure 14. BACKUP during data transmission Under other conditions If BACKUP goes LOW under any conditions, excluding during data transmission, the XT clock should continue for a minimum period of 65 bits. NIPPON PRECISION CIRCUITS17CMOS LSi SM8210S TYPICAL APPLICATION FF section Decoder Alert PTT me ee prt creer eS pose etna ete een ' 1 ! i 5 I | \ | ! ! ! { | 1 | ! ! I ! 1 | I | 1 | ' | \ ! ' | 1 | t j ' ! | } \ ; 1 SM8210S || ! \ | decoder IC j ' | | I \ ' I ! I j Wavetorm |! I 14 1 RF 7] adjust Amplifier }1 Speaker ! \ I I I \ I i I I I ! I i \ \ Poo e-------- WS toe ef eed CPU 'D ROM poo------t--~----+-- joo oon sf DC/DC . converter LCD driver LCD Power supply Display NiPPON PRECISION CIRCUITS LTD. reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products, Nippon Precision Circuits Lid. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Ltd. makes no claim or warranty that such applications will be suilable for the use specified without further testing or modification, NIPPON PRECISION CIRCUITS LTD. Shuwa Sakurabashi Building -4, Hachobori 4-chome Chuo-ku, Tokyo 104 Japan NIPPON PRECISION CIRCUITS LTD. Telephone: 03-3555-7521 Facsimile: 03-3555-7528 NC9210A 1992.06 NIPPON PRECISION CIRCUITS18