HEF4053B Triple single-pole double-throw analog switch Rev. 12 -- 25 March 2016 Product data sheet 1. General description The HEF4053B is a triple single-pole double-throw (SPDT) analog switch, suitable for use as an analog or digital multiplexer/demultiplexer. Each switch has a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). All three switches share an enable input (E). A HIGH on E causes all switches into the high-impedance OFF-state, independent of Sn. VDD and VSS are the supply voltage connections for the digital control inputs (Sn and E). The VDD to VSS range is 3 V to 15 V. The analog inputs/outputs (nY0, nY1 and nZ) can swing between VDD as a positive limit and VEE as a negative limit. VDD VEE may not exceed 15 V. Unused inputs must be connected to VDD, VSS, or another input. For operation as a digital multiplexer/demultiplexer, VEE is connected to VSS (typically ground). VEE and VSS are the supply voltage connections for the switches. 2. Features and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +125 C Complies with JEDEC standard JESD 13-B 3. Applications Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating 4. Ordering information Table 1. Ordering information All types operate from 40 C to +125 C. Type number Package Name Description Version HEF4053BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4053BTT TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 HEF4053B Nexperia Triple single-pole double-throw analog switch 5. Functional diagram ( 9'' < 6 /2*,& /(9(/ &219(56,21 < '(&2'(5 = < 6 6 < 6 < 6 = < < = < < = /2*,& /(9(/ &219(56,21 < = < 6 /2*,& /(9(/ &219(56,21 < = ( 966 DDH Fig 1. Logic symbol Fig 2. 9(( DDH Functional diagram Q= Q< 6Q /(9(/ &219(57(5 Q< ( /(9(/ &219(57(5 WRRWKHUPXOWLSOH[HUVGHPXOWLSOH[HUV DDH Fig 3. Logic diagram (one multiplexer/demultiplexer) HEF4053B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 12 -- 25 March 2016 (c) Nexperia B.V. 2017. All rights reserved 2 of 19 HEF4053B Nexperia Triple single-pole double-throw analog switch Q VDD + 0.5 V VI input voltage II/O input/output current - 10 mA IDD supply current - 50 mA Tstg storage temperature 65 +150 C Tamb ambient temperature 40 +125 C Ptot total power dissipation P [1] [2] power dissipation V Tamb = 40 C to +125 C SO16 package [2] - 500 mW TSSOP16 package [2] - 500 mW - 100 mW per output To avoid drawing VDD current out of terminal Z, when switch current flows into terminals Y, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VDD current will flow out of terminals Y, and in this case there is no limit for the voltage drop across the switch, but the voltages at Y and Z may not exceed VDD or VEE. For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VDD supply voltage see Figure 7 3 - 15 V VI input voltage 0 - VDD V Tamb ambient temperature in free air 40 - +125 C t/V input transition rise and fall rate VDD = 5 V - - 3.75 s/V VDD = 10 V - - 0.5 s/V VDD = 15 V - - 0.08 s/V HEF4053B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 12 -- 25 March 2016 (c) Nexperia B.V. 2017. All rights reserved 4 of 19 HEF4053B Nexperia Triple single-pole double-throw analog switch DDH 9'' 966 9 RSHUDWLQJDUHD 9'' 9(( 9 Fig 7. Operating area as a function of the supply voltages 10. Static characteristics Table 6. Static characteristics VSS = VEE = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VIH VIL Conditions Max Min Max Min Max Min Max 5V 3.5 - 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 - 4.0 V 15 V - 0.1 - 0.1 - 1.0 - 1.0 A Z port; 15 V all channels OFF; see Figure 8 - - - 1000 - - - - nA 15 V - - - 200 - - - - nA IO < 1 A LOW-level input voltage IO < 1 A input leakage current IS(OFF) OFF-state leakage current Y port; per channel; see Figure 9 IDD CI supply current IO = 0 A input capacitance HEF4053B Product data sheet Tamb = 85 C Tamb = 125 C Unit Min HIGH-level input voltage II Tamb = 40 C Tamb = 25 C VDD Sn, E inputs 5V - 5 - 5 - 150 - 150 A 10 V - 10 - 10 - 300 - 300 A 15 V - 20 - 20 - 600 - 600 A - - - - 7.5 - - - - pF All information provided in this document is subject to legal disclaimers. Rev. 12 -- 25 March 2016 (c) Nexperia B.V. 2017. All rights reserved 5 of 19 HEF4053B Nexperia Triple single-pole double-throw analog switch 10.1 Test circuits 9'' 9''RU966 ,6 6WR6 Q< Q= Q< VZLWFK ( 966 9(( 9'' 92 9, DDM Fig 8. Test circuit for measuring OFF-state leakage current Z port 9'' 9''RU966 6WR6 Q< Q= Q< VZLWFK ,6 ( 966 9(( 966 9, 92 DDM Fig 9. Test circuit for measuring OFF-state leakage current nYn port 10.2 ON resistance Table 7. ON resistance Tamb = 25 C; ISW = 200 A; VSS = VEE = 0 V. Symbol Parameter Conditions VDD VEE Typ Max Unit RON(peak) ON resistance (peak) VI = 0 V to VDD VEE; see Figure 10 and Figure 11 5V 350 2500 10 V 80 245 15 V 60 175 5V 115 340 10 V 50 160 15 V 40 115 5V 120 365 10 V 65 200 15 V 50 155 5V 25 - 10 V 10 - 15 V 5 - RON(rail) ON resistance (rail) VI = 0 V; see Figure 10 and Figure 11 VI = VDD VEE; see Figure 10 and Figure 11 RON ON resistance mismatch between channels HEF4053B Product data sheet VI = 0 V to VDD VEE; see Figure 10 All information provided in this document is subject to legal disclaimers. Rev. 12 -- 25 March 2016 (c) Nexperia B.V. 2017. All rights reserved 6 of 19 HEF4053B Nexperia Triple single-pole double-throw analog switch 10.2.1 ON resistance waveform and test circuit 9 96: 9'' 9''RU966 6WR6 Q< Q= Q< VZLWFK ( 966 9(( 966 ,6: 9, DDM RON = VSW / ISW. Fig 10. Test circuit for measuring RON DDH 521 9'' 9 9 9 9, 9 Fig 11. Typical RON as a function of input voltage HEF4053B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 12 -- 25 March 2016 (c) Nexperia B.V. 2017. All rights reserved 7 of 19 HEF4053B Nexperia Triple single-pole double-throw analog switch 11. Dynamic characteristics Table 8. Dynamic characteristics Tamb = 25 C; VSS = VEE = 0 V; for test circuit see Figure 15. Symbol Parameter Conditions tPHL HIGH to LOW propagation delay nYn, nZ to nZ, nYn; see Figure 12 Sn to nYn, nZ; see Figure 13 LOW to HIGH propagation delay nYn, nZ to nZ, nYn; see Figure 12 tPLH Sn to nYn, nZ; see Figure 13 HIGH to OFF-state propagation delay tPHZ tPZH tPLZ OFF-state to HIGH propagation delay E to nYn, nZ; see Figure 14 LOW to OFF-state propagation delay E to nYn, nZ; see Figure 14 OFF-state to LOW propagation delay tPZL E to nYn, nZ; see Figure 14 E to nYn, nZ; see Figure 14 VDD Typ Max Unit 5V 10 20 ns 10 V 5 10 ns 15 V 5 10 ns 5V 200 400 ns 10 V 85 170 ns 15 V 65 130 ns 5V 15 30 ns 10 V 5 10 ns 15 V 5 10 ns 5V 275 555 ns 10 V 100 200 ns 15 V 65 130 ns 5V 200 400 ns 10 V 115 230 ns 15 V 110 220 ns 5V 260 525 ns 10 V 95 190 ns 15 V 65 130 ns 5V 200 400 ns 10 V 120 245 ns 15 V 110 215 ns 5V 280 565 ns 10 V 105 205 ns 15 V 70 140 ns 11.1 Waveforms and test circuit 9'' Q