2003 Microchip Technology Inc. DS80164A-page 1
PIC16C63A/65B/73B/74B
The PIC16C63A/65B/73B/74B parts you have received
conform functionally to the Device Data Sheet
(DS30605C), except for the anomalies described
below.
None.
PIC16C63A/65B/73B/74B Data Sheet Errata
PIC16C63A/65B/73B/74B
DS80164A-page 2 2003 Microchip Technology Inc.
Clarifications/Corrections to the Data
Sheet:
In the Device Data Sheet (DS30605C), the following
clarificati ons and corrections should be noted.
1. Module: SSP (SPITM Mode)
In Section 10.2 (“SPI Mode”), Figure 10-1 and the
note box immediately beneath it have been
amende d to bett er demo nstrate the Peri pheral OE
line of the SSP module and describe its relation-
ship to the TRISC<5> bit of PORTC.
Chang es are ind ic ate d in bold.
FIGURE 10-1: SSP BLOCK DIAGRAM
(SPI MODE)
Read Write
Internal
Data B us
SSPSR reg
SSPM3:SSPM0
bit0 Shift
Clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 Output
TCY
Prescaler
4, 16, 64
2
Edge
Select
2
4
TRISC<3>
2
SMP:CKE
RC4/SDI/SDA
RC5/SDO
RA5/SS/AN4
RC3/SCK/SCL
SSPBUF reg
Peripheral OE
Note 1: When the SPI module is in Slave mode
with SS pin control enabled
(SSPCON<3:0> = 0100), the SPI mo dule
will reset if the SS pin is set to VDD.
2: If the SPI is used in Slave mode with
CKE = '1', then SS pin control must be
enabled.
3: When the SPI i s in Sla ve mod e with SS
pin control enabled (SSPCON<3:0> =
0100), the st ate of the SS pin can affect
the state read back from the TRISC<5>
bit. The Peripheral OE signal from the
SSP module into PORTC, controls the
state that is read back from the
TRISC<5> bit (see Section 5.3 for infor-
mation on PORTC). If Read-Modify-
Write instructions, such as BSF, are
performed on the T R ISC regi ster whi le
the SS pin is high, this will cause the
TRISC<5> bit to be set, thus disabling
the SDO output.
2003 Microchip Technology Inc. DS80164A-page 3
PIC16C63A/65B/73B/74B
2. Module: Packaging (Pinout and Product
Identification)
PIC16C63A and PIC16C73B devices are now
offered in 28-pin near chip-scale micro lead frame
packages (commonly known as “QFN”). This
pac kaging t ype has been ad ded to the produc t line
since the latest revision of the Device Data Sheet.
The addition of this option requires the following
additions to the Device Data Sheet. The
referenced figures and tables follow this text.
1. The “ Pin Diagram” on page 2 of the Dat a Sheet
is amended with the addition of the 28-pin QFN
pinout, shown in Figure 1.
2. Table 3-1 of Section 3.0 (“Architectural
Overview”) is replaced with an updated version
that adds a column for QFN pin assignments.
All new information is indicated in bold.
3. Section 18.1 (“Package Marking Information”)
is amend ed to inc lu de a marking template and
example for 28-pin QFN devices. These are
shown in Figure 2.
4. Section 18.0 (“Package Information”) is
amended to include the mechanical drawings
of the 28-pin QFN package. These are shown
in Figure 3 and Figure 4, respectively.
5. Table B-1 (“De vice Differe nces”) is ame nded to
include the 28-pin QFN for the PIC16C63 A and
PIC16C73B devices.
FIGURE 1: PINOUT DIAGRAM FOR PIC16C63A AND PIC16C73B, 28-PIN QFN
FIGURE 2: PACKAGE MARKING TEMPLATE FOR PIC16C63A AND PIC16C73B, 28-PIN QFN
2
3
4
5
6
1
7
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS
15
16
17
18
19
20
21
RB0/INT
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
VSS
OSC2/CLKO
OSC1/CLKI
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
23
24
25
26
27
28 22
RB7
RB6
RB5
RB4
RB3
RB2
RB1
10 11
891213 14
QFN (28-pin)
PIC16C63A
PIC16C73B
28-Lead QFN Example
XXXXXXXX
XXXXXXXX
YYWWNNN
PIC16C63A
-I/ML
0310017
PIC16C63A/65B/73B/74B
DS80164A-page 4 2003 Microchip Technology Inc.
TABLE 3-1: PIC16C63A/73B PINOUT DESCRIPTION
Pin Name DIP
Pin# SOIC
Pin# QFN
Pin# I/O/P
Type Buffer
Type Description
OSC1/CLKIN 9 9 6IST/CMOS
(3) Oscillator crystal input/external clock source input.
OSC2/CLKOUT 10 10 7O — Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
MCLR/VPP 1126 I/P ST Master clear (RESET) input or programming voltage input.
This pin is an active low RESET to the device.
PORTA is a bidirectional I/O port.
RA0/AN0(4) 2227 I/O TTL RA0 can also be analog input 0(4).
RA1/AN1(4) 3328 I/O TTL RA1 can also be analog input 1(4).
RA2/AN2(4) 441I/O TTL RA2 can also be analog input 2(4).
RA3/AN3/VREF(4) 552I/O TTL RA3 can also be analog input 3 or analog reference
voltage(4).
RA4/T0CKI 6 6 3I/O ST RA4 can also be the clock input to the Timer0 module.
Output is open drain type.
RA5/SS/AN4(4) 774I/O TTL RA5 can also be analog input 4(4) or the slave select for
the synchronous serial port.
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT 21 21 18 I/O TTL/ST(1) RB0 can also be the external interrupt pin.
RB1 22 22 19 I/O TTL
RB2 23 23 20 I/O TTL
RB3 24 24 21 I/O TTL
RB4 25 25 22 I/O TTL Interrupt-on-change pin.
RB5 26 26 23 I/O TTL Interrupt-on-change pin.
RB6 27 27 24 I/O TTL/ST(2) Interrupt-on-change pin. Serial programming clock.
RB7 28 28 25 I/O TTL/ST(2) Interrup t-on- change pin. Serial programming data.
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI 11 11 8I/O ST RC0 can also be the Timer1 oscillator output or Timer1
clock input.
RC1/T1OSI/CCP2 12 12 9I/O ST RC1 can also be the Timer1 oscillator input or Capture2
input/Compare2 output/PWM2 output.
RC2/CCP1 13 13 10 I/O ST RC2 can also be the Capture1 input/Compare1
output/PWM1 output.
RC3/SCK/SCL 14 14 11 I/O ST RC3 can also be the synchronous serial clock input/output
for both SPI and I2C modes.
RC4/SDI/SDA 15 15 12 I/O ST RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO 16 16 13 I/O ST RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK 17 17 14 I/O ST RC6 can also be the USART Asynchronous Transmit
or Synchronous Clock.
RC7/RX/DT 18 18 15 I/O ST RC7 can also be the USART Asynchronous Receive
or Synchronous Data.
VSS 8, 19 8, 19 16 P — Ground reference for logic and I/O pins.
VDD 20 20 17 P — Positive supply for logic and I/O pins.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
4: A/D module is not available in the PIC16C63A.
2003 Microchip Technology Inc. DS80164A-page 5
PIC16C63A/65B/73B/74B
FIGURE 3: 28-PIN QFN PACKAGE (DRAWING 1, PACKAGING)
Lead Width
*Controlling Parameter
Drawing No. C04-114
Notes:
Mold Draft Angle Top
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
B
α
.009
12°
.011 .014 0.23
12°
0.28 0.35
Pitch
Number of Pins
Overall Width
Standoff
Molded Package Length
Overall Length
Molded Package Width
Molded Package Thickness
Overall Height
MAX
Units
Dimension Limits
A2
A1
E1
D
D1
E
n
p
A
.026
.236 BSC
.000
.226 BSC
INCHES
.026 BSC
MIN
28
NOM MAX
0.65
.031
.002 0.00
6.00 BSC
5.75 BSC
MILLIMETERS*
.039
MIN
28
0.65 BSC
NOM
0.80
0.05
1.00
.008 REFBase Thickness A3 0.20 REF
JEDEC equivalent: mMO-220
0.85.033
.0004 0.01
.236 BSC
.226 BSC
6.00 BSC
5.75 BSC
Lead Length
Tie Bar Width
L .020 .024 .030 0.50 0.60 0.75
R .005 .007 .010 0.13 0.17 0.23
Tie Bar Length Q.012 .016 .026 0.30 0.40 0.65
Chamfer CH .009 .017 .024 0.24 0.42 0.60
E2
D2
Exposed Pad Width
Exposed Pad Length .140 .146 .152 3.55 3.70 3.85
.140 .146 .152 3.55 3.70 3.85
D
E
E1
n
1
2
D1
A
A2
EXPOSED
METAL
PADS
BOTTOM VIEW
TOP VIEW
Q
L
R
p
A1
A3
α
CH X 45°
B
D2
E2
28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body, Punch Singulated (QFN)
PIC16C63A/65B/73B/74B
DS80164A-page 6 2003 Microchip Technology Inc.
FIGURE 4: 28-PIN QFN PACKAGE (DRAWING 2, PACKAGING)
B
D2
D
PAD OUTLINE
ALTERNATE
SEE DETAIL
A1
A
DETAIL
TOP VIEW
OPTIONAL
INDEX
AREA
1
2
L
BOTTOM VIEW
n
E
METAL
PAD
ALTERNATE
EXPOSED
INDICATORS
INDEX
p
E2
Lead Width
*Controlling Parameter
Drawing No. C04-105
Notes:
JEDEC equivalent: mMO-220
B .009 .011 .013 0.23 0.28 0.33
Pitch
Number of Pins
Overall Width
Standoff
Overall Length
Overall Height
MAX
Units
Dimension Limits
A1
D
E
n
p
A
.000
INCHES
.026 BSC
MIN
28
NOM MAX
.002 0.00
6.00
MILLIMETERS*
.039
MIN
28
0.65 BSC
NOM
0.05
1.000.90.035
.001 0.02
Lead Length L .020 .022 .024 0.50 0.55 0.60
E2
D2
Exposed Pad Width
Exposed Pad Length
.140 .146 .152 3.55 3.70 3.85
.031 0.80
5.90 6.10.240.236.232
.232 .236 6.00.240 5.90 6.10
.140 .146 3.70.152 3.55 3.85
28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body, Saw Singulated (QFN)
2003 Microchip Technology Inc. DS80164A-page 7
PIC16C63A/65B/73B/74B
3. Module: RESET
Section 13.4 .1 (“POWER-ON RESET (POR)”) ha s
been amended to clarify the minimum specifica-
tions required for MCLR in order to RESET the
PIC16CXXX. The following paragraphs and figure
have been added:
If a MCLR pul se occur s that is less th at the mini-
mum specification (parameter #30), improper
device operation can occur.
If the minimum specification cannot be met, then
an exte rnal circ uit must be used t o ensure that any
pulse width less than the specification will be fil-
tered before it reaches the MCLR pin.
A possible circuit to remedy this is shown in
Figure 5. This circuit works by delaying the MCLR
release following a power-up. If no delay is
required, th e capac itor may be omitted.
An alternati ve would be to use a supervisory circuit
to control MCLR.
Design validation should be performed to verify
that the application works as expected.
FIGURE 5: MCLR EXTERNAL CIRCUIT
C1
R1
VDD
MCLR
PIC16CXXX
4.7 kΩ≤ R1 ≤ 100 kΩ
0.01 µF≤ C1 ≤ 0.1 µF
(optional)
PIC16C63A/65B/73B/74B
DS80164A-page 8 2003 Microchip Technology Inc.
REVISION HISTORY
Rev A Document (7/2003)
First revision of this document. Device Data Sheet
Clarification issues 1 (SSP), 2 (Packaging) and 3
(RESET).
2003 Microchip Technology Inc. DS80164A-page 9
Information contained in this publication regarding device
applications and the like is intended through sug gestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microc hip Technology Incorporated with respect
to the accuracy or use of such inf orm ation, or inf ringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, MPLAB, PIC, PICmicro, PICST ART, PRO MA TE and
PowerSmart are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, microID, MXDE V, MXLAB, PICMASTE R, SEEVAL
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Accuron, Application Maestro, dsPICDEM, dsPICDEM.net,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-
Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSI M,
PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, Powe rTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartT el and T otal Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the co de protection fe atures of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such ac t s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, Cal ifornia in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
DS80164A-page 28 2003 Microchip Technology Inc.
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