NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM 240pin Registered DDR2 SDRAM MODULE Based on 64Mx8 & 128Mx4 DDR2 SDRAM Die B Features * Differential clock inputs * Data is read or written on both clock edges * Programmable Operation: - Device Latency: 5, 6 - Burst Type: Sequential or Interleave - Burst Length: 4, 8 - Operation: Burst Read and Write * Auto Refresh (CBR) and Self Refresh Modes * On-Die Termination (ODT) * Off-Chip Driver (OCD) * 14/10/1 Addressing (row/column/rank) - 512MB * 14/11/1 Addressing (row/column/rank) - 1GB * 14/11/2 Addressing (row/column/rank) - 2GB * Serial Presence Detect * Gold contacts * SDRAMs in 60-ball FBGA Package * RoHS compliance * 64Mx72 Registered DDR2 DIMM based on 64Mx8 DDR2 SDRAM (NT5TU64M8BE) * 128Mx72 & 256Mx72 Registered DDR2 DIMM based on 128Mx4 DDR2 SDRAM (NT5TU128M4BE) * JEDEC Standard 240-pin Dual In-Line Memory Module * Error Check Correction (ECC) Support * Registered inputs with one-clock delay * Performance: PC2-5300 PC2-6400 PC2-6400 Speed Sort DIMM Latency* f CK Clock Frequency t CK Clock Cycle f DQ DQ Burst Frequency Unit -3C -25D -25C 5 6 5 333 400 400 3 2.5 2.5 ns 667 800 800 MHz MHz * Intended for 333 and 400 MHz applications * Inputs and outputs are SSTL-18 compatible * VDD = 1.8 0.1 Volt, VDDQ = 1.8 0.1 Volt * SDRAMs have 4 internal banks for concurrent operation Description NT512T72U89B0BV, NT1GT72U4PB0BV, NT2GT72U4NB0BV and NT2GT72U4NB1BV are Registered 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Dual In-Line Memory Module (DIMM), organized as a one-bank 64Mx72 or128Mx72 and two-banks 256Mx72 high-speed memory array. The module uses nine 64Mx8 (NT512T72U89B0BV), eighteen 128Mx4 (NT1GT72U4PB0BV) or thirty-six 128Mx4 (NT2GT72U4NB0BV, NT2GT72U4NB1BV) DDR2 SDRAMs in FBGA packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. The DIMM is intended for use in applications operating up to 333 MHz (400MHz) clock speeds and achieves high-speed data transfer rates of up to 667 MHz (800MHz). Prior to any access operation, the device latency and burst/length/operation type must be programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. REV 1.3 05/2007 1 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Ordering Information Part Number Speed Organization NT512T72U89B0BV-3C 333 MHz (3ns @ CL = 5) PC2-5300 DDR2-667 Gold 1.8V 128Mx72 NT2GT72U4NB0BV-3C 256Mx72 NT512T72U89B0BV-25D 64Mx72 400 MHz (2.5ns @ CL = 6) NT2GT72U4NB1BV-25D 128Mx72 DDR2800 NT512T72U89B0BV-25C NT1GT72U4PB0BV-25C Power 64Mx72 NT1GT72U4PB0BV-3C NT1GT72U4PB0BV-25D Leads PC2-6400 400 MHz (2.5ns @ CL = 5) 256Mx72 64Mx72 128Mx72 NT2GT72U4NB1BV-25C 256Mx72 Pin Description CK0, CKE0, CKE1 Differential Clock Inputs DQ0-DQ63 Clock Enable CB0-CB7 Row Address Strobe DQS0-DQS8 Column Address Strobe , A0-A9, A11-A13 A10/AP BA0, BA1 ODT0, ODT1 NC RFU Par_In REV 1.3 05/2007 Data input/output ECC Check Bit Data Input/Output Bidirectional data strobes DM0-DM8/DQS9-17 Input Data Mask/High Data Strobes Write Enable - Chip Selects VDD Address Inputs VDDQ Column Address Input/Auto-precharge VREF SDRAM Bank Address Inputs VDDSPD Differential data strobes Core Power I/O Power Ref. Voltage for SSTL_18 inputs Serial EEPROM positive power supply Reset pin VSS Ground Active termination control lines SCL Serial Presence Detect Clock Input SDA Serial Presence Detect Data input/output No Connect Reserved for Future Use SA0-2 Serial Presence Detect Address Inputs Parity error found on the Address and Control bus Parity bit for the Address and Control bus 2 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Pinout Pin Front 1 VREF 2 VSS 3 DQ0 44 4 DQ1 45 5 VSS 6 Pin Front Pin Front Pin Back Pin Back Pin Back 42 CB0 82 VSS 43 CB1 83 121 VSS 162 CB5 202 DM4/DQS13 122 DQ4 163 VSS 203 VSS 84 DQS4 123 DQ5 164 DM8/DQS17 204 VSS 46 DQS8 85 VSS 124 VSS 165 205 DQ38 86 DQ34 125 DM0, DQS9 166 VSS 206 47 VSS DQ39 87 DQ35 126 167 CB6 207 VSS NC, 7 DQS0 48 CB2 88 VSS 127 VSS 168 CB7 208 DQ44 8 VSS 49 CB3 89 DQ40 128 DQ6 169 VSS 209 DQ45 9 DQ2 50 VSS 90 DQ41 129 DQ7 170 VDDQ 210 VSS 10 DQ3 51 VDDQ 91 VSS 130 VSS 171 NC, CKE1 211 DM5/DQS14 11 VSS 52 CKE0 92 131 DQ12 172 VDD 212 12 DQ8 53 VDD 93 DQS5 132 DQ13 173 NC 213 VSS 13 DQ9 54 NC 94 VSS 133 VSS 174 NC 214 DQ46 14 VSS 55 95 DQ42 134 DM1/DQS10 175 VDDQ 215 DQ47 176 A12 216 VSS 15 56 VDDQ 96 DQ43 135 16 DQS1 57 A11 97 VSS 136 VSS 177 A9 217 DQ52 17 VSS 58 A7 98 DQ48 137 RFU 178 VDD 218 DQ53 18 59 VDD 99 DQ49 138 RFU 179 A8 219 VSS 19 NC 60 A5 100 VSS 139 VSS 180 A6 220 NC 20 VSS 61 A4 101 SA2 140 DQ14 181 VDDQ 221 NC 21 DQ10 62 VDDQ 102 NC 141 DQ15 182 A3 222 VSS 22 DQ11 63 A2 103 VSS DM6/DQS15 23 VSS 64 VDD 104 24 DQ16 105 25 DQ17 65 VSS 106 26 VSS 66 VSS 27 KEY 142 VSS 183 A1 223 143 DQ20 184 VDD 224 DQS6 144 DQ21 VSS 145 VSS 185 107 DQ50 146 DM2/DQS11 186 KEY CK0 225 VSS 226 DQ54 227 DQ55 67 VDD 108 DQ51 147 187 VDD 228 VSS DQS2 68 Par_In 109 VSS 148 VSS 188 A0 229 DQ60 29 VSS 69 VDD 110 DQ56 149 DQ22 189 VDD 230 DQ61 30 DQ18 70 A10/AP 111 DQ57 150 DQ23 190 BA1 231 VSS 31 DQ19 71 BA0 112 VSS VDDQ 232 DM7/DQS16 32 VSS 72 VDDQ 113 33 DQ24 73 114 34 DQ25 74 115 35 Vss 75 28 36 VDDQ 76 151 VSS 191 152 DQ28 192 DQS7 153 DQ29 193 234 VSS VSS 154 VSS 194 VDDQ 235 DQ62 116 DQ58 155 DM3/DQS12 195 ODT0 236 DQ63 233 117 DQ59 156 196 A13 237 VSS DQS3 77 ODT1 118 VSS 157 VSS 197 VDD 238 VDDSPD 38 Vss 78 VDDQ 119 SDA 158 DQ30 198 VSS 239 SA0 39 DQ26 79 Vss 120 SCL 159 DQ31 199 DQ36 240 SA1 40 DQ27 80 DQ32 160 VSS 200 DQ37 41 Vss 81 DQ33 161 CB4 201 VSS 37 and Par_In are optional functions to check address and command parity. REV 1.3 05/2007 3 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Input/Output Functional Description Symbol Type Polarity Function CK0 (SSTL) The positive line of the differential pair of system clock inputs which drives the input to Positive the on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the Edge rising edge of their associated clocks. (SSTL) Negative The negative line of the differential pair of system clock inputs which drives the input to Edge the on-DIMM PLL. CKE0, CKE1 (SSTL) Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. , (SSTL) Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. (SSTL) Active Low When sampled at the positive rising edge of the clock, operation to be executed by the SDRAM. , , , , define the VREF Supply Reference voltage for SSTL-18 inputs VDDQ Supply Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity ODT0, ODT1 Input Active High BA0, BA1 (SSTL) - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A13 defines the row address (RA0-RA13) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0-CA10) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. A0 - A9 A10/AP A11-A13 (SSTL) - DQ0 - DQ63 CB0 - CB7 (SSTL) Active High VDD, VSS Supply On-Die Termination control signals Data and Check Bit Input/Output pins. Check bits are only applicable on the x72 DIMM configurations. Power and ground for the DDR SDRAM input buffers and core logic Negative and Data strobe for input and output data Positive Edge DQS0 - DQS17 - (SSTL) DM0 - DM8 Input Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. Input Active Low The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs will be driven low and the PLL clocks to the DRAMs and the registers will be set to low level. The PLL will remain synchronized with the input clock. SA0 - SA2 - Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. SDA - This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pull-up. SCL - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pull-up. V DDSPD Supply Par_In Input Out REV 1.3 05/2007 Serial EEPROM positive power supply. Parity bit for the Address and Control bus. (1 for Odd, 0 for Even) Parity error found in the Address and Control bus. 4 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Functional Block Diagram (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs) REV 1.3 05/2007 5 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Functional Block Diagram (1GB, 1 Rank, 128Mx4 DDR2 SDRAMs) ! ! ! ! ! ! ! " " " " " " " " ! # " " ' " " " $ " & % % & & % # & # # # $ $ $ $ $ $ $ () $ *+ % ,, $$ ), +-- ), ./ 0)1. +) ( $. ( $. 23 23 " 23 % 4- $ % % % % 5 %!5 5 5 ( $. % $ % $ % ( $. REV 1.3 05/2007 6 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Functional Block Diagram (2GB DDR2-533/667, 2 Ranks, 128Mx4 DDR2 SDRAMs) REV 1.3 05/2007 7 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Functional Block Diagram (2GB DDR2-800, 2 Ranks, 128Mx4 DDR2 SDRAMs) Vss DQS0 DQS9 DQS DQ0 DQ1 DM I /O 0 I /O 1 I /O 2 DQ2 DQ3 DQS DM DQS I/ O 0 I/ O 1 I/ O 2 D0 I /O 3 DQ4 DQ5 D18 DQS1 DQS I /O 0 I /O 1 I /O 2 I /O 3 DM DQS I/ O 0 I/ O 1 D1 I/ O 2 I/ O 3 DM DQS DQ12 DQ13 DQ14 DQ15 D19 DQS2 DM D27 I /O 0 I /O 1 DM DQS I/O 0 I/O 1 D10 I /O 2 I /O 3 I/O 2 I/O 3 DM D28 DQS11 DQS DQ16 I /O 0 I /O 1 I /O 2 I /O 3 DQ17 DQ18 DQ19 DM DQS I/ O 0 I/ O 1 I/ O 2 I/ O 3 D2 DM DQS DQ20 I /O 0 I /O 1 I /O 2 I /O 3 DQ21 DQ22 DQ23 D20 DQS3 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 D11 DM D29 DQS12 DQS DQ24 DQ25 DQ26 DQ27 DM DQS DQS DM DM DQS I /O 0 I/ O 0 DQ28 I /O 0 I/O 0 I /O 1 I /O 2 I /O 3 I/ O 1 I/ O 2 I/ O 3 DQ29 DQ30 DQ31 I /O 1 I /O 2 I /O 3 I/O 1 I/O 2 I/O 3 D3 D21 DQS8 D12 DM D30 DQS17 DQS CB0 CB1 CB2 DM I /O 0 I /O 1 I /O 2 I /O 3 CB3 D8 DQS DQS DM I/ O 0 CB4 I /O 0 I/ O 1 I/ O 2 I/ O 3 CB5 CB6 CB7 I /O 1 I /O 2 I /O 3 D26 DQS4 DM DQS DM I/O 0 I/O 1 I/O 2 I/O 3 D17 D35 V DDSPD VDDQ DQS I/O I/O I/O I/O 0 1 2 3 DM DQS I/O I/O I/O I/O D4 0 1 2 3 DM DQS DQ36 DQ37 DQ38 D22 I/O I/O I/O I/O DQ39 DQS5 0 1 2 3 DM DQS I/O I/O I/O I/O D13 0 1 2 3 DQS I/O 0 I/O 1 DQ41 DQ42 DQ43 I/O 2 I/O 3 DM DQS I/O 0 I/O 1 D5 I/O 2 I/O 3 DM Serial PD SCL DM DQS D23 DQS6 D0 -D35 D0 -D35 D0 -D35 D31 DQS14 DQ40 Serial PD D0 -D35 V DD VREF VSS DQS13 DQ32 DQ33 DQ34 DQ35 DQ44 DQ45 I/O 0 I/O 1 DQ46 DQ47 I/O 2 I/O 3 DM DQS I/O 0 I/O 1 D14 I/O 2 I/O 3 DM WP A0 A1 A2 SA0 SA1 SA2 SDA D32 DQS15 DQS DQ48 DQ49 DQ50 DQ51 I/O 0 I/O 1 I/O 2 I/O 3 DM DQS I/O 0 I/O 1 D6 I/O 2 I/O 3 DM DQS D24 DQS7 DQ52 DQ53 I/O 0 I/O 1 DQ54 DQ55 I/O 2 I/O 3 DM DQS I/O 0 I/O 1 D15 I/O 2 I/O 3 DM D33 DQS16 DQ56 DQ57 I /O 0 I /O 1 I /O 2 DQ58 DQ59 DQS DM D7 I /O 3 I/ O 0 I/ O 1 I/ O 2 DQS DM DQ60 DQ61 D25 I /O 0 DQ62 DQ63 I/ O 3 R E G I S T E R BA0-BA1 A0-A13 CKE0 CKE1 ODT0 ODT1 RBA 0-RBA1 RA0-RA 13 : SDRAMs D18-D35 BA0-BA1 : SDRAMs D0-D35 A0-A13 : SDRAMs D 0-D35 : SDRAMs D0-D35 : SDRAMs D0-D35 RCKE0 RCKE1 RODT 0 RODT 1 DM I/O 0 I/O 1 I/O 2 I/O 3 D16 DQS DM D34 Signals for Address and Command Parity Function VSS C0 VDD C1 Register A 1 PAR_IN PAR_IN PPO VDD C0 VDD C1 Register B1 PAR_IN PPO 100K Ohms : SDRAMs D0-D35 CKE0 : SDRAMs D0-D17 CKE1 : SDRAMs D18-D35 ODT0 : SDRAMs D0 -D17 ODT1 : SDRAMs D18-D35 PCK7 Notes : DQS I /O 1 I /O 2 I /O 3 : SDRAMs D0 -D17 05/2007 I/O 1 I/O 2 I/O 3 D9 DQS10 DQ8 DQ9 DQ10 DQ11 REV 1.3 DQS I/O 0 I /O 1 I /O 2 I /O 3 DQ6 DQ7 I/ O 3 DM I /O 0 CK0 1. DQ-to-I/O wiring may be changed within a byte. 2. Resistor values without noted are 22 Ohms +/- 5% 3. and alternate between the bottom and surface side of DIMM. P L L PCK0-PCK6, PCK8 ,PCK9 PCK7 , , SDRAMs D0 -D35 CK SDRAMs D0 -D35 Register CK Register 8 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Serial Presence Detect -- Part 1 of 2 (512MB) 64Mx72 1 RANK REGISTERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Serial PD Data Entry (Hexadecimal) SPD Entry Value Byte Description 0 Number of Serial PD Bytes Written during Production 1 Total Number of Bytes in Serial PD device 2 Fundamental Memory Type 3 4 5 6 7 Reserved 8 Voltage Interface Level of this Assembly 9 DDR2 SDRAM Device Cycle Time at CL=5 10 DDR2 SDRAM Device Access Time from Clock at CL=5 11 DIMM Configuration Type 12 Refresh Rate/Type 13 Primary DDR2 SDRAM Width 14 Error Checking DDR2 SDRAM Device Width 15 Reserved 16 Note DDR2-667 DDR2-800 DDR2-800 DDR2-667 DDR2-800 DDR2-800 -3C -25D -25C -3C -25D -25C 128 80 80 80 256 08 08 08 DDR2-SDRAM 08 08 08 Number of Row Addresses on Assembly 14 0E 0E 0E Number of Column Addresses on Assembly 10 0A 0A 0A Number of DIMM Bank 1 rank, Height=30mm 60 60 60 Data Width of Assembly X72 48 48 48 Undefined 00 00 00 SSTL_1.8 3ns 0.45ns 05 05 05 2.5ns 30 25 25 0.4ns 45 40 40 parity 06 06 06 7.8us/SR 82 82 82 X8 08 08 08 00 X8 08 00 Undefined Undefined 00 00 00 DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C 0C 0C 17 DDR2 SDRAM Device Attributes: Number of Device Banks 4 04 04 04 18 DDR2 SDRAM Device Attributes: CAS Latencies Supported 38 70 38 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: 3/4/5 4/5/6 3/4/5 <4.10mm 01 01 01 Reg. DIMM 01 01 01 PLL=1, Register =1 04 04 04 Support weak driver, 50ohm ODT, and PASR 07 07 07 3D 22 DDR2 SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=5 3.75ns 3ns 3.75ns 3D 30 24 Maximum Data Access Time from Clock at CL=5 0.5ns 0.45ns 0.5ns 50 45 50 25 Minimum Clock Cycle Time at CL=3 5ns 3.75ns 5ns 50 3D 50 26 Maximum Data Access Time from Clock at CL=3 0.5ns 0.6ns 60 50 60 27 Minimum Row Precharge Time (tRP) 12.5ns 3C 3C 32 28 Minimum Row Active to Row Active delay (tRRD) 1E 1E 1E 29 Minimum RAS to CAS delay (tRCD) 3C 3C 32 30 Minimum RAS Pulse Width (tRAS) 45ns 2D 2D 2D 31 Module Bank Density 512MB 80 80 80 32 Address and Command Setup Time Before Clock (tIS) 33 0.6ns 15ns 7.5ns 15ns 12.5ns 0.2ns 0.17ns 20 17 17 Address and Command Hold Time After Clock (tIH) 0.275ns 0.25ns 27 25 25 34 Data Input Setup Time Before Clock (tDS) 0.10ns 0.05ns 10 05 05 35 Data Input Hold Time After Clock (tDH) 0.17ns 0.12ns 17 12 12 36 Write Recovery Time (tWR) 15.0ns 3C 3C 3C 37 Internal Write to Read Command delay (tWTR) 7.5ns 1E 1E 1E 38 Internal Read to Precharge delay (tRTP) 7.5ns 1E 1E 1E 39 Reserved Undefined 00 00 00 40 Extension of Byte 41 tRC and Byte 42 tRFC The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns 00 00 30 41 Minimum Core Cycle Time (tRC) 3C 3C 39 REV 1.3 05/2007 60ns 57ns 9 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Serial Presence Detect -- Part 2 of 2 (512MB) 64Mx72 1 RANK REGISTERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Serial PD Data Entry (Hexadecimal) SPD Entry Value Byte Description DDR2-667 DDR2-800 DDR2-800 DDR2-667 DDR2-800 DDR2-800 -3C -25D -25C -3C -25D -25C 42 Min. Auto Refresh Command Cycle Time (tRFC) 105ns 43 Maximum Clock Cycle Time (tCK) 44 Max. DQS-DQ Skew Factor (tDQS) 0.24ns 45 Read Data Hold Skew Factor (tQHS) 0.34ns 46 PLL Relock Time 47 Tcasemax 48 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) 6C 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) 4.7C 51 DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) 5.85C 53 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3P fast) 54 69 8.0ns 0.2ns 69 80 80 80 18 14 14 22 1E 1E 0F 0F 0F 53 50 50 7A 7A 7A 7.2C 53 63 63 6C 2F 3C 3C 37 37 37 7.05C 27 2F 2F 3.85C 4.55C 4D 5B 5B DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3P slow) 1.05C 1.05C 2A 2A 2A 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) 15.2C 18.4C 4D 5C 5C 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) 19C 20.5C 26 29 29 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) 20C 28 28 28 58 Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) 00 00 00 00 59 Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) 00 00 00 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) 00 00 00 00 61 Resister Case Temperature Rise from Ambient due to Register Active/Mode Bit(DT Register Active/Mode Bit) 00 00 00 00 62 SPD Revision 1.2 12 12 12 63 Checksum Data Checksum Data 5C 60 7C 15.0s 11.2 64-71 Manufacturer's JEDEC ID Code 72 Module Manufacturing Location 73-91 Module Part number 0.3ns 69 10 61C/W 0.825 REV 1.3 05/2007 7F7F7F0B00000000 Manufacturing code -- Module Part Number in ASCII -- Undefined -- 92-255 Module Revision Code Note: NT512T72U89B0BV-3C NT512T72U89B0BV-25D NT512T72U89B0BV-25C NANYA Note 4E54353132543732553839423042562D334320 4E54353132543732553839423042562D323544 4E54353132543732553839423042562D323543 10 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1 NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Serial Presence Detect -- Part 1 of 2 (1GB) 128Mx72 1 RANK REGISTERED DDR2 SDRAM DIMM based on 128Mx4, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Serial PD Data Entry (Hexadecimal) SPD Entry Value Byte Description 0 Number of Serial PD Bytes Written during Production 1 Total Number of Bytes in Serial PD device 2 Fundamental Memory Type 3 4 5 6 7 Reserved 8 Voltage Interface Level of this Assembly 9 DDR2 SDRAM Device Cycle Time at CL=5 10 DDR2 SDRAM Device Access Time from Clock at CL=5 11 DIMM Configuration Type 12 Refresh Rate/Type 13 Primary DDR2 SDRAM Width 14 Error Checking DDR2 SDRAM Device Width 15 Reserved 16 Note DDR2-667 DDR2-800 DDR2-800 DDR2-667 DDR2-800 DDR2-800 -3C -25D -25C -3C -25D -25C 128 80 80 80 256 08 08 08 DDR2-SDRAM 08 08 08 Number of Row Addresses on Assembly 14 0E 0E 0E Number of Column Addresses on Assembly 11 0B 0B 0B Number of DIMM Bank 1 rank, Height=30mm 60 60 60 Data Width of Assembly X72 48 48 48 Undefined 00 00 00 SSTL_1.8 3ns 0.45ns 05 05 05 2.5ns 30 25 25 0.4ns 45 40 40 parity 06 06 06 7.8s/SR 82 82 82 X4 04 04 04 04 X4 04 04 Undefined 00 00 00 DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C 0C 0C 17 DDR2 SDRAM Device Attributes: Number of Device Banks 4 04 04 04 18 DDR2 SDRAM Device Attributes: CAS Latencies Supported 38 70 38 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: 22 DDR2 SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=5 3.75ns 3ns 24 Maximum Data Access Time from Clock at CL=5 0.5ns 0.45ns 25 Minimum Clock Cycle Time at CL=3 5.0ns 3.75ns 26 Maximum Data Access Time from Clock at CL=3 0.6ns 0.5ns 27 Minimum Row Precharge Time (tRP) 12.5ns 28 Minimum Row Active to Row Active delay (tRRD) 29 Minimum RAS to CAS delay (tRCD) 30 Minimum RAS Pulse Width (tRAS) 31 Module Bank Density 01 01 01 32 Address and Command Setup Time Before Clock (tIS) 0.2ns 0.17ns 20 17 17 33 Address and Command Hold Time After Clock (tIH) 0.27ns 0.25ns 27 25 25 34 Data Input Setup Time Before Clock (tDS) 0.10ns 0.05ns 10 05 05 35 Data Input Hold Time After Clock (tDH) 0.17ns 0.12ns 17 12 12 36 Write Recovery Time (tWR) 15.0ns 3C 3C 3C 37 Internal Write to Read Command delay (tWTR) 7.5ns 1E 1E 1E 38 Internal Read to Precharge delay (tRTP) 39 Reserved 40 Extension of Byte 41 tRC and Byte 42 tRFC 41 Minimum Core Cycle Time (tRC) REV 1.3 05/2007 3/4/5 4/5/6 3/4/5 <4.10mm 01 01 01 Reg. DIMM 01 01 01 PLL=1, Register=2 05 05 05 Support weak driver, 50ohm ODT, and PASR 07 07 07 3.75ns 3D 30 3D 0.5ns 50 45 50 5.0ns 50 3D 50 0.6ns 60 50 60 3C 3C 32 1E 1E 1E 3C 3C 32 2D 2D 2D 15ns 7.5ns 15ns 12.5ns 45ns 1GB 7.5ns 1E 1E 1E Undefined 00 00 00 The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns 00 00 30 3C 3C 39 60ns 57ns 11 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Serial Presence Detect -- Part 2 of 2 (1GB) 128Mx72 1 RANK REGISTERED DDR2 SDRAM DIMM based on 128Mx4, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Serial PD Data Entry (Hexadecimal) SPD Entry Value Byte Description DDR2-667 DDR2-800 DDR2-800 DDR2-667 DDR2-800 DDR2-800 -3C -25D -25C -3C -25D -25C 42 Min. Auto Refresh Command Cycle Time (tRFC) 105ns 43 Maximum Clock Cycle Time (tCK) 44 Max. DQS-DQ Skew Factor (tDQS) 0.24ns 45 Read Data Hold Skew Factor (tQHS) 0.34ns 46 PLL Relock Time 47 Tcasemax 48 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) 6C 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) 4.7C 51 DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) 5.85C 53 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3P fast) 3.85C 54 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3P slow) 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) 15.2C 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) 19C 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) 58 69 8.0ns 0.2ns 69 80 80 80 18 14 14 22 1E 1E 0F 0F 0F 53 50 50 7A 7A 7A 7.2C 53 63 63 6.0C 2F 3C 3C 37 37 37 7.05C 27 2F 2F 4.55C 4D 5B 5B 2A 2A 2A 18.4C 4C 5C 5C 20.5C 26 29 29 20C 28 28 28 Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) 00 00 00 00 59 Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) 00 00 00 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) 00 00 00 00 61 Resister Case Temperature Rise from Ambient due to Register Active/Mode Bit(DT Register Active/Mode Bit) 00 00 00 00 62 SPD Revision 1.2 12 12 12 63 Checksum Data Checksum Data D6 E3 FF 15s 11.2 64-71 Manufacturer's JEDEC ID Code 72 Module Manufacturing Location 73-91 Module Part number NT1GT72U4PB0BV-3C NT1GT72U4PB0BV-25D NT1GT72U4PB0BV-25C REV 1.3 05/2007 10 61C/W 0.825 1.05C NANYA 7F7F7F0B00000000 Manufacturing code -- Module Part Number in ASCII -- Undefined -- 92-255 Module Revision Code Note: 1. 2. 3. 0.3ns 69 Note 4E543147543732553450423042562D33432020 4E543147543732553450423042562D32354420 4E543147543732553450423042562D32354320 12 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1 NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Serial Presence Detect -- Part 1 of 2 (2GB) 256Mx72 2 RANKS REGISTERED DDR2 SDRAM DIMM based on 128Mx4, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Serial PD Data Entry (Hexadecimal) SPD Entry Value Byte Description 0 Number of Serial PD Bytes Written during Production 1 Total Number of Bytes in Serial PD device 2 Fundamental Memory Type 3 4 5 6 7 Reserved 8 Voltage Interface Level of this Assembly 9 DDR2 SDRAM Device Cycle Time at CL=5 10 DDR2 SDRAM Device Access Time from Clock at CL=5 11 DIMM Configuration Type 12 Refresh Rate/Type 13 Primary DDR2 SDRAM Width 14 Error Checking DDR2 SDRAM Device Width 15 Reserved 16 Note DDR2-667 DDR2-800 DDR2-800 DDR2-667 DDR2-800 DDR2-800 -3C -25D -25C -3C -25D -25C 128 80 80 80 256 08 08 08 DDR2-SDRAM 08 08 08 Number of Row Addresses on Assembly 14 0E 0E 0E Number of Column Addresses on Assembly 11 0B 0B 0B Number of DIMM Bank 2 rank, Height=30mm 61 61 61 Data Width of Assembly X72 48 48 48 Undefined 00 00 00 SSTL_1.8 3ns 0.45ns 05 05 05 2.5ns 30 25 25 0.4ns 45 40 40 parity 06 06 06 7.8s/SR 82 82 82 X4 04 04 04 04 X4 04 04 Undefined 00 00 00 DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C 0C 0C 17 DDR2 SDRAM Device Attributes: Number of Device Banks 4 04 04 04 18 DDR2 SDRAM Device Attributes: CAS Latencies Supported 38 70 38 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: 22 DDR2 SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=5 3.75ns 3ns 24 Maximum Data Access Time from Clock at CL=5 0.5ns 0.45ns 25 Minimum Clock Cycle Time at CL=3 5.0ns 3.75ns 26 Maximum Data Access Time from Clock at CL=3 0.6ns 0.5ns 27 Minimum Row Precharge Time (tRP) 12.5ns 28 Minimum Row Active to Row Active delay (tRRD) 29 Minimum RAS to CAS delay (tRCD) 30 Minimum RAS Pulse Width (tRAS) 31 Module Bank Density 01 01 01 32 Address and Command Setup Time Before Clock (tIS) 0.2ns 0.17ns 20 17 17 33 Address and Command Hold Time After Clock (tIH) 0.27ns 0.25ns 27 25 25 34 Data Input Setup Time Before Clock (tDS) 0.1ns 0.05ns 10 05 05 35 Data Input Hold Time After Clock (tDH) 0.17ns 0.12ns 17 12 12 36 Write Recovery Time (tWR) 15.0ns 3C 3C 3C 37 Internal Write to Read Command delay (tWTR) 7.5ns 1E 1E 1E 38 Internal Read to Precharge delay (tRTP) 39 Reserved 40 Extension of Byte 41 tRC and Byte 42 tRFC 41 Minimum Core Cycle Time (tRC) REV 1.3 05/2007 3/4/5 4/5/6 3/4/5 <4.10mm 01 01 01 Reg. DIMM 01 01 01 PLL=1, Register 07=4,05=2 07 05 05 Support weak driver, 50ohm ODT, and PASR 07 07 07 3.75ns 3D 30 3D 0.5ns 50 45 50 5.0ns 50 3D 50 0.6ns 60 50 60 3C 3C 32 1E 1E 1E 3C 3C 32 2D 2D 2D 15ns 7.5ns 15.0ns 12.5ns 45.0ns 1GB 7.5ns 1E 1E 1E Undefined 00 00 00 The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns 00 00 30 3C 3C 39 60ns 57ns 13 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Serial Presence Detect -- Part 2 of 2 (2GB) 256Mx72 2 RANKS REGISTERED DDR2 SDRAM DIMM based on 128Mx4, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Serial PD Data Entry (Hexadecimal) SPD Entry Value Byte Description DDR2-667 DDR2-800 DDR2-800 DDR2-667 DDR2-800 DDR2-800 -3C -25D -25C -3C -25D -25C 42 Min. Auto Refresh Command Cycle Time (tRFC) 105ns 43 Maximum Clock Cycle Time (tCK) 44 Max. DQS-DQ Skew Factor (tDQS) 0.24ns 45 Read Data Hold Skew Factor (tQHS) 0.34ns 46 PLL Relock Time 47 Tcasemax 48 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) 6C 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) 4.7C 51 DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) 5.85C 53 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3P fast) 3.85C 54 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3P slow) 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) 15.2C 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) 19C 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) 58 69 8.0ns 0.2ns 69 80 80 80 18 14 14 22 1E 1E 0F 0F 0F 53 50 50 7A 7A 7A 7.2C 53 63 63 5.3C 2F 35 35 37 37 37 7.05 27 2F 2F 4.55 4D 5B 5B 2A 2A 2A 18.4C 4C 5C 5C 20.5C 26 29 29 20C 28 28 28 Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) 00 00 00 00 59 Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) 00 00 00 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) 00 00 00 00 61 Resister Case Temperature Rise from Ambient due to Register Active/Mode Bit(DT Register Active/Mode Bit) 00 00 00 00 62 SPD Revision 1.2 12 12 12 63 Checksum Data Checksum Data D9 DD F9 15.0s 11.2 64-71 Manufacturer's JEDEC ID Code 72 Module Manufacturing Location 73-91 Module Part number NT2GT72U4NB0BV-3C NT2GT72U4NB0BV-25D NT2GT72U4NB0BV-25C REV 1.3 05/2007 10 61C/W 0.825C 1.05C NANYA 7F7F7F0B00000000 Manufacturing code -- Module Part Number in ASCII -- Undefined -- 92-255 Module Revision Code Note: 1. 2. 3. 0.3ns 69 Note 4E54324754373255344E423042562D33432020 4E54324754373255344E423142562D32354420 4E54324754373255344E423042562D32354320 14 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. 1 NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Absolute Maximum Ratings Symbol VIN, VOUT Parameter Rating Units Voltage on I/O pins relative to VSS -0.5 to 2.3 V V Voltage on VDD supply relative to VSS -1.0 to 2.3 VDDQ Voltage on VDDQ supply relative to VSS -0.5 to 2.3 V HSTG Storage Humidity (without condensation) 5 to 95 % VDD Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating conditions Symbol Parameter TCASE Operating Temperature (Ambient) Rating Units Note 1,2,3 0 to 95 C -50 to 100 C TSTG Storage Temperature (Plastic) HSTG Storage humidity (without condensation) 5 to 95 % HOPR Operating Humidity (relative) 10 to 90 % PBAR Barometric pressure (operating & storage) 105 to 69 K Pascal Note: 1. 2. 3. 4. 4 Case temperature is measured at top and center side of any DRAMs. tCASE > 85C tREFI = 3.9 6s All DRAM specification only support 0C < tCASE < 85C Up to 9850 ft. DC Electrical Characteristics and Operating Conditions (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) Symbol VDD VDDQ VSS, VSSQ VREF Min Max Units Notes Supply Voltage Parameter 1.7 1.9 V 1 I/O Supply Voltage 1.7 1.9 V 1 Supply Voltage, I/O Supply Voltage I/O Reference Voltage 0 0 V 0.49VDDQ 0.51VDDQ V 1, 2 V 1 1 VIH (DC) Input High (Logic1) Voltage VREF + 0.125 VDDQ + 0.3 VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.125 V -5 5 6A IL Input / Output Leakage Current Note: 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VID is the magnitude of the difference between the input level on CK and the input level on . REV 1.3 05/2007 15 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs) PC2-5300 (-3C) PC2-6400 (-25D) PC2-6400 (-25C) Unit I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 996 1094 1094 mA I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 1144 1243 1243 mA I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 323 323 323 mA I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 748 748 748 mA I DD2Q Precharge quiet standby current; All banks idle; tCK=tCK(IDD); CKE is HIGH; is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. 649 758 758 mA I DD3PF Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Fast PDN Exit MRS(12) = 0mA 580 639 639 mA I DD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Slow PDN Exit MRS(12) = 1mA 343 343 343 mA I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 748 847 847 mA I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 1639 1689 1689 mA I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 1639 1738 1738 mA I DD5 Auto-Refresh Current: tRC = tRFC (MIN) 1837 2134 2134 mA I DD6 Self-Refresh Current: CKE 0.2V 70 70 70 mA I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1936 2184 2184 mA Symbol Parameter/Condition Note: Module IDD was calculated from component IDD. It may differ from the actual measurement. REV 1.3 05/2007 16 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V (1GB, 1 Rank, 64Mx8 DDR2 SDRAMs) PC2-5300 (-3C) PC2-6400 (-25D) PC2-6400 (-25C) Unit I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1826 2024 2024 mA I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 2123 2321 2321 mA I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 480 480 480 mA I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 1331 1331 1331 mA I DD2Q Precharge quiet standby current; All banks idle; tCK=tCK(IDD); CKE is HIGH; is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. 1133 1351 1351 mA I DD3PF Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Fast PDN Exit MRS(12) = 0mA 995 1113 1113 mA I DD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Slow PDN Exit MRS(12) = 1mA 519 519 519 mA I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1331 1529 1529 mA I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 3025 3124 3124 mA I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 3025 3223 3223 mA I DD5 Auto-Refresh Current: tRC = tRFC (MIN) 3421 4015 4015 mA I DD6 Self-Refresh Current: CKE 0.2V 139 139 139 mA I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 3707 4202 4202 mA Symbol Parameter/Condition Note: Module IDD was calculated from component IDD. It may differ from the actual measurement. REV 1.3 05/2007 17 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V (2GB, 2 Rank, 64Mx8 DDR2 SDRAMs) PC2-5300 (-3C) PC2-6400 (-25D) PC2-6400 (-25C) Unit I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 2816 3212 3212 mA I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 3113 3509 3509 mA I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 619 619 619 mA I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 2321 2321 2321 mA I DD2Q Precharge quiet standby current; All banks idle; tCK=tCK(IDD); CKE is HIGH; is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. 1925 2361 2361 mA I DD3PF Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Fast PDN Exit MRS(12) = 0mA 1648 1885 1885 mA I DD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Slow PDN Exit MRS(12) = 1mA 698 698 698 mA I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 2321 2717 2717 mA I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 4015 4312 4312 mA I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 4015 4411 4411 mA I DD5 Auto-Refresh Current: tRC = tRFC (MIN) 4411 5203 5203 mA I DD6 Self-Refresh Current: CKE 0.2V 278 278 278 mA I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 4697 5390 5390 mA Symbol Parameter/Condition Note: Module IDD was calculated from component IDD. It may differ from the actual measurement. REV 1.3 05/2007 18 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 1 of 2) Symbol DDR2-667 -3C Parameter DDR2-800 -25D/25C Min. Max. Min. Unit Max DQ output access time from CK/ -0.45 +0.45 -0.4 +0.4 ns tDQSCK DQS output access time from CK/ -0.4 +0.4 -0.35 +0.35 ns tCH (avg) Average CK high-level width 0.48 0.52 0.48 0.52 tCK (avg) tCL (avg) Average CK low-level width 0.48 0.52 0.48 0.52 tCK (avg) Min(tCH (abs), tCL(abs)) - Min(tCH (abs), tCL(abs)) - ns 3 8 2.5 8 ns 175 - 125 - ps tAC tHP Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time tCK (avg) Clock Cycle Time tDH (base) DQ and DM input hold time tDS (base) DQ and DM input setup time 100 - 50 - ps tIPW Input pulse width 0.60 - 0.60 - tCK (avg) tDIPW DQ and DM input pulse width (each input) 0.35 - 0.35 - tCK (avg) tAC max ns tHZ Data-out high-impedance time from CK/ - tAC max - tLZ(DQ) Data-out low-impedance time from CK/ 2tAC min tAC max 2tAC min tAC max ns tLZ(DQS) DQS low-impedance time from CK/ tAC min tAC max tAC min tAC max ns - 0.24 - 0.20 ns tDQSQ DQS-DQ skew (DQS & associated DQ signals) tQHS Data hold Skew Factor tQH Data output hold time from DQS - 0.34 - 0.30 ns tHP -tQHS - tHP -tQHS - ns Write command to 1st DQS latching transition -0.25 0.25 -0.25 0.25 tCK (avg) DQS input low (high) pulse width (write cycle) 0.35 - 0.35 - tCK (avg) tDSS DQS falling edge to CK setup time (write cycle) 0.20 - 0.20 - tCK (avg) tDSH DQS falling edge hold time from CK (write cycle) 0.20 - 0.20 - tCK (avg) tMRD Mode register set command cycle time 2 - 2 - nCK tWPST Write postamble 0.40 0.60 0.40 0.60 tCK (avg) tDQSS tDQSL,(H) Write preamble 0.35 - 0.35 - tCK (avg) tIH (base) Address and control input hold time 275 - 250 - ps tIS (base) Address and control input setup time 200 - 175 - ps Read preamble 0.9 1.1 0.9 1.1 tCK (avg) tRPST Read postamble 0.4 0.6 0.4 0.6 tCK (avg) tDelay Minimum time clocks remains ON after CKE asynchronously drops Low tIS + tCK + tIH - tIS + tCK + tIH - ns tRFC Refresh to active/Refresh command time tWPRE tRPRE REV 1.3 05/2007 105 Notes ns 19 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 2 of 2) Symbol DDR2-667 -3C Parameter Min. DDR2-800 -25D/-25C Max. Min. Unit Max. tREFI Average Periodic Refresh Interval (85C < TCASE 7 95C) 3.9 6s tREFI Average Periodic Refresh Interval (0C 7 TCASE 7 85C) 7.8 6s tRRD Active bank A to Active bank B command 7.5 - 7.5 - ns tFAW For Activate window 37.5 - 35 - ns 2 - 2 - nCK 15 tCCD to tWR Write recovery time - 15 - ns tDAL Auto precharge write recovery + precharge time WR +tRP - WR +tRP - nCK tWTR Internal write to read command delay 7.5 - 7.5 - ns tRTP Internal read to precharge command delay 7.5 - 7.5 - ns tXSNR Exit self refresh to a Non-read command tRFC +10 - tRFC +10 - ns tXSRD Exit self refresh to a Read command 200 - 200 - nCK Exit precharge power down to any Non- read command 2 - 2 - nCK tXARD Exit active power down to read command 2 - 2 - nCK tXARDS Exit active power down to read command tXP Notes 7-AL - 8-AL - nCK tCKE CKE minimum pulse width 3 - 3 - nCK tOIT OCD drive mode output delay 0 12 0 12 ns ODT tAOND ODT turn-on delay tAON ODT turn-on tAONPD ODT turn-on (Power down mode) tAOFD ODT turn-off delay tAOF ODT turn-off 2 2 2 2 nCK tAC(min) tAC(max) +0.7 tAC(min) tAC(max) +0.7 ns tAC(min) +2 2tCK + tAC(max)+1 tAC(min) +2 2tCK + tAC(max)+1 ns 2.5 2.5 2.5 2.5 nCK tAC(min) tAC(max)+ 0.6 tAC(min) tAC(max)+ 0.6 ns tAOFPD ODT turn-off (Power down mode) tAC(min) +2 2.5tCK + tAC(max)+1 tAC(min) +2 2.5tCK + tAC(max)+1 ns tANPD ODT to power down entry latency 3 - 3 - nCK tAXPD ODT power down exit latency 8 - 8 - nCK tRAS Row Active Time 45 70000 45 70000 ns tRCD RAS to CAS delay 15 - 15 (-25D) 12.5 (-25C) - ns tRC Row Cycle Time 60 - 60 (-25D) 57.5 (-25C) ns tRP Row Precharge Time 15 - 15 (-25D) 12.5 (-25C) ns Speed Grade Definition REV 1.3 05/2007 20 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Package Dimensions (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs) 3& 8 8 8 8 !8 8 8 ! ( $. : ;< 8 8 8 8 8 8! 8 8 8 8 . " ! 8 " 8 8 8! 8 . 8 8 8! 9 8 ,.4 8 9 8 ! 8 8 8 8 8 8 ,- )$ +)$ 9 9 9 8 9 8 8 8 . 3+. # 8 8 % 8 ! ?).$# " 8 8 . 8 .14 8 8 ./=1 > .4 .+ )1 $ +*9 8 : 8 < 0) $$ +.4 > $ $. . ,8 - . $ : )14 $< *Device position is only for reference. REV 1.3 05/2007 21 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Package Dimensions (1GB, 1 Rank, 128Mx4 DDR2 SDRAMs) 3& 8 8 8 8 !8 8 8 ! ( $. : ;< 8 8 8 8 8 8! 8 8 8 . " 8 8 8 . 8 8 " ! 8 % 8 9 8 9 8 8 8 ( $. 8 ! . 8 8 8! 9 8 ,.4 8 9 8 ! 8 8 8 8 8 8 3+. # ?).$# " 8 8 8! 8 . ,- )$ +)$ 9 9 .14 8 8 ./=1 > .4.+ )1 $ +*9 8 : 8 < 0) $$ +.4 > $ $. . ,8 - . $ : )14 $< *Device position is only for reference. REV 1.3 05/2007 22 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Package Dimensions (2GB, 2 Ranks, 128Mx4 DDR2-667 SDRAMs) 3& 8 8 8 8 !8 8 8 ! ( $. : ;< 8 8 8 8 8 8! 8 ( $. 8 8 . " 8 8 8 . 8 8 " ! 8 % 8 9 8 9 8 8 8 ( $. ( $. 8 ! . 8 8 8! 9 8 ,.4 8 9 8 ! 8 8 8 8 8 8 3+. # ?).$# " 8 8 8! 8 . ,- )$ +)$ 9 9 .14 8 8 ./=1 > .4.+ )1 $ +*9 8 : 8 < 0) $$ +.4 > $ $. . ,8 - . $ : )14 $< *Device position is only for reference. REV 1.3 05/2007 23 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Package Dimensions (2GB, 2 Ranks, 128Mx4 DDR2-800 SDRAMs) FRONT 131.35 5.171 128.95 5.077 SIDE 4.00 0 .157 Detail A 2.5 0.098 Detail B BACK 63.00 2. 30 0.091 17.80 0.700 1 0.0 0. 394 Register PLL 30.00 1. 180 (2X) 4.00 0.157 133.35 5.250 1.27 +/- 0.10 0.050 +/- 0.004 55.00 2.17 Register 2.48 Detail B 2 .50 0 .098 4. 00 0.157 3. 80 0. 15 Detail A 5.00 0.197 0.8 +/- 0.5 Width 0.003 +/- 0.020 1.00 Pitch 0.039 1 .50 +/- 0.1 0 .05 +/- 0.04 Note: All dimensions are typical with tolerances of+/- 0.15 (0.006) unless otherwise stated. Units: Millimeters (Inches) *Device position is only for reference. REV 1.3 05/2007 24 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT2GT72U4NB0BV / NT2GT72U4NB1BV NT512T72U89B0BV / NT1GT72U4PB0BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Revision Log Rev Date 0.1 09/2006 Preliminary Release. 1.0 09/2006 Official Release 1.1 02/2007 Update operating condition. 1.2 04/2007 Update SPD code (Byte 21 & Byte 63) 1.3 04/2007 Added DDR2-800 information and 1st Version PCB item information. REV 1.3 05/2007 Modification 25 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.