PD69208M and PD69200 Datasheet
8-Port PSE PoE Manager and PSE PoE Controller
PD-000303451. 5.0 11/18
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aerospace & defense, communications, data center and industrial markets. Products include high-performance and
radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products;
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globally. Learn more at www.microsemi.com.
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 iii
Contents
1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Revision 5.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Revision 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Revision 3.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Revision 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.5 Revision 1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.6 Revision 1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.7 Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Typical PoE Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Digital Block Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 PD Detection Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3 Classification Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.4 Current Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.5 Main Power MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.6 Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.7 Power on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.8 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.9 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.10 SPI Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.10.1 PD69208M SPI Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.10.2 Broadcast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.10.3 PD69200 I2C Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 PD69200 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 PD69200 Features Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 PD69208M Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3.1 Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3.2 Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3.3 Port Real Time Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3.4 Port Current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3.5 Port Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3.6 Main Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3.7 Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3.8 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3.9 Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4 PD69208M Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1 Pin Configuration and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.1 PD69200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 iv
5.2.2 PD69208M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.3 PD69200 Recommended PCB Layout for 32 Pin QFN 5mm x 5mm . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.4 PD69208M Recommended PCB Layout for 56-Pin QFN 8mm x 8mm . . . . . . . . . . . . . . . . . . . . . . . . . 25
6 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1 PD69200 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2 PD69208M Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3 PD69208M Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4 Recommended Solder Reflow Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.5 Tape and Reel—Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.5.1 PD69200 Tape and Reel Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.5.2 PD69208M Tape and Reel Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.6 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.1 PD Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2 Legacy (Reduced Capacitor) Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.3 Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.4 Port Start Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.5 Over-Load Detection and Port Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.6 Disconnect Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.7 IC Thermal Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.8 Over-Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.9 VMAIN Out of Range Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.10 2-Pair and 4-Pair Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.11 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.12 Port Power Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.13 Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.14 System OK Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.15 Interrupt Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.16 Port Matrix Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.17 Power Good Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.18 LED Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.19 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 v
Figures
Figure 1 Typical PoE Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2 PD69208M Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3 SPI Detailed Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4 PD69200 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5 PD69208M Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6 PD69200 Top-Layer Copper PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 7 PD69200 Top-Layer Solder Paste and Vias PCB Layout for Thermal Pad Array . . . . . . . . . . . . . 24
Figure 8 Top-Copper Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9 Top-Solder Paste Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 10 Top-Layer Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 11 BOT and Internal Layers Copper Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 12 Top-Layer Pin Geometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 13 PD69200 Package Outline Drawing (32 Pin QFN 5 mm x 5 mm) . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 14 PD69208M Package Drawing (56 Pin QFN 8 mm x 8 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 15 Classification Reflow Profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 16 PD69200 Tape Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 17 PD69200 Reel Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 18 PD69208M Tape and Reel Pin-1 Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 19 PD69208M Tape Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 20 PD69208M Reel Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 21 4-Pair PoE System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 22 Typical IEEE802.3at Port PoE Voltage Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 23 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 vi
Tables
Table 1 SPI Communication – Packet Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2 PD69208M SPI Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3 PD69208M Broadcast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4 SPI Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5 I2C Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6 PD69200 Features Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 7 PD69208M Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 8 PD69208M Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 9 PD69208M Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 10 PD69208M Port Real Time Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 11 PD69208M Port Current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 12 PD69208M Port Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 13 PD69208M Main Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 14 PD69208M Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 15 PD69208M Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 16 PD69208M Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 17 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 18 PD69200 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 19 PD69208M Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 20 PD69200 Package Outline Dimensions and Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 21 PD69208MPackage Outline Dimensions and Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 22 PD69208M Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 23 PD69200 Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 24 Classification Reflow Profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 25 Pb-Free Process – Package Classification Reflow Temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 26 PD69200 Tape Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 27 PD69200 Reel Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 28 PD69208M Tape Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 29 PD69208M Reel Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 30 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 31 PD69208M Manufacturing and Ordering Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Revision History
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 1
1 Revision History
The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the most current publication.
1.1 Revision 5.0
Revision 5.0 of this document was published in November 2018. The following was a summary of the
changes made in this revision:
• Updated the Features and Applications details. For more information, see Features, page 4 and
Applications, page 4.
• Port real time protection details are updated for IPORT
, ILIM, ICUT
, IUDL, PPWR, and TMPS. For more
information, see Table 10, page 14.
• Port current monitoring information is updated for accuracy. For more information, see Table 11,
page 14.
• Main voltage information is updated for accuracy. For more information, see Ta ble 13 , page 15.
• The PD69200 pin diagram is updated. For more information, see Figure 4, page 18.
• The Top-Layer Pin Geometry measurement is updated. For more information, see Figure 12,
page 28.
• The PD692000 Thermal Specifications table is added. For more information, see Table 23, page 31.
• The company name Freescale is replaced with NXP across the document.
• Updated Figures 8 - 12. For more information, see Figure 8, page 25,Figure 9, page 26, Figure 10,
page 27, Figure 11, page 27, and Figure 12, page 28.
• Added table footnotes for D, VVVV, and SS. For more information, see the Ordering Information,
page 41.
1.2 Revision 4.0
Revision 4.0 of this document was published in February 2018. The following was a summary of the
changes:
• Preliminary designation was removed.
• Thermal specifications were updated. For more information, see PD69200 Thermal Specifications,
page 31.
• The tape specification was updated. For more information, see Figure 19, page 35.
• Tape mechanical data was added. For more information, see Table 28, page 35.
• Ordering part numbers were updated. For more information, see Ordering Information, page 41.
1.3 Revision 3.0
Revision 3.0 of this document was published in November 2017. The following was a summary of the
changes:
• Maximum storage temperature value is no longer preliminary.
• The link to stencil and via plug recommendations was updated.
• Application information was updated.
• Maximum slew rate requirement of 100 mS was added.
• Manufacturing and ordering part number information was updated.
• Updated revision 2.0 history to include entry for the redefinition of quiescent current in terms of port
threshold.
1.4 Revision 2.0
Revision 2.0 of this document was published in September 2017. The following was a summary of the
changes:
• Updated the recommended PCB layout for better manufacturability.
• Redefined quiescent current in terms of port threshold.
• Added the PD69208M Manufacturing and Ordering Part Numbers table.
Revision History
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 2
• Added a note about I2C communication configuration.
• Added table footnotes for ESD (HBM and CDM).
• Updated the main voltage monitoring table for accuracy data.
• Updated the Peak Classification Temperature (TP).
• Updated the description for pin 24 for PD69200.
• Updated the description for pin 19 for PD69208M.
• Updated the thermal specifications table.
• Changed the notation from VPORT_NEGx to VPORT
.
• Added a footnote for Absolute Storage Temperature in the table.
• Updated the accuracy values in the Port Current Monitoring table.
• Updated the RSIG_LOW and RSIG_HIGH values in the Detection table.
• Updated the LSB value in the Temperature Monitoring table.
• Updated the values for D11, D12, D15, D16, and D17 in the SPI Timing Diagram Description table.
1.5 Revision 1.2
Revision 1.2 of this document was published in August 2016. The following is a summary of the changes:
• According to PCN155881, qualification of UTAC Thailand assembly for PD6920X. Parts from UTAC
will be identified by different marking that was added.
• Match 802.3af ILIM and IINRUSH levels to IEEE standard levels.
• Match 802.3at ILIM low level to IEEE standard levels.
1.6 Revision 1.1
Revision 1.1 of this document was published in July 2016. The following is a summary of the changes:
• Updated the feature’s list. Changed MSL1 of PD69208 to MSL3.
• Updated ordering information. Changed MSL1 of PD69208 to MSL3.
1.7 Revision 1.0
Revision 1.0 of this document was published in December 2015. This was the first publication.
Overview
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 3
2 Overview
Microsemi's PD69208M Power over Ethernet (PoE) manager IC integrates power, analog, and state-of-
the-art logic into a single 56-pin, plastic QFN package. The device is used in Ethernet switches and
Midspans to allow network devices to share power and data over the same cable. The PD69208M device
is an 8-port, mixed-signal, and high-voltage PoE driver. Together with the PD69200 external MCU, it
performs as a PSE system. Microsemi's PoE controller, PD69200, is a cost-effective, pre-programmed
MCU designed to implement enhanced mode.
PD69208M/PD69200 chip-set supports PoE Powered Device (PD) detection, power-up, and protection
according to IEEE standards, as well as legacy/pre-standard PD detection. It provides PD real-time
protection through the following mechanisms: overload, under-load, over-voltage, over-temperature, and
short-circuit, and enables operation in a standalone mode. It also executes all real-time functions as
specified in IEEE802.3at and IEEE802.3bt Class 3.
PD69208M supports supply voltages between 32 V and 57 V without additional power supply sources. A
system that powers over four pairs can be implemented by combining two ports of PD69208M, enabling
an extra feature for a simple and low-cost, high-power PD device. An on-going monitoring of system
parameters for the host software is available via communication. Internal thermal protection is
implemented in the chip. PD69208M is a low-power dissipation device that uses internal MOSFETs and
internal 100 m sense resistors.
PD69200 features an ESPI bus for all PD69208M. It is developed based on NXP Kinetis_L family,
MKL15Z128VFM4, that is embedded with the ARM Cortex™-M0+ core. It also uses I2C or UART
interface to the host CPU, and is designed to support software field upgradable through the
communication interface.
PD69208M is available in a 56 pin, 8 mm x 8 mm QFN package. PD69200 is available in 32 pin,
5 mm x 5 mm QFN package.
Overview
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 4
2.1 Features
• 8 independent channels
• Complies with IEEE802.3af-2003, IEEE802.3at-2009 (including two-event classification), and
IEEE802.3bt
• Drives 2-pair power ports or 4-pair ports
• Supports pre-standard PD detection
• Single DC voltage input (32 V to 57 V)
• Built in 3.3 V and 5 V regulators
• Input voltage out of range protection
• Wide ambient temperature range: -40 °C to +85 °C
• On-chip Over-temperature thermal protection and monitoring
• Low power dissipation (0.1 sense resistor and 0.2 MOSFET Rdson per channel)
• Includes Reset command pin
• 4 x direct address configuration pins
• Continuous port monitoring and system data
• Configurable load current setting
• Configurable PSE AT/AF/BT-Type3 modes
• Power soft start mechanism
• Voltage monitoring/protection
• Internal power on reset
• Emergency power management supporting four configurable power bank I/Os
• Advance System Power Management algorithm supports up to 96 physical ports
• Can be cascaded to up to 12 PoE devices (96 ports)
• Supports both UART and I2C interfaces to host CPU
• Backwards compatible with Microsemi communication protocol used at prior generations
• LED stream support
• System OK indication
• Software download via I2C or UART
• Detailed port status
• Programmable threshold temperature alarm limit
• Interrupt out pin for system and port events
• Forced port power ON function
• Port power limit setting
• Port matrix and priority
• Automatic PoE device type detection
• MSL3, RoHS compliant
2.2 Applications
• Power over Ethernet (all IEEE compliant 2-pair modes)
• Supports 4-pair and IEEE802.3bt PSE Type 3
• Switches/Routers/Midspans
• Industrial automation
• PoE for LED lighting
Overview
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 5
2.3 Typical PoE Application
The following figure illustrates the typical PoE application of PD69208M and PD69200 devices.
Figure 1 • Typical PoE Application
Note: Fuses per port are not required for use in circuits with total power level of up to 3kW as the PD69208M
designed to fulfill limited power source (LPS) requirements per the latest editions of IEC60950-1 and
EN60950-1.
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Functional Descriptions
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 6
3 Functional Descriptions
The following illustration shows the functional blocks of PD69208M.
Figure 2 • PD69208M Block Diagram
The following sections describe the functional blocks of PD69208M.
3.1 Digital Block Module
The logic main control block includes digital timing mechanisms and state machines synchronizing and
activating PoE functions according to PD69200 control commands, such as:
• Real Time Protection (RTP)
• Start Up Macro (DVDT)
• Load Signature Detection (RES DET)
• Classification Macro (CLASS)
• Voltage and Current Monitoring (VCM)
• ADC Interfacing
• Direct Digital Signals with Analog Block
• SPI Communication Block
•Registers
3.2 PD Detection Generator
Upon request from PD69200 to the main control module, the PD detection generator generates four
different voltage levels to ensure a robust AF/AT/BT PD detection functionality.
3.3 Classification Generator
Upon request from PD69200 to the main control module, state machine applies a regulated class event
and mark event voltage to ports, as required by IEEE standards.
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Functional Descriptions
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 7
3.4 Current Limiter
This circuit continuously monitors the current of powered ports and limits the current to a pre-defined
value set by AF/AT. When the current value exceeds this specific value, the system starts measuring the
elapsed timing. If this interval is greater than a preset threshold, the port is disconnected.
3.5 Main Power MOSFET
The main power switching FET is used to control PoE current into load.
3.6 Analog to Digital Converter
A 10-bit analog to digital converter (ADC) is used to convert analog signals into digital registers for the
logic control module.
3.7 Power on Reset
Power on Reset (PoR) monitors the internal 3.3 V and 5 V DC levels. If this voltage drops below specific
thresholds, a reset signal is generated, and PD69208M is reset.
3.8 Voltage Regulator
The voltage regulator generates 3.3 V and 5 V for internal circuitry. These voltages are derived from
VMAIN supply. To use internal voltage regulator connect:
•V
AUX5 to DRV_VAUX5
•V
AUX3P3 to VAUX3P3_INT
There are three options to reduce PD69208M power dissipation by regulating voltage outside the chip:
• Use an external NPN transistor to regulate the 5 V. In this setup, the configuration of regulators pins
should be as follows:
• DRV_VAUX5 is connected to NPN BASE
•V
AUX5 is connected to NPN EMITTER (Connect Collector to VMAIN)
•V
AUX3P3 is connected to VAUX3P3_INT
• Supply PD69208M with an external 5 V voltage regulator. In this setup, regulators pins configuration
should be as follows:
•V
AUX3P3 is connected to VAUX3P3_INT
• DRV_VAUX5 is not connected (left open)
•V
AUX5 is connected to external 5 V
• Supply PD69208M with an external 3.3 V voltage regulator. In this setup, regulators pins
configuration should be as follows:
•V
AUX5 is connected to DRV_VAUX5
•V
AUX3P3_INT is not connected (left open)
•V
AUX3P3 is connected to external 3.3 V
These options can be implemented simultaneously to reduce PD69208M power dissipation.
3.9 Clock
PD69208M clock (CLK) is an internal 8 MHz clock oscillator.
Functional Descriptions
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 8
3.10 SPI Communication
PD69208M uses SPI communication in SPI slave mode to communicate with PD69200 MCU. Each
PD69208M has an address determined by ADDR0-ADDR3 pins. The PD69200 can support up to 12 ICs.
The actual frequency between PD69200 and PD69208M ICs is 1 MHz.
The following table lists the SPI communication packet structure.
3.10.1 PD69208M SPI Addressing
PD69208M operates in 8-bit address and 16-bit data. It responds to SPI transaction if the first SPI byte
(IC address byte bits[7:1]) complies with the following:
3.10.2 Broadcast
• A broadcast command is intended to instruct all connected PD69208M ICs to perform a specific
operation.
• The broadcast command is a write command with the standard packet structure. In a broadcast read
operation, the read data is not valid and the read operation has no impact.
Table 1 • SPI Communication – Packet Structure
Control byte
Selects PD69208M
According to the
address R/W Bit
Internal Register
Address
Number of words
(only in read access)
Data Written to IC (in
write access)
Read from IC (in
read access)
8 bits R(0)/W(1) 8 bits 8 bits 16 bits
Table 2 • PD69208M SPI Addressing
3 Bits (bit 7:5) 4 Bits (bit 4:1) 1 Bit (bit 0)
000 Address Input Pin Read/Write
Table 3 • PD69208M Broadcast
3 Bits (bit 7:5) 4 Bits (bit 4:1) 1 Bit (bit 0)
001 0000 Write
Functional Descriptions
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 9
Figure 3 • SPI Detailed Timing Diagram
The following table lists the SPI timing diagram description.
Table 4 • SPI Timing Description
Name Min Delay Max Delay Description
D1 910 nS SPI clock period
D2 45 % 55% SPI duty cycle
D3 340 nS SPI_CS setup to SPI clock positive edge (delay after
SPI_CS active signal)
D4 340 nS SPI_CS hold to SPI clock positive edge (delay before
SPI_CS inactive signal)
D5 2 SPI clock cycles Delay between last SCK in eSPI1 frame and first SCK at
adjacent eSPI1 frame
D6 1 SPI clock cycles Between byte 0 (IC address) and byte 1 (address)
D7 1 SPI clock cycles Between byte 1 (address) and byte 2 (data).
D8 1 SPI clock cycles Between byte 2 (MS data byte) and byte 3 (LS data
byte).
D9 340 nS MOSI setup time
D10 340 nS MOSI hold time
D11 700 nS MISO tri-state to valid data from clock positive edge
D12 700 nS MISO valid data to tri-state from SPI_CS positive edge
D13 1 SPI clock cycles SPI_CS width (Delay eSPI1 frame to adjacent eSPI1
frame)
D14 60 nS Filtered glitch width
D15 D3 + D11 + 24 SPI clock
cycles
MISO tri-state from SPI_CS negative edge to valid data
D16 200 nS MISO setup to SCK positive edge
D17 200 nS MISO hold to SCK positive edge
D3
D4
D1 D2
D7
D6 D8
D9
D10
CS_N
SCK
MOSI
MISO
D5
D11
D12
D2
SPI1 frame
8 SCK clock cycles 8 SCK clock cycles 8 SCK clock cycles
D13
Noise Spike
D14
D15
Functional Descriptions
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 10
3.10.3 PD69200 I2C Address Selection
The I2C interface between the host CPU and a specific PD69200 requires setting the PD69200 address.
This is done by applying a specific voltage level to pin #22 (I2C_ADDR_MEAS) as listed in the following
table:
Note: UART communications configuration:
• Bits per second: 19,200 bps
• Data bits: 8
• Parity: None
• Stop bits: 1
• Flow control: None
Note: I2C communication configuration:
• Address: 7 bits
• Clock stretch: host should support
• Transaction: 15 bytes or 1 byte
Table 5 • I2C Address Selection
I2C_ADDR Voltage Level I2C Address (Hexadecimal)
0.00 to 0.21 VDC UART
0.21 to 0.41 VDC 0x4
0.41 to 0.62 VDC 0x8
0.62 to 0.83 VDC 0xC
0.83 to 1.03 VDC 0x10
1.03 to 1.24 VDC 0x14
1.24 to 1.44 VDC 0x18
1.44 to 1.65 VDC 0x1C
1.65 to 1.86 VDC 0x20
1.86 to 2.06 VDC 0x24
2.06 to 2.27 VDC 0x28
2.27 to 2.48 VDC 0x2C
2.48 to 2.68 VDC 0x30
2.68 to 2.89 VDC 0x34
2.89 to 3.09 VDC 0x38
3.09 to 3.30 VDC 0x3C
Electrical Specifications
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 11
4 Electrical Specifications
The following sections describes the electrical characteristics of PD69200 and PD69208M devices.
4.1 PD69200 Electrical Characteristics
In this application, PD69200 consumption is ~20mA.
• Manufacturer: NXP
• Manufacturer part number: MKL15Z128VFM4
• Maximum pull-ups consumption based on PD69200 application is 2mA. See the hardware
application note document: catalog number PD69208_AN_211
4.2 PD69200 Features Description
The following table lists the main features of PD69200.
Table 6 • PD69200 Features Description
Features Description
Supports up to 12 PoE devices -
96 physical ports (48 logical)
Up to 12 PoE devices can be cascaded, fitting into a 96-physical-port PoE
system that uses one PoE controller (PD69200). PD69200 can support up to
48 logical ports. A logical port can be built from 2×Physical ports or
1×Physical port.
Power Management The system supports three power management modes: Class (LLDP), Dynamic
and Static.
Threshold Configuration Over-voltage and under-voltage thresholds can be configured for disconnection
purposes.
High Power Ports
(2 pairs or 4 pairs)
PoE devices can be configured (both hardware and software) to enable higher
current through ports (up to ~627 mA) or double power at the RJ in case of
4 pairs.
Communication Supports both I2C and UART interfaces with the host CPU.
Legacy (reduced capacitance)
Detection
Enables detection and powering of pre-standard devices (PDs) up to 30 µF.
LED Stream Provides a direct SPI interface to an external LED stream circuitry. Enables
designers to implement a simple LED circuit that does not require a software
code. (LED stream clock frequency is 1 MHz).
System OK Indication Provides a digital output pin to host. System validity indication, when the system
OK pin state is low. The output behavior is controlled by software mask register
settings (Mask 0×28). The mask default settings is 0, meaning that this pin
indicates valid software and Vmain is within the range. This pin is active low.
For more information, see the Serial Communication Protocol User Guide
document - Catalog Number: PD69200_UG_COMM_PROT).
System and Port Measurements Measurements of the following parameters: Current (mA),
Power Consumption (W), Vmain (V), Port Voltage (V), and PD Class (0-4).
Detailed Port Status Port statuses are received from PoE managers. Statuses such as port on and
port off due to disconnection or overload.
Interrupt Pin Interrupt out from PoE controller, PD69200, indicating events such as: port on,
port off, port fault, PoE device fault, voltage out of range, and more. For a full list
of interrupt events, see the Serial Communication Protocol User Guide
document - Catalog Number: PD69200_UG_COMM_PROT.
Electrical Specifications
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 12
4.3 PD69208M Electrical Characteristics
Unless otherwise specified under conditions, the Min and Max ratings stated in the following table apply
to the entire specified operating ratings of the device. Typ values stated are either by design or by
production testing at 25 °C ambient.
Port Power Limit Configurable port power limit; when a port exceeds the limit, it is automatically
disconnected.
Port Matrix Control Enables layout designers to connect any physical port to any logical port as
required.
'Power Good' Interrupt from Power
Supply directly to PoE Drivers.
For systems comprising more than a single power supply, when one power
supply fails, a fast port disconnection mechanism is executed to maintain
operation and prevent collapse of other power supplies.
Table 7 • PD69208M Electrical Characteristics
Symbol Parameter Conditions Min Typ Max Units
VMAIN Main Supply Voltage Supports Full
IEEE802.3AF and AT
functionality
32 57 V
VPORT Port Output VMAIN- VPORT_NEGx 057V
VTH POR Threshold Internal or External 3.3 V
supply
8V
IMAIN Main Power Supply
Current @ Operating
Mode.VMAIN = 55 V
14 mA
VAUX5 5 V Output Voltage VAUX5-AGND 4.5 5 5.5 V
VAUX3P3 3.3 V Output Voltage VAUX3P3-AGND 3 3.3 3.6 V
IAUX3P3 3.3 V Output Current for
application use
Without external NPN 5 mA
With external NPN
transistor on VAUX5
30 mA
VAUX3P3_IN 3.3 V Input Voltage VAUX3P3-AGND 3 3.3 3.6 V
DVDD Digital 3.3 V Input Voltage DVDD-DGND 3 3.3 3.6 V
PORTP Power On Reset DVDD
Trip Point
DVDD-DGND 2.575 2.775 2.975 V
PORHYS Power On Reset DVDD
Hysteresis
PORTP-DGND 0.2 0.25 0.3 V
RCH_ON Total Channel Resistance Rds_on + Rsense + Rbonding 0.34
Table 6 • PD69200 Features Description (continued)
Features Description
Electrical Specifications
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 13
4.3.1 Detection
4.3.2 Classification
Table 8 • PD69208M Detection
Symbol Parameter Conditions Min Typ Max Units
VOC Pre-detection Voltage,
Open-circuit Voltage
VMAIN- VPORT_NEGx, open port 7.8 V
VVALID Detection Voltage VMAIN- VPORT_NEGx, for IEEE802.3
compliant signature resistance
(RSIG < 33 K)
9.3 V
ISC Short Circuit Current VMAIN- VPORT_NEGx = 0 V 388 408 µA
RSIG_LOW Minimum Valid Detection
Resistance
15 19 K
RSIG_HIGH Maximum Valid Detection
Resistance
26.5 33 K
Table 9 • PD69208M Classification
Symbol Parameter Conditions Min Typ Max Units
VCLASS Class Event Output Voltage VMAIN- VPORT_NEGx;
0 mA IPORT 50 mA
15.5 18 20.5 V
VMARK Mark Event Output Voltage VMAIN- VPORT_NEGx;
0.1mA IPORT 5 mA
78.510V
ICLASS_LIM Class event
current limitation
VMAIN- VPORT_NEGx = 0 V 51 70 100 mA
IMARK_ LIM Mark event
current limitation
VMAIN- VPORT_NEGx= 0 V 51 70 100 mA
Classification Current
Thresholds
Class 0 0 5 mA
Class 1 8 13 mA
Class 2 16 21 mA
Class 3 25 31 mA
Class 4 35 45 mA
Class Error 51 100 mA
Electrical Specifications
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 14
4.3.3 Port Real Time Protection
4.3.4 Port Current Monitoring
Table 10 • PD69208M Port Real Time Protection
Symbol Parameter Conditions Min Typ Max Units
TRISE Turn on rise time From 10% to 90% of the voltage
difference at the VPORT_NEGx in
POWER_ON state from the
beginning of POWER_UP
15 µS
IINRUSH Output current in
POWER_UP state
CLOAD 180 µF1
1. Can be overridden by communication command.
400 425 450 mA
TINRUSH Inrush Time 65 mS
IPORT Output Operating Current 802.3af 10 360 mA
802.3at 10 627 mA
802.3bt class 5 10 560 mA
802.3bt class 6 10 692 mA
ICUT Overload Current 802.3af 375 mA
802.3at 645 mA
802.3bt class 5 589 mA
802.3bt class 6 709 mA
TCUT Overload Time Limit 62 64 66 mS
ILIM Port Current Limit 802.3af 400 425 450 mA
802.3bt class 1-3 670 720 770 mA
802.3at, 802.3bt class 4-6 790 850 892
TLIM Port Current Limit Time VMAIN- VPORT_NEGx< 30 V 1 2 3 mS
PPWR Port power accuracy > 90 W 2 %
IUDL DC Disconnect Under-load
Current
2 Pairs 6 7.5 9 mA
4 Pairs (for each pairset) 2 2.5 3 mA
TMPDO PD Maintain Power
Signature Dropout Time
Limit
322 324 326 mS
TMPS PD Maintain Power
Signature Time For Validity
802.3bt PSE Type 1, 2 46 48 50 mS
802.3bt PSE Type 3, 4 3 4 5 mS
TOFF Turn Off Time From VMAIN to 2.8V 500 mS
Table 11 • PD69208M Port Current Monitoring
Parameter Conditions Typ Max Units
Resolution Reported as 14 Bits 10 Bits
LSB 122.07 µA
Measurement Period 16 mS
Electrical Specifications
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 15
4.3.5 Port Voltage Monitoring
4.3.6 Main Voltage Monitoring
4.3.7 Temperature Monitoring
Accuracy 50 mA < IPORT < 150 mA 9 %
150 mA < IPORT < 350 mA 4.5 %
350 mA < IPORT < 600 mA 3.5 %
IPORT > 600 mA 3.0 %
Table 12 • PD69208M Port Voltage Monitoring
Parameter Typ Max Units
Resolution 10 Bits
LSB 58.6 mV
Measurement Period 3 mS
Accuracy 3.3 %
Table 13 • PD69208M Main Voltage Monitoring
Parameter Conditions Typ Max Units
Resolution 10 Bits
LSB 58.6 mV
Measurement Period 3 mS
Accuracy 42 V < VMAIN < 50 V 2 %
50 V < VMAIN < 57 V 1.5 %
50 V < VMAIN < 57 V1
1. 0-70 °C
0.6 %
Table 14 • PD69208M Temperature Monitoring
Parameter Conditions Min Typ Max Units
Resolution 8 Bits
LSB Temperature = (DATA x 1.9384) - 273 1.9384 °C
Measurement Period 3 mS
Accuracy -3 3 °C
Table 11 • PD69208M Port Current Monitoring (continued)
Parameter Conditions Typ Max Units
Electrical Specifications
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 16
4.3.8 Digital Interface
4.3.9 Immunity
Table 15 • PD69208M Digital Interface
Symbol Parameter Conditions Min Typ Max Units
VIH Input Logic High Voltage RESET_N, MOSI, MISO, SCK,
CS_N, PGD[0..3], ADDR[0..3]
2.2 V
VIL Input Logic Low Voltage RESET_N, MOSI, MISO, SCK,
CS_N, PGD[0..3], ADDR[0..3]
0.8 V
Hyst Input Logic Hysteresis
Voltage
RESET_N, MOSI, MISO, SCK,
CS_N, PGD[0..3], ADDR[0..3]
0.4 0.6 0.8 V
IIH Input Logic High Current RESET_N, MOSI, MISO, SCK,
CS_N, PGD[0..3], ADDR[0..3]
-10 10 µA
IIL Input Logic Low Current RESET_N, MOSI, MISO, SCK,
CS_N, PGD[0..3], ADDR[0..3]
-10 10 µA
VOH Output Logic High Voltage RESET_N, MOSI, MISO, SCK,
CS_N, PGD[0..3], ADDR[0..3]
IOH = -1mA
2.4 V
VOL Output Logic Low Voltage RESET_N, MOSI, MISO, SCK,
CS_N, PGD[0..3], ADDR[0..3]
IOH = 1mA
0.4 V
Table 16 • PD69208M Immunity
Symbol Parameter Conditions Min Typ Max Units
ESD ESD rating HBM1
1. ESD HBM complies with JESD22 Class 2 standard.
ESD rating CDM2
2. ESD CDM complies with JESD22 Class 1 standard.
Surge Lightning surge3
3. System level common mode 10/700 µS according to IEC61000-4-5.
EN61000 4-5 -1 1 KV
Electrical Specifications
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 17
4.4 PD69208M Absolute Maximum Ratings
PoE performance is not guaranteed when exceeding the recommended rating. Exposure to any stress in
the range between the recommended rating, as listed in the following table, and the absolute maximum
rating should be limited to a short time. Exceeding these ratings may impact long-term operating
reliability.
Note: DRV_VAUX5 and IREF are output pins and should not apply voltage or current. DRV_VAUX5 can be left
open when not used.
Table 17 • Absolute Maximum Ratings
Parameters Min Max Units
Supply Input Voltage (VMAIN)1, 2
1. Power Sequence Requirement: Vmain > VAUX5 > VAUX3P3= TRIM, DVDD.
2. PD69208M EPAD is connected by copper plane on PCB to AGND. AGND is ground for IC.
-0.3 72 V
PORT_NEG[0.7] pins -0.3 VMAIN+0.5 V
VAUX5 -0.3 6 V
VAUX3P3, DVDD -0.3 4 V
Digital pins: MISO, MOSI, SCK, CS_N,
ADDR[3:0], PGD[3:0], RESET_N, TRIM
-0.3 DVDD + 0.3 and < 4.0 V
Junction Temperature 150 °C
Lead Soldering Temperature (40s, reflow) 260 °C
Storage Temperature -65 150 °C
Pin Descriptions
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 18
5 Pin Descriptions
The PD69200 device has 32 pins and PD69208M device has 56 pins, which are described in this
section.
5.1 Pin Configuration and Pinout
The following figures represent the top- and bottom-view of PD69200 and PD69208M devices.
Figure 4 • PD69200 Pin Diagram
Note: The marking position of PD69200 may change subject to NXP practice.
Note: For definitions about markings in the PD69200 pinout diagram, see the ordering information table
(Table 30, page 41).
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Pin Descriptions
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 19
Figure 5 • PD69208M Pin Diagram
Note: For definitions about markings in the PD69208M pinout diagram, see the ordering information table
(Table 30, page 41).
5.2 Pin Descriptions
The following sections describe the functional pin descriptions of PD69200 and PD69208M devices.
5.2.1 PD69200
The following table lists the functional pin descriptions of the PD69200 device.
Table 18 • PD69200 Pin Description
Number Designator Type Description
EPAD Thermal Isolated Thermal PAD, recommended to tie to GND.
1UART1_TX
1OUT Reserved UART.
2UART1_RX
1IN Reserved UART.
3 ESPI_xCS OUT ESPI Bus to PoE Manager. SPI chip select (Active Low). CS is
asserted during all SPI frame.
4 ESPI_SCK OUT ESPI Bus to PoE Manager. SPI clock output to PD6920x, and
LED stream clock output, set to 1 MHz.
5 ESPI_MOSI OUT SPI packets are transmitted on this line.
6 ESPI_MISO IN ESPI Bus to PoE Manager. SPI Master In Slave Out. SPI
packets are received on this line.
7 VDDA Supply Main Supply 3.3 V.
8 VSSA GND Analog ground.
9 Analog_IN Analog_IN Analog input. Should be connected to 3.3 V.
10 SWD_CLK DEBUG Serial Debug Data Bus Clock.
Top View - 8×8 QFN – 56L Bottom View - 8×8 QFN – 56L
25
26
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
52
46
47
48
9
10
50
51
12
24
49
23
54
55
53
11
42
41
40
39
38
37
36
35
34
33
31
32
27
28 43
44
45
13
14
30
29
VPORT_NEG3
TST
VPORT_NEG2
VPORT_NEG2
VPORT_NEG0
VPORT_NEG0
VPORT_NEG1
VPORT_NEG1
VPORT_NEG3
VPORT_NEG4
DGND
VPORT_NEG5
VPORT_NEG5
VPORT_NEG7
VPORT_NEG7
VPORT_NEG6
VPORT_NEG6
VPORT_NEG4
TRIM
IREF
DRV_VAUX5
VAUX5
VAUX3P3_INT
VAUX3P3
AGND
VMAIN
PGD1
AGND
AGND
PGD3
CS_N
PGD0
MISO
MOSI
SCK
DVDD
RESET_N
ADDR3
ADDR1
ADDR0
ADDR2
PGD2
56
25
26
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
52
46
47
48
9
10
50
51
12
24
49
23
54
55
53
11
42
41
40
39
38
37
36
35
34
33
31
32
27
28
43
44
45
13
14
30
29
56
N.C
N.C
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
N.C
PD69208M
F R e4
DATE CODE
EPAD
Pin Descriptions
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 20
11 UART0_RX1IN UART receive from host. 15 byte protocol commands are
received on this line. The baud rate is set to 19,200 bps.
For more information, see the Serial Communication Protocol
User Guide document - Catalog Number:
PD69200_UG_COMM_PROT.
12 UART0_TX1OUT UART transmit to host. 15 byte protocol reply/telemetry are
transmitted on this line. The baud rate is set to 19,200 bps.
For more information, see the Serial Communication Protocol
User Guide document - Catalog Number:
PD69200_UG_COMM_PROT.
13 SWD_DIO DEBUG Serial Debug Data Bus.
14 Reserved (NMI_b) IRQ_Input Spare, an external pull-up must be connected.
15 VDD Supply Main Supply 3.3 V.
16 VSS GND Digital ground.
17 EXTAL0 (OSC_IN)2Oscillator Oscillator input - Reserved.
18 XTAL0 (OSC_OUT)2Oscillator Oscillator output - Reserved.
19 xRESET(3,4) IN/OUT Host Reset input (Active Low). The shortest reset pulse from
the host that is required for the PD69200 application is
150 µSec. PD69200 can generate self-reset. In this case, the
xRESET pin is driven low by the PD69200 for about
100 µSec. It is recommended to connect this pin to a host open
drain output with 10 K pull-up. An 47 nF filter capacitor should
be connected between this pin to GND, close to the PD69200
device. If this pin is connected to a push/pull driver, a serial
resistor of 1.5 K must be connected instead of the pull-up.
The required shortest reset pulse in this case is 300 µSec.
For more information about this pin connectivity, see the
Hardware Application Note, Catalog Number:
PD69208_AN_211.
20 I2C0_SCL4 IN/OUT I2C clock from the host master. Speed is limited to 400 KHz and
clock stretching functionality must be implemented in the host
master. If PD69200 is busy, it holds the clock line.
21 I2C0_SDA4IN/OUT I2C bidirectional data. 15 byte protocol messages are
transmitted on this line.
For more information, see the Serial Communication Protocol
User Guide document - Catalog Number:
PD69200_UG_COMM_PROT.
22 I2C_ADDR_MEAS Analog_IN I2C address of PD69200. Analog input to determine I2C
address or UART operation. See I2C address selection in
Tab le 5, page 10.
23 Analog_IN Analog_IN Reserved analog input. connect to GND.
24 xI2C_MESSAGE_READY3OUT I2C message ready for read by the host. PD69200 asserts this
line low when it has an answer to the host. Therefore, the host
can poll this line and initiate I2C read cycle only when the
message is ready. This pin is active low.
After the host reads the data from PD69200, this pin is
asserted to high.
Table 18 • PD69200 Pin Description (continued)
Number Designator Type Description
Pin Descriptions
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 21
Note: All I/Os in this application can sink or source 3 mA maximum.
5.2.2 PD69208M
The following table lists the functional pin descriptions of PD69208M devices
25 xINT_OUT(3, 4) OUT Interrupt output indication. This line is asserted low when a
pre-configured event is in progress. The host configures the
event that should generate an interrupt through 15 bytes
protocol. When this event occurs, the xINT_OUT pin is
asserted. This pin is active low.
26 xLED_CS3OUT Chip select signal for LED stream. This pin is active low.
27 xLED_LATCH3OUT Latch signal for LED stream. This pin is active low.
28 xLED_OE3OUT Output enable signal for LED stream. This pin is active low.
29 Reserved IN Reserved for MPRPD counter for future support. If not used,
connect to VDD.
30 FAN_CONTROL OUT Optional. Fan control operates a fan, when the PD69208M
device temperature is above the temperature alarm threshold.
This pin is active high.
31 xDISABLE_PORTS3IN Disable all PoE ports. When this input is asserted low, the
PD69200 device shuts down all of the PoE ports in the system.
This pin contains software filter of 480 mSec to reject noise and
false disable scenarios.
32 xSys_OK/LED System OK3OUT System validity indication. When the system is in OK state, the
pin state is low. The behavior of this output is controlled by
software mask register settings (Mask 0x28). The mask default
settings is 0, meaning that this pin indicates valid software, and
Vmain is in range. This pin is active low.
For more information, see the Serial Communication Protocol
User Guide document - Catalog Number:
PD69200_UG_COMM_PROT.
1. Weak pull-up is recommended. See the PD69208_AN_211 document.
2. The oscillator pins are reserved and unused. The MCU uses internal clock source set to 47.972MHz +/- 1.5% (max).
3. The initial x indicates that the pin is active low.
4. Open drain output requires an external pull-up. See the Hardware Application Note: PD69208_AN_211 document.
Table 19 • PD69208M Pin Description
Number Designator Type Description
EPAD Exposed PAD. Connect to analog ground. A decent ground plane
should be deployed around this pin as required.
See the PD69208M Layout Design Guidelines section in the
Hardware Application Note, Catalog Number: PD69208M_AN_211.
1 N.C N/A Not connected; do not connect externally (leave floating).
2 TST Digital Input Test pin for production use only. Keep connected to DGND.
3 VPORT_NEG0 Analog I/O Negative port 0 output.
4 VPORT_NEG0 Analog I/O Negative port 0 output.
5 RESERVED N/A Reserved pin. Do not connect externally.
6 VPORT_NEG1 Analog I/O Negative port1 output.
Table 18 • PD69200 Pin Description (continued)
Number Designator Type Description
Pin Descriptions
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 22
7 VPORT_NEG1 Analog I/O Negative port1 output.
8 RESERVED N/A Reserved pin. Do not connect externally.
9 VPORT_NEG2 Analog I/O Negative port 2 output.
10 VPORT_NEG2 Analog I/O Negative port 2 output.
11 RESERVED N/A Reserved pin. Do not connect externally.
12 VPORT_NEG3 Analog I/O Negative port 3 output.
13 VPORT_NEG3 Analog I/O Negative port 3 output.
14 RESERVED N/A Reserved pin. Do not connect externally.
15 AGND Power Analog ground.
16 RESERVED N/A Reserved pin. Do not connect externally.
17 VMAIN Power Main high-voltage supply voltage. A low ESR 1 µF (or higher)
bypass capacitor, connected to AGND, should be placed as close as
possible to this pin through low-resistance traces.
18 N.C N/A Not connected. Do not connect externally.
19 DRV_VAUX5 Power Driven outputs for 5 V external regulation; if internal regulation is
used, connect to pin 20. If an external NPN is used to regulate the
voltage, connect this pin to Base.
If an NPN is used, a 4.7 F capacitor should be connected between
this pin and AGND.
20 VAUX5 Power Regulated 5 V output voltage source; A 4.7 F or higher filtering
capacitor should be connected between this pin and AGND. If an
external NPN is used to regulate the voltage, connect this pin to the
emitter. Or the collector should be connected to Vmain.
21 AGND Power Analog ground.
22 VAUX3P3 Power Regulated 3.3 V output voltage source. A 4.7 F or higher filtering
capacitor should be connected between this pin and AGND.When
an external 3.3 V regulator is used, connect it to this pin to supply
the chip.
23 VAUX3P3_INT Power Connected to VAUX3P3 (pin 22) if internal 3.3 V regulator is used.
Leave unconnected (Floating) if external 3.3 V regulator is used.
24 IREF Analog Input Reference resistor pin. Connect a 28.7 k 1% resistor to AGND.
25 TRIM Test Input Test Input pin; Keep connected to VAUX3P3.
26 RESERVED N/A Reserved pin. Do not connect externally.
27 RESERVED N/A Reserved pin. Do not connect externally.
28 AGND Power Analog ground.
29 RESERVED N/A Reserved pin. Do not connect externally.
30 VPORT_NEG4 Analog I/O Negative port 4 output.
31 VPORT_NEG4 Analog I/O Negative port 4 output.
32 RESERVED N/A Reserved pin. Do not connect externally.
33 VPORT_NEG5 Analog I/O Negative port 5 output.
34 VPORT_NEG5 Analog I/O Negative port 5 output.
35 RESERVED N/A Reserved pin. Do not connect externally.
Table 19 • PD69208M Pin Description (continued)
Number Designator Type Description
Pin Descriptions
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 23
36 VPORT_NEG6 Analog I/O Negative port 6 output.
37 VPORT_NEG6 Analog I/O Negative port 6 output.
38 RESERVED N/A Reserved pin. Do not connect externally.
39 VPORT_NEG7 Analog I/O Negative port 7 output.
40 VPORT_NEG7 Analog I/O Negative port 7 output.
41 PGD1 Digital I/O Power good input from system power supply.
42 DGND Power Digital ground.
43 DVDD Power In Regulated 3.3 V for digital circuitry. Connect voltage from pin
VAUX3P3 or from external power supply source if used. A 1 F or
higher filtering capacitor should be connected between this pin and
DGND.
44 RESET_N Digital Input Reset input - active low (0 = reset). An external 10 K pull-up resistor
should be connected between this pin and DVDD.
45 N.C N/A Not connected. Do not connect externally.
46 PGD2 Digital Input Power good input from system power supply.
47 PGD3 Digital Input Power good input from system power supply.
48 ADDR0 Digital Input SPI address bit 0 to set chip address.
49 ADDR1 Digital Input SPI address bit 1 to set chip address.
50 ADDR2 Digital Input SPI address bit 2 to set chip address.
51 ADDR3 Digital Input SPI address bit 3 to set chip address.
52 CS_N Digital Input SPI bus and chip select.
53 SCK Digital Input SPI bus and serial clock input.
54 MOSI Digital Input SPI bus and Master Data Out/slave In.
55 MISO Digital Output SPI bus and Master Data In/slave Out.
56 PGD0 Digital Input Power good input from system power supply.
Table 19 • PD69208M Pin Description (continued)
Number Designator Type Description
Pin Descriptions
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 24
5.3 PD69200 Recommended PCB Layout for 32 Pin QFN
5mm x 5mm
The following figures illustrate the PCB layout pattern for PD69200. Units are in mm.
Figure 6 • PD69200 Top-Layer Copper PCB Layout
Figure 7 • PD69200 Top-Layer Solder Paste and Vias PCB Layout for Thermal Pad Array
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Pin Descriptions
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 25
5.4 PD69208M Recommended PCB Layout for 56-Pin QFN
8mm x 8mm
The following figures illustrate the PCB layout pattern for PD69208M. Units are in mm.
Figure 8 • Top-Copper Layer
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Pin Descriptions
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 26
Figure 9 • Top-Solder Paste Layer
8QLWVLQ0LOOLPHWHUPP
Pin Descriptions
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 27
Figure 10 • Top-Layer Mask
Figure 11 • BOT and Internal Layers Copper Plane
8QLWVLQ0LOOLPHWHUPP
Pin Descriptions
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 28
Figure 12 • Top-Layer Pin Geometry
Note: The CM has latitude to modify the solder paste stencil for manufacturability reasons. The solder paste
stencil shall cover 65% to 80% of the thermal pad and must not allow solder to be applied to the thermal
vias under the QFN package using any method they deem appropriate. Any design should be subject to
system validation and qualification prior to commitment to mass production of field deployment.
Use a 5 mil stencil.
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Package Information
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 29
6 Package Information
This chapter describes package drawings of PD69200 and PD69208Mdevices.
6.1 PD69200 Package Outline Drawing
The following figure illustrates the package drawing of PD69200 device.
Figure 13 • PD69200 Package Outline Drawing (32 Pin QFN 5 mm x 5 mm)
The following table lists the dimensions and measurements of the PD69200 package.
Note: Dimensions do not include protrusions; they should not exceed 0.155 mm (.006) on any side. Lead
dimension should not include solder coverage. Dimensions are in millimeters and inches for reference.
Table 20 • PD69200 Package Outline Dimensions and Measurements
Dimension Millimeters Inches
MinMaxMinMax
A 0.80 1.00 0.031 0.039
A1 0.00 0.05 0 0.002
A3 0.20 REF 0.008 REF
K 0.20 MIN 0.008 MIN
e 0.50 BSC 0.02 BSC
L 0.30 0.50 0.012 0.02
b 0.18 0.30 0.007 0.012
D2 3.50 3.70 0.138 0.147
E2 3.50 3.70 0.138 0.147
D 5.00 BSC 0.197 BSC
E 5.00 BSC 0.197 BSC
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Package Information
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 30
6.2 PD69208M Package Outline Drawing
The following figure illustrates the package drawing of the PD69208Mpackage.
Figure 14 • PD69208M Package Drawing (56 Pin QFN 8 mm x 8 mm)
The following table lists the dimensions and measurements of the PD69208Mpackage.
Note: Dimensions do not include protrusions; they should not exceed 0.155mm (.006) on any side. Lead
dimension should not include solder coverage. Dimensions are in millimeters and inches for reference.
Table 21 • PD69208MPackage Outline Dimensions and Measurements
Dimension Millimeters Inches
Min Max Min Max
A 0.80 1.00 0.031 0.039
A1 0.00 0.05 0 0.002
A3 0.20 REF 0.008 REF
K 0.20 MIN 0.008 MIN
e 0.50 BSC 0.02 BSC
L 0.30 0.50 0.012 0.02
b 0.18 0.30 0.007 0.012
D2 6.50 6.75 0.256 0.267
E2 6.50 6.75 0.256 0.267
D 8.00 BSC 0.315 BSC
E 8.00 BSC 0.315 BSC
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Package Information
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 31
6.3 PD69208M Thermal Specifications
The following tables list the thermal specifications of PD69208M and PD69200.
Note: All parameters are as per JEDEC JESD-51.
6.4 Recommended Solder Reflow Information
• RoHS 6/6
• Pb-free 100% Matte Tin Finish
• Package Peak Temperature for Solder Reflow(40 seconds maximum exposure)—260 °C
(+0 °C, -5 °C)
Table 22 • PD69208M Thermal Specifications
Thermal Resistance Typ Units Notes
JA 19.0 °C/W Junction-to-ambient thermal
resistance.
JT 0.05 °C/W Junction-to-top thermal
characterization parameter. A thermal
metric derived from the difference in
junction temperature (TJ) and
package top temperature (TT) divided
by total heating power (PH).
JC (top) 4.9 °C/W Junction-to-case thermal resistance
with heat flow through package top.
JB 2.2 °C/W Junction-to-board thermal resistance.
Table 23 • PD69200 Thermal Specifications
Thermal Resistance Typ Units Notes
JA 33 °C/W Junction-to-ambient thermal
resistance.
JT 8 °C/W Junction-to-top thermal
characterization parameter. A thermal
metric derived from the difference in
junction temperature (TJ) and
package top temperature (TT) divided
by total heating power (PH).
JC (top) 1.8 °C/W Junction-to-case thermal resistance
with heat flow through package top.
JB 12 °C/W Junction-to-board thermal resistance.
Table 24 • Classification Reflow Profiles
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Average Ramp-up Rate (TSmax to Tp) 3 °C/second max 3 °C/second max
Preheat
Temperature Min (TSmin)
Temperature Max (TSmax)
Time (tsmin to tsmax)
100 °C
150 °C
60 - 120 seconds
150 °C
200 °C
60 - 180 seconds
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Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 32
Figure 15 • Classification Reflow Profiles
Note: Exceeding the ratings that are mentioned in Table 25, page 32 may cause damage to the device.
Time Maintained
Temperature (TL)
Time (tL)
183 °C
60 - 150 seconds
217 °C
60 - 150 seconds
Peak Classification Temperature (TP) 210 - 235 °C 240 - 255 °C
Time within 5 °C of actual peak
temperature (tp)
10 - 30 seconds 20 - 40 seconds
Ramp-Down Rate 6 °C/second max 6 °C/second max
Time 25 °C to Peak Temperature 6 minutes max 8 minutes max
Table 25 • Pb-Free Process – Package Classification Reflow Temperatures
Package Thickness Volume mm3 < 350
Volume mm3
350 – 2000 Volume mm3 > 2000
< 1.6 mm1
1. Tolerance: The device manufacturer or supplier should assure process compatibility up to and
including the stated classification temperature, meaning that the Peak reflow temperature is +0
°C. For example, 260 °C to 0 °C, at the rated MSL value.
260 +0 °C 260 +0 °C 260 +0 °C
1.6 mm - 2.5 mm1260 +0 °C 250 +0 °C 245 +0 °C
2.5 mm1250 +0 °C 245 +0 °C 245 +0 °C
Table 24 • Classification Reflow Profiles
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Package Information
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 33
6.5 Tape and Reel—Packaging Information
The following sections provide the tape and reel information.
6.5.1 PD69200 Tape and Reel Specification
Figure 16 • PD69200 Tape Specification
The following table lists the PD69200 tape mechanical data.
Table 26 • PD69200 Tape Mechanical Data
Dimensions Value (mm) Value (inches)
D 1.50 + 0.1/0 0.059 + 0.004/0
E 1.75 ±0.1 0.069 ±0.004
P0 4.00 ±0.1 0.157 ±0.004
T (max) 0.3 ±0.05 0.0118 ±0.003
D1 1.5 0.059
F 5.5 ±0.1 0.216 ±0.003
K (max) 1.6 ±0.1 0.0.63 ±0.004
P2 2.00 ±0.1 0.079 ±0.004
R30 1.181
W 12.00 ±0.3 0.472 ±0.012
P1 8.00 ±0.1 0.31 ±0.004
K0 1.1 0.043
A0 5.30 0.208
B0 5.30 0.208
Package Information
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 34
Figure 17 • PD69200 Reel Specification
The following table lists the PD69200 reel mechanical data.
6.5.2 PD69208M Tape and Reel Specification
Figure 18 • PD69208M Tape and Reel Pin-1 Orientation
Table 27 • PD69200 Reel Mechanical Data
Dimensions Value (mm) Value (inches)
Tape size 12 +0.3 0.472 +0.012
W1 12.4 0.488
W2 18.4 0.724
W3 15.4 0.606
Package Information
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 35
Figure 19 • PD69208M Tape Specifications
The following table lists the PD69208M tape mechanical data.
Figure 20 • PD69208M Reel Specifications
Table 28 • PD69208M Tape Mechanical Data
Dimension Value (mm)
A0 8.35 ±0.10
B0 8.35 ±0.10
K0 1.40 ±0.10
K1 N/A
Pitch 12.00 ±0.10
Width 16.00 ±0.30
Package Information
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 36
6.6 Reference Documents
• IEEE Std 802.3-2018 Clause 33 Power over Ethernet over 2-Pair and Clause 145 Power over
Ethernet
• Microsemi, Serial communication protocol user guide, Catalog Number:
PD69200_UG_COMM_PROT
• Microsemi, Designing 48-port Enhanced PoE System (802.3af/802.3at Compliant) application note,
Catalog Number: PD69208_AN_211
• Microsemi, Software Download Algorithm technical note (TN-140), Catalog Number: 06-0024-081
• Microsemi, PoE LED stream technical note, Catalog Number: PD69100_TN_201
• NXP, Kinetis_L MKL15Z128VFM4 datasheet
• NXP package drawings 98ASA00473D
Table 29 • PD69208M Reel Mechanical Data
Dimensions Value (mm) Value (inch)
Tape size 16.00 ±0.3 0.630 ±0.012
A max. 330 13"
B max 1.5 0.059
C 13.0 ±0.20 0.512 ±0.008
D min. 20.2 0.795
N min. 50 1.968
G 16.4+2.0/-0.0 0.645+ 0.079/-0.0
T max 29 1.142
BASE QUANTITY 2000 pcs.
Application Information
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 37
7 Application Information
PD69208M/PD69200 PSE Chipset performs IEEE802.3af (Type 1), IEEE802.3at (Type 2), and
IEEE802.3bt (Type 3) PSE functionalities in addition to pre-standard and legacy (capacitor) detection.
Moreover, it includes additional protections such as short circuit and dV/dT protection upon startup.
Note: IEEE802.3bt functionality will be enabled by a firmware upgrade.
7.1 PD Detection
The PD detection feature detects a valid IEEE802.3af, IEEE802.3at or IEEE802.3bt. The PD detection is
done based on four different voltage levels generated over PD (the load) as illustrated in Figure 22,
page 38.
7.2 Legacy (Reduced Capacitor) Detection
When legacy detection is enabled, the PD detection mechanism detects and powers up legacy and
pre-standard PDs as well as IEEE802.3af, IEEE802.3at and IEEE802.3bt standard compliant PDs
(Classes 0 - 6).
7.3 Classification
The classification process takes place immediately after PD detection is successfully completed. The
goal of the classification process is to detect PD class as specified in IEEE802.3 standards.
In IEEE802.3af mode, the classification mechanism is based on a single voltage level (single event). In
IEEE802.3at and IEEE802.3bt modes, the classification mechanism is based on two voltage levels
(multiple events) as defined in IEEE802.3-2015 Clause 33 and IEEE802.3bt.
Figure 21 • 4-Pair PoE System Diagram
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Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 38
Figure 22 • Typical IEEE802.3at Port PoE Voltage Diagram
7.4 Port Start Up
Upon a successful detection and classification process, power is applied to the load via a controlled start
up mechanism.
During this period, inrush current is limited to 425 mA for a typical duration of 65 mS, which allows PD
load to charge and allows steady state of power condition.
7.5 Over-Load Detection and Port Shut Down
After power up, PD69208M automatically initializes its internal protection mechanisms. These
mechanisms are used to monitor and disconnect power from the PD when extreme conditions occur, as
specified in the IEEE802.3 standards. These conditions include over-current or short ports terminals
scenarios.
7.6 Disconnect Detection
PD69208M supports the DC disconnect function as per IEEE802.3 standards. This mechanism
continuously monitors load current and disconnects power according to IUDL, TMPDO, and TMPS
parameters as specified in Table 10, page 14.
7.7 IC Thermal Monitoring
PD69208M contain a thermal sensor that is sampled by the PD69200 for every 20 mS so that the
PD69208M die temperature is monitored at all times. If the die exceeds the temperature limit (150 °C),
the system ports are disconnected to protect the PD69208M ICs.
A temperature alarm threshold can be set by PD69200 controller to send interrupt indication by the
xINT_OUT pin before ports are disconnected. The temperature can be read and monitored by the host
as well, if required.
7.8 Over-Temperature Protection
In addition to the die thermal sensor, there are thermal sensors on each MOSFET that continuously
monitors each port main MOSFETs junction temperature, and shuts down the port load power when the
temperature exceeds 200 °C.
7.9 VMAIN Out of Range Protection
The system automatically disconnects ports power when VMAIN exceeds the pre-configured over-voltage
and under-voltage thresholds.
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Application Information
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 39
7.10 2-Pair and 4-Pair Ports
Operation modes include the following:
• POE Type 1/2 class 0-4 (up to 30 W)
• POE Type 3 class 0-4 2-Pair and class 5-6 4-Pair (up to 60 W)
Note: For more information about 4-Pair operation modes and power configuration, see
Microsemi_PoE_4_Pair_Behavior_PD6920x_PSE_Application_Note_160159.
7.11 Power Management
System supports three power management modes:
• Class (LLDP and CDP)
• Dynamic
•Static
7.12 Port Power Limit
Port power limit (PPL) is used to configure port power limit. When a port exceeds the power limit, it gets
disconnected automatically.
7.13 Reset Pin
xRESET pin is PD69200 digital host reset input (Active Low). The shortest pulse that is guaranteed to be
recognized is 100 nSec. PD69200 can generate self-reset. The xRESET pin is driven low by PD69200
for at least 128 bus clock cycles until the flash initialization has completed. It is recommended to connect
this pin to a host open drain output with pull-up in a range of 4.7 K to 10 K. If this pin is connected to a
push/pull driver, a serial resistor of 4.7 K must be connected instead of pull-up. Avoid resetting the
PD69208M IC directly by the RESET_N pin. The PD69200 controls the PD69208M ICs if system reset is
needed.
For more information about this pin connectivity, see the hardware application note, Catalog Number:
PD69208_AN_211.
7.14 System OK Indication
Digital output pin to host is used as a system validity indication. When system is OK pin state is low. The
behavior of this output is controlled by software mask register settings (Mask 0×28). The mask default
settings is 0, meaning that this pin indicates valid software and Vmain is in range. This pin is active low.
For more information, see the Serial Communication Protocol User Guide document - Catalog Number:
PD69200_UG_COMM_PROT.
7.15 Interrupt Pin
Interrupt out from PoE controller, indicating events such as: port on, port off, port fault, PoE device fault,
voltage out of range, and more. For a full list of interrupt events, see the Serial Communication Protocol
User Guide document - Catalog Number: PD69200_UG_COMM_PROT. This pin is active low.
7.16 Port Matrix Control
Port matrix control enables layout designers to ascribe each physical port in the system to a logical port if
required.
7.17 Power Good Interrupt
Interrupt from power supply directly to PD69208M manager. For systems comprising more than a single
power supply, in case one power supply fails, a port shutdown mechanism is executed to maintain
operation and prevent collapse of other power supplies.
When function is used, PGD0, PGD1, PGD2, and PGD3 should be connected to main power supplies
status indication pin. Any change of at least 1 µS on these lines triggers a pre-defined disconnection
Application Information
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 40
matrix. This matrix is defined by PD69200 system power parameters. The port shutdown function reacts
within 2 µS to any power good event.
7.18 LED Stream
The direct SPI interface to an external LED stream circuitry that can drive LEDs directly without the host
intervention. It enables designers to implement a simple LED circuit that does not require a software
code. The LED stream clock frequency is 1 MHz.
For more information, see the TN-218, catalog number PD69200_TN_218.
7.19 Power Sequencing
Figure 23 • Power Sequencing
When using external Vaux5 or Vaux3p3
•Td1: V
main at 5 V to Vaux5 > 0 µS
•Td2: V
aux5 to Vaux3p3 > 0 µS
•Td3: V
aux3p3 to Vaux5 > 0 µS
•Td4: Vaux5 to Vmain at 5 V > 0 µS
•DV
DD = Vaux3p3
Note: See the Application Note AN211 - Designing a PD69208 48-port PoE System 802.3af/802.3at compliant.
For proper operations, you need to ensure that Vmain is always in the highest voltage connected to the
IC. With an external DC-DC converter, the maximum 3.3 V slew rate is 100 mS.
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Ordering Information
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 41
8 Ordering Information
The following table the part ordering information for PD69200 and PD69208M devices.
Table 30 • Ordering Information
The Firmware Release Notes has all the required information about how to specify the choice of VVVV
and SS. You can find the Firmware Release Notes in the Microchip Software Libraries, and register
yourself to a My Microchip account to have access to the release notes.
Note: The package meets RoHS, Pb-free, and MSL3 of the European Council to minimize the environmental
impact of electrical equipment.
Note: Initial burning of controller's firmware is performed in factory. Firmware upgrades can be performed by
users using communication interface. For more information, see TN-140, Catalog Number: 06-0024-081.
Part Number Package
Packaging
Type Temperature Part Marking Tray Marking
PD69200D1-VVVV2SS3
1. D stands for the detection method set as: C: Detection Method = IEEE802.3 and pre-standard;
R: Detection Method = IEEE802.3.
2. VVVV is firmware revision
3. SS stands for firmware parameters option
Plastic QFN
5mm × 5mm
(32 lead)
Tray –40 °C to 85 °C Microsemi Logo
NXP Logo
69200
M15M7V4
XXXXX5
YYYYY6
4. Short part number
5. Mask set
6. Date code
PD69200D-
VVVVSS
PD-OOOOG3bb7
YYWW
7. MKTG Product Type (Detection = R: Resistor/D = C: Resistor/Legacy)/Version/SW Parameters/Operation P/N.
PD69200D-VVVVSS-TR Plastic QFN
5mm × 5mm
(32 lead)
Tape and
Reel
–40 °C to 85 °C Microsemi Logo
NXP Logo
69200
M15M7V4
XXXXX5
YYYYY6
PD69200-
VVVVSS-TR
PD-OOOOT3bb7
YYWW
PD69208MILQ-TR-LE Plastic QFN
8mm × 8mm
(56 lead)
Tape and
Reel
–40 °C to 85 °C Microsemi Logo
PD69208M
F R e48
YYWWAZZ9
8. F = FAB Code, R = Product revision code (D for V2R2 and E for V2R4), and e4 = 2nd level interconnect.
9. YY = Year, WW = Week, A = Assembly location, and ZZ = assembly lot sequence code.
PD69208MILQ-TR Plastic QFN
8mm × 8mm
(56 lead)
Tape and
Reel
–40 °C to 85 °C Microsemi Logo
PD69208M
F R e48
YYWWAZZ9
Ordering Information
Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 42
The following table lists the manufacturing and ordering part numbers of PD69208M devices.
Customers can order the PD69208M device using either the ordering part number or the manufacturing
part number. See Table 30, page 41 for package, packing type, temperature, and part marking
information.
Table 31 • PD69208M Manufacturing and Ordering Part Numbers
Ordering Part Number Die Revision Product Revision Code Manufacturing Part Number
PD69208MILQ-TR-LE V2R4 E PD69208MILQ-TR-LE
PD69208MILQ-TR V2R4 E PD69208MILQ-TR-LE
