®
Alt er a Cor pora t ion 1
Mercury
Programmable Logic
Device Family
Jan uary 2003, ve r. 2.2 Data Sheet
DS-MERCURY-2.2
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Features… ■High-performance programmable logic device (PLD) family (see
Table 1)
– Integrated high-speed tr ansceivers with support for clock data
recovery (CDR) at up to 1.25 gigabits per second (Gbps)
– Look-up table (LUT)-based architecture optimized for high
speed
– Adv anced inter connect struc ture for fast rout ing of critical paths
– Enhanced I/O structure for versat ile standards and interface
support
– Up to 14,400 logic elements (LEs)
■System -level features
– Up to four general-purpose phase-locked loops (PLLs) with
programmable multiplication and delay shifting
– Up to 12 PLL output ports
– Dedic ated mu ltiplier circuitr y for high-spee d impleme ntation of
signed or unsigned multiplication up to 16 × 16
– Embedded system blocks (ESBs) used to implement memory
functions including quad-port RAM, true dual-port RAM, first-
in first-out (FIFO) buffers, and content-addressable memory
(CAM)
– Each E SB co nta ins 4,0 96 bits and can b e split and used as two
2,048-bit unidirectional dual-port RAM blocks
Note to Table 1:
(1) Each ESB can be used for two dual- or single-port RAM blocks.
Table 1. Mercury Device Features
Feature EP1M120 EP1M350
Typic al gat es 120, 000 350, 000
HSDI channels 8 18
LEs 4,800 14,400
ESBs (1) 12 28
Maximum RAM bits 49,152 114,688
Maxim um us er I/O pins 303 486
2Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
...and More
Features
■Advanced high-speed I/O features
– Robust I/O standard support, including LVTTL, PCI up to
66 MHz, 3.3-V AGP in 1× and 2× mod es , 3. 3- V S S TL -3 an d 2.5 - V
SSTL-2, GTL+, HSTL, CTT, LVDS, LVPECL, and 3.3-V PCML
– High-speed differential interface (HSDI) with dedicated
circuitry for CDR at up to 1.25 Gbps for LVDS, LVPECL, and
3.3-V PC ML
– Support for source-synchronous True-LVDSTM circuitry up to
840 megabi ts pe r se cond (Mbps) fo r LV DS, LVPECL, and 3.3-V
PCML
– Up to 18 input and 18 output dedicated differential channels of
high-spee d LV DS, LVPECL, or 3.3-V PCML
– Built-in 10 0- Ω termination resistor on HSDI data and clock
differential pairs
–Flexible-LVDS
TM circuitry provides 624-Mbps support on up to
100 channels with the EP1M350 device
– Versatile three-register I/O element (IOE) supporting double
data rate I/O (DDRIO), double data-rate (DDR) SDRAM, zero
bus turnaround (ZBT) SRAM, and quad data rate (QDR) SRAM
■Designed for low-power operati on
– 1.8-V internal supply voltage (VCCINT)
– MultiVoltTM I/O interface voltage levels (VCCIO) compatible
wit h 1. 5-V, 1.8-V, 2.5-V, an d 3.3-V devices
– 5.0-V tolerant with external resistor
■Ad vanc ed interconnect struct ure
– Mult i- le vel Fa stT rac k® Interconnect structure providing fast,
predictable interconnect delays
– Optimized high-speed Priority FastTrack Interconnect for
routing critical paths in a design
– Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
softw are tools and megafunctions)
–FastLUT
TM connection allo wing high spee d direct connec tion
between LEs in the same logic array block (LAB)
– Leap lines allowing a single LAB to directly drive LEs in adjacent
rows
– The RapidLAB interconnect providing a high-speed connection
to a 10-LAB-wide region
– Dedicated clock and control signal resources, including four
dedicated clocks, six dedicated fast global signals, and additional
row-global signals
Altera Corporation 3
Mercury Pr o grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
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Tables 2 and 3 show the MercuryTM FineLi ne BGATM device package sizes,
options, and I/O pin counts.
General
Description
Mercury devices integrate high-speed differential transceivers and
support for CDR with a speed-optimized PLD architecture. These
transceivers are implemented through the dedicated serializer,
deserializer, and clock recovery circuitry in the HSDI and incorporate
support for the LVDS, LVPECL, and 3.3-V PCML I/O standards. This
cir cuit r y, tog et her with enhance d I /O elem en ts ( IOEs) and supp or t for
numerous I/O standards, allows Mercury devices to meet high-speed
interface requirements.
Mercury devices are the first PLDs optimized for core performance. These
LUT-based, enhanced memory devices use a network of fast routing
resources to achieve optimal performance. These resources are ideal for
data- path , regi ster- inten sive, m ath em atical , digital signal p rocessing
(DSP), or communications designs.
Table 2. Mercury Package Si ze s
Feature 484-Pin
FineLine BG A 780-Pin
FineLine BG A
Pitch (m m ) 1.00 1.00
Area (m m2)529841
Length × width (mm × mm) 23 × 23 29 × 29
Table 3. Mercury Package Option s & I/O Cou nt
Device 484-Pin
FineLine BG A 780-Pin
FineLine BG A
EP1M120 303
EP1M350 486
4Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Mercury devices include other features for performance such as quad-
port RAM, CAM, gene ral purpose PLLs, and ded icated circuitry for
implementing multiplier circuits. Table 4 shows Mercury performance.
Note to Table 4:
(1) The cloc k tree sup port s up t o 400 MHz. Al tho ug h the registere d performan c e for the se d esi gn s exc eed 400 MHz,
they ar e limi t ed by the cl o c k t r ee limi t.
Configuration
The logic, circuitry, and interconnects in the Mercury architecture are
configured with CMOS SRAM elements. Mercury devices are
reco nfi g ur abl e and are 100% tested prior to shipment. As a result, test
vectors d o not have to be gener a ted f or fa ult cove rag e purp ose s. In ste ad,
the de sig ne r can fo cus on sim ul ation and de sig n v er ification. In a ddit ion,
the desig ner doe s not nee d to manage inventorie s of differen t ASI C
designs; Mercury devices can be configured on the board for the specific
functionality required.
Mercury devices are configured at system power-up with data stored in
an Alt era ® seria l configu ration d evice or provided by a s ystem con troller.
Altera offers in-system programmabilit y (ISP)-cap able configu ration
de vices, which co nfigure Mercury devices via a serial data stream.
Mercury devices can be configured in under 70 ms. Moreover, Mercury
devices contain an optimized interface that permits microprocessors to
configure Mercury devices serially or in parallel, synchronously or
asynchronously. This interface also enables microprocessors to treat
Mercury devices as memory and to configure the device by writing to a
virtual memory location, simplifying reconfiguration.
Table 4. Mercury Pe rformance
Application Resources Used Performance
LEs ESBs -5 Speed
Grade -6 Speed
Grade -7 Sp eed
Grade Units
16-bit load able c ounter (1) 16 0 400 400 400 MHz
32-bit load able c ounter (1) 32 0 400 400 400 MHz
32-bit accu m ulat or (1) 32 0 400 400 400 MHz
32-to-1 mult iplexer 27 0 1.864 2.466 2.72 3 ns
32 × 64 asynchronous FIFO 103 2 290 258 242 MHz
8-bit, 37-tap FIR filter 251 1 290 240 205 MSPS
Altera Corporation 5
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After a Mercury device has been configured, it can be reconfigured
in-circu it by reset ting the devic e and lo ading new da ta. Real-time cha nges
can be made during system operation, enabling innovative reconfigurable
computing applications.
Software
Mercury devices are supported by the Altera QuartusTM II development
system, a single, integrated package that offers HDL and schematic design
entry, compilation and logic synthesis, full simulation and worst-case
ti ming an alysi s, Sig nalTapTM logic analysis, a nd device co nfiguratio n. The
Quartus II software also ships with Altera-specific HDL synthesis tools
from Exemplar Logic and Synopsys, and Altera-specific Register Transfer
Level (RTL) and timing simulation tools from Model Technology. The
Quar tus II softw are suppor ts PCs runn ing Window s 98, Wind ows NT 4. 0,
and Windows 2000; UNIX workstations running Solaris 2.6, 7, or 8, or
HP-UX 10.2 or 11.0 ; and PCs running Red Hat Linu x 7.1.
The Quartus II software provides NativeLinkTM interfaces to other
industry-standard PC- and UNIX-workstation-based EDA tools. For
example, designers can invoke the Quartus II software from within the
Mentor Graphics LeonardoSpectrum software, Synplicity’s Synplify
software , and th e Syno psys FP GA Express software. The Quartus II
software also contains built-in optimized synthesis libraries; synthesis
tools ca n use these libr arie s to opti mi ze designs for Merc ury devic es . For
example, the Synopsys Design Compiler library, supplied with the
Quartus II development system, includes DesignWare functions
optimized for the Mercury architecture.
For more information on the Quartus II development system, see the
Quartus II Programmable Logic Development System & Software Data Sheet.
Functional
Description
The Mercury architecture contains a row-based logic array to implement
general logic and a row-based embedded system array to implement
memory and specialized logic functions. Signal interconnections within
Mercury devices are provided by a series of row and column
interconnects with varying lengths and speeds. The priority FastTrack
Interconnect structure is faster than other interconnects; the Quartus II
Compiler places design-critical paths on these faster lines to improve
design perfo rmance.
6Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Mercury device I/O pins are evenly distributed across the entire device
area; other Altera device families have I/O pins placed on the device
periphery. Mercury device I/O pin placement allows for higher I/O count
at a given die size; pad size is no longer a limiting issue. Each I/O pin is
fed by an IOE. IOEs are grouped in IOE row bands from the top to the
bottom of the device. IOE row bands are separated by several LAB rows.
LABs from the associated LAB row closest to the I/O row band drive IOEs
through the local interconnect. This feature allows fast clock-to-output
times w he n a pin is d riven by any of the 1 0 LEs in the a dja ce nt associate d
LAB. Each IOE contains a bidirectional buffer along with an input register,
output register, output enable (OE) register, and input latch for DDR.
When used with a global clock, these dedicated registers provide
exceptional bidirectional I/O performance.
IOEs provide a variety of features, such as 3.3-V, 64-bit, 66-MHz PCI
compl i an ce; 3.3-V, 64-bit , 133 -MH z PC I-X com plianc e; Joi nt Test Acti on
Group (JTAG) boundary-scan test (BST) support; output drive strength
control; slew-rate control; tri-state buffers; bus-hold circuitry;
programmable pull-up r esisters ; progr ammable input a nd output delays;
and open-drain outputs. Mercury devices offer enhanced I/O support,
including support for 1.8-V I/O, 2.5-V I/O, LVCMOS, LVTTL, HSTL,
LVPECL, 3.3-V PCML, 3.3-V PCI, PCI-X, LVDS, GTL+, SSTL-2, SSTL-3,
CTT, and 3. 3-V AGP I/O standards. C D R (u p to 1.25 Gbps) an d source-
synchronous (up to 840 Mbps) transfers are supported with HSDI
circuit ry fo r LV DS, LVPECL, an d 3.3-V PCML I/O s ta ndards.
The ESB can implement a variety of memory functions, including CAM,
quad- port R AM, tr ue dual -por t RAM , d ual - and sin gle -por t RAM, ROM ,
and FIFO functions . ESBs are grou ped i nto two rows: one at the top and
one at the bottom of the device. Embedding the memory directly into the
die improves performance and reduces die area compared to distributed-
RAM implementations. Moreover, the abundance of cascadable ESBs, in
conjunction with the ability for one ESB to implement two separate
memory bloc ks, en sures th at th e Merc ury dev ice can implem ent multipl e
wide me mo ry blocks for hi gh-density designs. The ESB’ s hi gh speed
ensures the implemention of small memory blocks without any speed
penalty. The abundance of ESBs ensures that designers can create as many
different-sized memory blocks as the system requires. Figure 1 shows an
overview of the Mercury device.
Altera Corporation 7
Mercury Pr o grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
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Figure 1. Mer cu ry Architecture Bloc k Diagram Note (1)
Note to Figure 1:
(1) Figure 1 shows an EP1M120 devi ce. Mercury devices h ave a varying number of ro ws, columns, and ESBs, as sh own
in Table 5.
Table 5 lists the resources available in Mercury devices.
Associated LAB Row
Buried LAB Row
Buried LAB Row
Associated LAB Row
Buried LAB Row
Buried LAB Row
Associated LAB Row
Buried LAB Row
Buried LAB Row
Associated LAB Row
Associated LAB Row
Buried LAB Row
ESB ESB ESB ESB ESB ESB
ESB ESB ESB ESB ESB ESB
Local Interconnect:
Connects LEs within
the Same or Adjacent
LABs
Row and Priority Row
Interconnect: Connects
LABs within a Row
Column and Priority
Column Interconnect:
Connects LABs within
Different Rows (Top
to Bottom)
Leap Lines: Connects
Adjacent LABs in
Same Column
RapidLAB Interconnect:
Connects Any 10
Consecutive LABs
within a Row from
a Central LAB
I/O Band with HSDI
I/O Band
I/O Band
I/O Band
I/O Band
Table 5. Mercury Device Resources
Device LAB Rows LAB Columns I/ O R ow Bands ESBs
EP1M120 12 40 5 12
EP1M350 18 80 4 28
8Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Mercu ry devices p ro vide four dedic ated c lock inpu t pins an d six
dedicated fast I/O pins that globally drive register control inputs,
including clocks. These signals ensure efficient distribution of high-speed,
low-skew control signals. The control signals use dedicated routing
channe ls to prov ide sh ort delays a nd low sk ew. The de dicated fa st signal s
can also be driven by interna l logic, providing an ideal solution for a clock
divider or internal l y gener at ed asynchro nous cont rol signal w ith high
fan-out . The dedicated cloc k an d fast I/O pins on Mer cury devices can
also feed logic. Dedicated clocks can also be used with the Mercury
general purp o se PLLs for clock management.
Each I/O row band also provides two additional I/O pins that can drive
two row-global signals. Row-global signals can drive register control
inputs for the LAB row associated with that particular I/O row band.
High-Speed
Differential
Interface
The top I/O or HSDI band in Mercury devices contains dedicated
circuit ry fo r support ing differenti al standards at speeds up to 1.25 Gbps .
Mercu ry devices have dedicated differential buffers and circui try to
support LVDS, LVPECL, and 3.3-V PCML I/O standards. Two dedicated
high-speed PLLs (separate from the general purpose PLLs) multiply
reference clocks and drive high-speed differential serializer/deserializer
channels. In addition, clock recovery units (CRUs) at each receiver
channel enable CDR. EP1M120 devices support eight input channels,
eight output channels, and two dedicated clock inputs for feeding the
receiver and/or transmitter PLLs. EP1M350 devices support 18 input
channels, 18 output channels, and two dedicated clock inputs.
Mercury devices have optional built-in 100-Ω termination resistors on
HSDI differe ntial receiver data pins and the HSDI_CLK1 and HSDI_CLK2
pins.
Designers can use the HSDI circuitry for the following applications:
■Gigabit Ethernet backplanes
■ATM, SONET
■RapidIO
■POS-PHY Level 4
■Fibr e Channel
■SDTV
The HSDI band supports one of two possible modes:
■Source-synchronous mode
■Clock data recovery (CDR) mode
Altera Corporation 9
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In sourc e-sy nc hr onou s mode, sourc e synchr on ous inte rf ac ing is
supported at up to 840 Mbps. Serial channels are transmitted and received
along with a low speed clock. The receiving device then multiplies the
clock by a factor of 1 to 12, 14, 16, 18, or 20. The serialization/
de serializ ation rate can be any nu mber from 4, 7, 8, 9 to 12, 14, 16 , 18, or 20
and do es not have to equal t he clock multi plication va lue. For exa mple, an
840-Mbps LVDS c han ne l ca n be r e ce ived alon g wit h a 8 4-M Hz c lock . Th e
84-MHz clock is multiplied by 10 to drive the serial shift register, but the
register can be clocked out in parallel at 7-, 8-, 9- to 12-, 14-, 16-, 18-, or
20- b its wide at 42 to 120 MHz. See Figures 2 and 3.
Figure 2. Re ceiver Diagram for Source Synchronous Mod e Notes (1), (2)
Notes to Figure 2:
(1) EP1M3 50 d evi ce s ha ve 18 in dividu al rec ei ver c ha nnels. EP1M120 devi c es h ave 8 in dividua l rec ei ver chan n el s .
(2) W = 1 to 12, 14, 16, 18, or 20
J = 4, 7, 8, 9 to 12, 14, 16, 18, or 20
W does not have to equal J.
(3) This clock pin drives an HSDI PLL only. It does not drive to the core.
+
—
Receiver
Channel
+
—
Receiver
Channel
+
—
Receiver
Channel
H
SDI_CLK2
(3)
HSDI
PLL2 ×W1
J
Deserializer Data to
LEs
To Glob
al
Clock
Receiver Channel 1
Receiver Channel 8
Receiver Channel 2
J Bits Wide
10 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Figure 3. Transmitter Diagram for Source Synchronous Mode Notes (1), (2)
Notes to Figure 3:
(1) EP1M350 devices have 18 individual transmitter channels. EP1M120 devices have 8 individual transmitter
channels.
(2) W = 1 to 12, 14, 16, 18 , or 20
B = 1 to 12, 14, 16, 18, or 20
J = 4, 7, 8, 9 to 12, 14, 16, 18, or 20
W, B, and J do not ha ve to be equa l .
(3) This clock pin drives an HSDI PLL only. It does not drive to the logic array.
The Mercury device’s source-synchronous mode also supports the
RapidIO interface protocol at up to 500 Mbps using the LVDS I/O
standard.
fFor more information on source synchronous interfacing see
AN 159: Using HSDI in Source-Synchronous Mode in Mercury Devices.
Transmitter
Channel
HSDI_CLK1
(3)
G
lobal Clock
f
rom Receiver
o
r System Clock HSDI
PLL1
×W
×
1
J
Serializer Data fro
m
LEs
Transmitter Channel 1
J Bits Wide
Transmitter
Channel Transmitter Channel 2
Transmitter
Channel Transmitter Channel 8
TXOUTCLOCK
W
B
Altera Corporation 11
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Table 6 defi nes th e sup port for so urce- synchronous mode appl ications.
Note to Table 6:
(1) You can use the CDR circuit to achieve data rates for DC coupled LVDS
applic ations. Yo u mu st AC -c ou pl e t h e cloc k to a 2.2-V c ommon mod e voltag e
(VCM) usin g the AC -coupl ing s cheme s in AN 134: Using Programmable I/O Standards
in Merc ur y D ev i ces . The data channels sho uld be DC-coupled. The byte ali gnm ent
relative to the clock is l ost when using the CDR circui t. Therefore, a byte-alignment
circuit is required. Most Mercury source-synchronous designs already include
byte -ali gnm ent logic since they u s ually us e DDR or SDR clocks . The CD R r un
length requ irement is waiv ed if the refe rence clock and the receiver data come from
the same source and have the same frequenc y.
In CDR mode, serial data is supported up to 1.25 Gbps per channel. The
system provides a reference clock which is multiplied by the receiver or
transmitte r PL L to the sa me rat e as the d ata is pr ov id ed. F or the rece ive r,
this mult iplie d refer en ce clock is use d by a CR U o n e ac h re ce iver cha nne l
to genera te a recovered c loc k i n-phase with the receiv ed data. That
recovered clock drives the programmable deserializer and synchronizer.
The synchronizer is a FIFO for data transfer between the recovered clock
domain a nd the g lobal cloc k domain. The dedi cated s ynchronizers can b e
bypassed if necessary. For every receiver channel in the EP1M350 and
EP1M120 devices, the ÷J recove red cloc k c an drive a p rio rity column line
for use as a cloc k. See Figure 4.
Tabl e 6. Sou r ce - Sy nch ronous Mode
Data Rate I/O Standard
LVDS LVPECL 3.3-V PCM L
≤840 Mbps (1) vv
12 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Figure 4. Rece iver & Transmitter Diagra ms for CDR Mode Notes (1), (2)
÷
J
Data
J
Synchronizer
Deserializer
DPLL
Data
J
RCLK
+—
Synchronizer
Serializer
Data
J
Synchronizer
Deserializer
DPLL
Data
(3)(3)
J
RCLK
+—
Synchronizer
Serializer
+—+—
PLL2
8
TX4 (TX9) RX4 (RX9) TX5 (TX10) RX5 (RX10)
HSDI_CLK1
(5)
HSDI_CLK2
(5)
(4)
(4) (4) (4)
REFCLK
PLL1
8
REFCLK
GCLK4
GCLK3
GCLK2
GCLK1
4 Dedicated
Clocks
× W× W
÷
J
÷
J
Data
J
Synchronizer
Deserializer
DPLL
Data
J
RCLK
+—
Synchronizer
Serializer
(3)
TX3 (TX8) RX3 (RX8)
÷
J
÷
J
÷
J
Data
J
Synchronizer
Deserializer
DPLL
Data
(3)
J
RCLK
+—
Synchronizer
Serializer
TX6 (TX11) RX6 (RX11)
÷
J
÷
J
Altera Corporation 13
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Notes to Figure 4:
(1) EP 1M 350 device s have 18 indivi d ua l receiver an d tran smitter chann els. EP1M120
devices have 8 individual receiver and transmitter channels. Receiver and
transmitter channel numbers in parenthesis are for EP1M350 devices.
(2) W = 1 to 12, 14, 16, 18, or 20
J = 3 to 12, 14, 16, 18, or 20
W does not have to equal J.
(3) F or ever y rece iv er c h an ne l in EP1M350 and E P 1M 120 devi c es, the ÷ J rec ove red
clock can drive the pr io r it y column inter c onnec t f or us e as a c lo c k.
(4) The t w o ce nte r channels adjacent to the H S DI PL Ls (c hannels 4 a nd 5 fo r EP1M120
devices, channels 9 and 10 for EP1M350 devices) can drive the Mercury device’s
global clocks.
(5) HSDI_CLK1 an d HSDI_CLK2 pins mus t be di f f ere nti a l. These c l ock pins drive
HSDI PLLs only. They do not drive to the logic array.
The multi plied refere nce clo ck is al so used to s ynchroni ze and serial ize at
the transmitter side.
Up to two different serial data rates are supported for input channels or
output channels. Received data must be non-return-to-zero (NRZ).
Table 7 defines the support for CDR-mode applications. Table 8 shows the
supported data rates for each speed grade.
Notes to Table 7:
(1) Th e V CM operatin g rang e for A C-c ou pled appl ic ations is from 0 t o 0.7 V an d fro m 1. 8 t o 2.4 V.
(2) Use AC-coupled LVDS or another I/O standard. The DC-coupled LVDS I/O standard provides performance up to
1.0 Gbps.
fFor more information on CDR, see AN 130: C DR in M ercury Devices.
Table 7. CDR-Mode Applications
Data Rate CDR Mode
DC-Coupled
LVDS DC-Coupled
LVPECL DC-Coupled
3.3 - V PC ML AC-Coupled
LVDS (1) AC-Coupled
LVPECL (1) AC-Coupled
3.3-V PCML
(1)
1.0 to 1.25 Gbps (2) vvvvv
≤1.0 Gbps vvvvvv
14 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
1Mercur y devi ce HS DI p erforma nce is finalized for c erta in speed
grad e s. Al so, t he indust ri al- gr ade C D R spe cif ic at ion is the sa me
as the -6 speed grade for commercial-grade CDR specification.
See Table 8.
Notes to Table 8:
(1) The -6 speed grade specifications apply for both commercial and industrial devices.
(2) EP1M350 devices can support any 8 channels at 1.25 Gbps. The other 10 channels must run at 1.0 Gbps or less.
Logic &
Interconnect
Mercury device logic is implemented in LEs. LE resources are used
differently according to specific operating modes and the type of logic
function being implemented. LEs are grouped into LABs in a row-based
architecture. The multi-level FastTrack Interconnect structure provides
the rou ting connec tion between LEs, ESBs, and IOEs .
Logic Arr ay Blo ck
Each LAB c onsists of 10 LEs , LE ca rry chains, mul tiplier circui try, LAB
control signals, local interconnect, and FastLUT connection lines. The
local interconnect transfers signals between LEs within the same or
adjacent LABs. FastLUT connections transfer the output of one LE to the
adja cent LE for ultr a-fast seque ntial LE con nections wit hin the same LAB.
The Quartus II Compile r places associated log ic within a LAB or adjace nt
LABs, allowing the use of fast local and FastLUT connections for high
performance. Figure 5 shows the Mercury LAB structure.
Table 8. CDR & Source-Synchronous Data Rates
Device Speed Grade Number of Channels Maximum CDR Data
Rate (Gbps) Maximum Source-
Synchronous Data
Rate (Mbps)
EP1M120 -5 8 1.25 840
-6 (1) 8 1.25 840
-7 8 1.0 840
EP1M350 -5 18 1.25 840
-6 (1) 8 (2) 1.25 840
10 (2) 1.0 840
-7 18 1.0 840
Altera Corporation 15
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Figure 5. Mer cu ry LAB Structu re
Notes to Figure 5:
(1) Pr ior it y column lines drive pr iori t y r ow lin es , but not ot her row lin es.
(2) The Rapi d LAB in te r connect can be driv en by p r io r it y column line s , b ut not oth er c o lum n l ines.
(3) In multiplier mode, the RapidLAB interconnect drives LEs directly.
Mercury devices use an interleaved LAB structure, which allows each
LAB to drive two local interconnect areas. Every other LE drives to either
the left or right local interconnect area, alternating by LE. The local
interconnect can drive LEs within the same LAB or adjac en t LABs. This
feature minimizes use of the row and column interconnects, providing
higher performance and flexibility. Each LAB structure can drive 30 LEs
through fast local interconnects.
The 10 LEs in the LAB are driven by
two local interconnect areas. The LAB
can drive two local interconnect areas.
Local Interconnect
Column and Priority
Column Interconnect (1)
Row and Priority
Row Interconnect (1)
RapidLAB Interconnect
to LAB in Row Above
to LAB in Row Below
Leap Line
Interconnect
(2)
(3) (3)
16 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Each LAB contains dedicated logic for driving control signals to its LEs.
The control signals include clock, clock enable, asynchronous clear,
asynchronous preset, asynchronous load, synchronous clear, and
synchronous load signals. A maximum of six control signals can be used
at a ti me. Althou gh synchron ous load an d clear sig nals are g enerally us ed
when implementing counters, they can also be used with other functions.
Each LAB can use two clocks and two clock enable signals. Each LAB’s
clock and clock e na ble s ig nals a re linked (e.g. , a ny LE in a p artic ula r L AB
using LABCLK1 will also use LABCLKENA1). In addition to LAB-wide
control of clock enables, Mercury devices can also control clock enable
signals on individual LEs, allowing more than two clock enables in a
given LAB. The Quartus II soft ware automat ically chooses whe ther a
clock enable is LAB-wide for individu al LEs. If both the rising and falling
edges of a clock are used in a LAB, both LAB-wide clock signals are used.
The LAB local interconnect, fast global signals, row-global signals, and
dedicated clo ck pins can gene rat e the LAB-w ide control signals. The
multi-level FastTrack Interconnect’s inherent low skew allows it to be
used for clock distribution. Figure 6 shows the LAB control signal
generation circuit.
Altera Corporation 17
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Figure 6. LAB-Wide Control Signals
Logic Element
The LE, the smallest unit of logic in the Mercury architecture, is compact
and provides efficient logic usage. Each LE contains a four-input LUT,
whic h is a fu ncti on g en erat or th at can quickly i mple ment an y function of
four variables. In addition, each LE contains a programmable register and
carry chain with carry select look ahead capability. Each LE drives all
inte r conn ect t ypes : local interconne ct , r ow a nd p r iority r ow in te rconnect,
column and priority column interconnect, leap lines, and RapidLAB
inte rconnect. Eac h LE also has th e ability to dr ive its combina torial output
directly to the next LE in the LAB using FastLUT connections. See
Figure 7.
SYNCCLR
or LABCLK2
ASYNCLOAD
or LABPRE
LABCLK1
SYNCLOAD
or LABCLKENA2
LABCLR
LABCLKENA
1
Dedicated
Clocks
Fast Global
Signals
L
ocal
I
nterconnect
L
ocal
I
nterconnect
L
ocal
I
nterconnect
L
ocal
I
nterconnect
4
6
Row Global
Signals 2
18 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Figure 7. Mercury LE
Notes to Figure 7:
(1) FastLU T interconnect uses the data4 input .
(2) LAB carry-out can only be generated by LE 4 and/or LE 10.
Each LE’s programmable register can be configured for D, T, JK, or SR
operati on. T he r egist er ’s clock, cloc k e na ble, a nd cle ar c ontr ol sig nal s ca n
be driven by global signals, general-purpose I/O pins, or any internal
logic. For c ombinator ial fun ctions, the regis ter is bypa ssed a nd the outp ut
of the LUT drives directly to the outputs of the LE.
Each LE has four da ta inputs that can dri ve the inter nal LUT. One of the se
inputs has a shorter delay than the others, improving overall LE
performance. This input is chosen automatically by the Quartus II
so ftware as appropriate.
labclk1
labclk2
labclr
labpre
Carry-In1
Carry-In0
LAB Carry-In
Clock &
Clock Enable
Select
LAB Carry-Out
(2)
Carry-Out1
Carry-Out0
Look-Up
Table
(LUT)
Carry
Chain to Local, Row, an
d
Column Routing
to Local, Row, an
d
Column Routing
Programmable
Register
PRN
CLRN
DQ
ENA
Register Bypass
Packed
Register Select
Chip-Wide
Reset
l
abclkena1
l
abclkena2
Synchronous
Load and
Clear Logic
LAB-wide
Synchronous
Load LAB-wide
Synchronous
Clear
Asynchronous
Clear/Preset/
Load Logic
data1
data2
data3
data4
(1)
FastLUT
Routing to next L
E
LE Clock
Enable
Altera Corporation 19
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Each LE has two outputs that drive the local, row, and column routing
resources. Each output can be driven independently by the LUT’s or
register’s output. For example, the LUT can drive one output, while the
register drives the other output. This feature, called register packing,
impr oves de vice ut ilization b e cau se th e reg iste r a nd t he L UT ca n b e us ed
for unrelated functions. The LE can also drive out registered and
unregistered versions of the LUT output.
LE Operat ing M ode s
The Mercury LE can operate in one of the following modes:
■Normal
■Arithmetic
■Multiplier
Each operating mo de use s LE resources differen tly. In each operat ing
mode, eight available inputs to the LE—the four data inputs from the LAB
local interco nnect; carry-in0, carry-in1 from the previous LE; the
LAB ca rry- in from the prev ious carry-ch ain g ener at ion; an d the Fa stLUT
Connection input from the previous LE—are directed to different
destinations to implement the desired logic function. LAB-wide signals
provide clock, as ynchrono us clear, a sy nc hrono us preset, asy nchrono us
load, synchronous clear, synchronous load, and clock enable control for
the register. These LAB-wide signals are available in all normal and
arithmetic LE modes.
The Quartus II software, in conjunction with parameterized functions
such as LPM and De sig nWar e functions, auto mati cally choos es the
appropriate mode for common functions, such as counters, adders, and
multipliers. If required, the designer can also create special-purpose
functions that specify which LE operating mode to use for optimal
performance.
Normal Mode
The normal mode is suitable for general logic applications and
combinat orial func tion s. I n normal mode, four data inp uts from the LAB
local interconnect and a single carry-in are inputs to a four-input LUT. The
Quartus II Compiler automatically selects the carry-in or the data3 signal
as one of the inputs to the LUT. The LUT (combinatorial) output can be
driven to the FastLUT connection to the next LE in the LAB. LEs in normal
mode support packed registers. Figure 8 shows an LE in norma l mode .
20 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Figure 8. Normal-Mode LE Note (1)
Notes to Figure 8:
(1) LEs in normal mode support register packing.
(2 ) When usin g t h e carry - in in n o r mal mod e, th e packed reg is t er fe at ure is un a v aila ble.
(3) There are two LAB-wide clock enables per LAB in addition to LE-specific clock enables.
Arithmetic Mode
The arithmetic mod e is ideal for imp lementin g adders, accumul ators, and
comparators. A LE in arithmetic mode contains four 2-input LUTs. The
first two 2-input LUTs compute two summations based on a possible
carry of 1 or 0; the other two LUTs generate carry outputs for the two
possible chains of the car ry-select look-ahead (CSL A) circuit ry. As s hown
in Figure 9, the LAB carry-in signa l selects the appropriate carr y-i n chain
(either carry-in0 or carry-in1). The logic level of the chain selected
in turn selects which parallel sum is generated as a combinatorial or
registered output. For examp le, when implementing an adder, this output
is the sig na l compris ed of t he sum data1 + data2 + carry, where carry is
0 or 1. The ot he r two L UT s u se the data1 and data2 signals to ge ne rate
two possible carry-out signals—one for a carry of 1 and the other fo r a
carry of 0. The carry-in0 signal acts as the carry select for the
carry-out0 output; carry-in1 acts as the carry select for the
carry-out1 out put. LEs in arithmetic mode can drive ou t register ed and
unregis tered ve rsions of the LUT outp ut. Figure 9 shows a M ercury LE in
arithmetic mode.
PRN/ALDn
CLRN
DQ
4-Input
LUT
LE-Ou
t
LE-Out
LE-Ou
t
ENA
data1
data2
data3
data4
Carry-In from
P
revious LE
(2)
Registered
Output
Combinatorial
Output
LAB-Wide Clock Enable
(3)
Altera Corporation 21
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The arithmetic mode also offers clock enable, counter enable, synchronous
up/down contr ol, synchr onous cl ear, and s ynchrono us lo ad options . The
counter enable and synchronous up/down control signals are generated
from the da ta in puts o f the LAB lo cal int erconne ct. T he s ynchrono us cle ar
and synchronous load options are LAB-wide signals that affect all
registers i n the LAB. Conseq u en tly, if any of the LEs in a LAB use the
counter mode, other LEs in that LAB must be used as part of the same
counter or be used for a combinatorial function. The Quartus II software
automatically places any registers that are not used by the counter into
other LABs.
Figure 9. A rithmetic Mode LE
Carry-Select Look-Ahead Chain
The CSLA chain provides a very fast carry-forward function between LEs
in arithmetic mode or multiplier mode. The CSLA chain uses the
redundant carry calculation to increase the speed of carry functions. The
LE can calculate sum and carry values for a possible carry-in of 1 and
carry-in of 0 in parallel. The carry-in0 an d carry-in1 sig nal s from a
lower-order bit drive forward into the higher-order bit via the parallel
carr y cha in and f eed into both the LU T an d the next por tion of the CSLA
chain. CS LA chains can begin in an y LE within a LAB.
LUT
LUT
LUT
LUT
data1
LAB Carry-In
data2
data3
Carry-In0
Carry-In1
Carry-Out0 Carry-Out1
PRN/ALDn
CLRn
DQ
LAB-Wide
Synchronous
Load
LAB-Wide
Synchronous
Clear
LE-Ou
t
LE-Ou
t
ENA
LAB-Wide
Clock Enable
Registered
Output
Combinatorial
Output
Sum
22 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
The CSLA chain’s speed advantage results from the parallel pre-
computa tion of carry c hains. Inste ad of inc luding every LUT in the cr itical
path, only the propagation delays between LAB carry-in generation
circuits (LE 4 and LE 10) make up th e critica l path. This featu re allows the
Mercury architecture to implement high-speed counters, adders,
multipliers, parity functions, and comparators of arbitrary width.
Figure 10 shows the CS LA circuitry in a LAB for a 10-bit full adder. One
portion of the LUT generates the sum of two bits using the input signals
and the app ropriat e carry-in bi t; the sum is routed to the outpu t of the LE.
The regis ter can be bypas se d fo r simp l e ad ders o r used for accumulato r
functions. Another portion of the LUT generates carry-out bits. A lab-
wide carry-in bit selects which chain is used for the addition of given
inputs. The actual carry-in signal for that selected chain, carry-in0 or
carry-in1, s elect s the car ry-out to ca rry for ward , which is route d to the
carry-in signal of the next-higher-order bit. The final carry-out signal is
routed to an LE, where it is driven to local, row, or column interconnects.
Altera Corporation 23
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Figure 10. CSLA Detail s
The Quartus II Compiler can create CSLA logic automatically during
design processing. Alternatively, the designer can create CSLA logic
manually during design en try. Par ameterized fu nctions such as lib rary of
parameterized modules (LPM) and DesignWare functions automatically
take advantag e of carry chains for the appropriate functions.
LE4
LE3
LE2
LE1
A1
B1
A2
B2
A3
B3
A4
B4
Sum1
Sum2
Sum3
Sum4
LE10
LE9
LE8
LE7
A7
B7
A8
B8
A9
B9
A10
B10
Sum7
LE6
A6
B6 Sum6
LE5
A5
B5 Sum5
Sum8
Sum9
Sum10
01
01
L
AB Carry-In
LAB Carry-Out
LUT
LUT
LUT
LUT
data1
LAB Carry-In
data2
Carry-In0
Carry-In1
Carry-Out0 Carry-Out1
Sum
24 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
The Quartus II Compiler creates carry chains longer than ten LEs by
linking LABs together automatically. For enhanced fitting, a long carry
chain skips intermediate LABs in a row structure. A carry chain longer
th an one LAB s k ips ei ther fro m an ev en-numbered LAB to th e next even -
number ed LAB, o r fro m an odd-numbered LAB to the next odd-
number ed LA B. For exampl e, the last LE of the first LAB in a LAB row
carries to the first LE of the third LAB in the same LAB row.
Multiplier Mode
Multiplier mode is used for implementing high-speed multipliers up to
16 ×16 in size. The LUT implements the partial product formation and
summation in a single stage for a N × M-bit multiply operation. A single
LE can implement the summation of ANBM + 1 + AN + 1BM for the
multiplier and multiplicand inputs. To increase the speed of the
multiplication, LAB wide signals are used to control the partial product
sum gene ration. These multip lier LAB-wide sig nals use the LABCLKENA1
and PRESET/ASYNCLOAD resources. The multiplier mode takes
advanta ge of the C SLA cir c uitr y for optimi z ed su m and ca r ry g ener at ion
in the partial product sum. There is a special CSLA circuitry mode used
for the multiplier where the carry chain runs vertically between LABs in
the sa me colu mn. The Quartus I I Compiler autom atically use s this speci al
mode for dedicated multiplier implementation only. The summation of
the multiplier and multiplicand bits is driven out along with the carry-
out0 and carry-out1 bits. The combinatorial or registered versions of
the sum can be driven out, allowing the multiplier to be pipelined.
The RapidLAB interconnect has dedicated fast connections to the LE
inputs in multiplier mode, further increasing the speed of the multiplier.
These dedicated con nections al low RapidLAB l i ne s to avoid dela y
incurred by driving onto local interconnects and then into the LE.
The Quar tus II so ftware imple ments para meteriz ed functions tha t use the
multiplier mode automatically when multiply operators are used.
Figure 11 shows a Mercury device LE in multiplier mode.
Altera Corporation 25
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Figur e 11. Mult iplier Mode LE
Notes to Figure 11:
(1) LABCLKENA1 cannot be used in mult ipli er mode.
(2) When th e Rapi d L A B o utput is used, loca l inte rco n nect o u t puts ar e unavailable.
The basis for the high-speed 16 × 16-bit multiplier in a Mercury device is
the bina r y tree multiplier. In the first stage of the binar y tree, the
mult iplicand bi ts, a[15:0], and the multiplier bits, b[15:0], are
multipl ied toget he r. The r es ults of the firs t sta ge ar e six teen 1 6-b it pa rtia l
products, a[15:0]b[15], a[15:0]b[14], . . . a[15:0]b[0]. The
partial products are then grouped into pairs and added together in the
second stage. In a similar fashion, the results of the previous stage are
groupe d in pairs an d then add ed forming the binary tr ee structur e seen in
Figure 12.
LAB Carry-In
Carry-In0
Carry-In1
Carry-Out0
Carry-Out1
LAB Carry-Out
CLRN
DQ
ENA
Registered
Sum Output
Combinatorial
Sum Output
Combinatorial
Sum Output
Programmable
Inverter
Programmable
Inverter
AN
B
M + 1
Programmable
Inverter
Programmable
Inverter
AN + 1
BM
Full
Adder
LAB-Wide Clock
Enable Signals
(1)
Partial Product
Generation
RapidLAB
Interconnect
(2
)
LE Output
LE Output
26 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Figure 12. Partial Product Formation
A15B0
A14B1
A13B2
A12B3
A11B4
A10B5
A9B6
A8B7
A7B8
A6B9
A5B10
A4B11
A3B12
A2B13
A1B14
A0B15
A15B1
A14B2
A13B3
A12B4
A11B5
A10B6
A9B7
A8B8
A7B9
A6B10
A5B11
A4B12
A3B13
A2B14
A1B15
A15B2
A14B3
A13B4
A12B5
A11B6
A10B7
A9B8
A8B9
A7B10
A6B11
A5B12
A4B13
A3B14
A2B15
A15B3
A14B4
A13B5
A12B6
A11B7
A10B8
A9B9
A8B10
A7B11
A6B12
A5B13
A4B14
A3B15
A15B4
A14B5
A13B6
A12B7
A11B8
A10B9
A9B10
A8B11
A7B12
A6B13
A5B14
A4B15
A15B5
A14B6
A13B7
A12B8
A11B9
A10B10
A9B11
A8B12
A7B13
A6B14
A5B15
A15B6
A14B7
A13B8
A12B9
A11B10
A10B11
A9B12
A8B13
A7B14
A6B15
A15B7
A14B8
A13B9
A12B10
A11B11
A10B12
A9B13
A8B14
A7B15
A15B8
A14B9
A13B10
A12B11
A11B12
A10B13
A9B14
A8B15
A15B9
A14B10
A13B11
A12B12
A11B13
A10B14
A9B15
A15B10
A14B11
A13B12
A12B13
A11B14
A10B15
A15B11
A14B12
A13B13
A12B14
A11B15
A15B12
A14B13
A13B14
A12B15
A15B13
A14B14
A13B15
A15B14
A14B15
A
15B15
A14B0
A13B1
A12B2
A11B3
A10B4
A9B5
A8B6
A7B7
A6B8
A5B9
A4B10
A3B11
A2B12
A1B13
A0B14
A13B0
A12B1
A11B2
A10B3
A9B4
A8B5
A7B6
A6B7
A5B8
A4B9
A3B10
A2B11
A1B12
A0B13
A12B0
A11B1
A10B2
A9B3
A8B4
A7B5
A6B6
A5B7
A4B8
A3B9
A2B10
A1B11
A0B12
A11B0
A10B1
A9B2
A8B3
A7B4
A6B5
A5B6
A4B7
A3B8
A2B9
A1B10
A0B11
A10B0
A9B1
A8B2
A7B3
A6B4
A5B5
A4B6
A3B7
A2B8
A1B9
A0B10
A9B0
A8B1
A7B2
A6B3
A5B4
A4B5
A3B6
A2B7
A1B8
A0B9
A8B0
A7B1
A6B2
A5B3
A4B4
A3B5
A2B6
A1B7
A0B8
A7B0
A6B1
A5B2
A4B3
A3B4
A2B5
A1B6
A0B7
A6B0
A5B1
A4B2
A3B3
A2B4
A1B5
A0B6
A5B0
A4B1
A3B2
A2B3
A1B4
A0B5
A4B0
A3B1
A2B2
A1B3
A0B4
A3B0
A2B1
A1B2
A0B3
A2B0
A1B1
A0B2
A1B0
A0B1
A0B0
A15
B15
A14
B14
A13
B13
A12
B12
A11
B11
A10
B10
A9
B9
A8
B8
A7
B7
A6
B6
A5
B5
A4
B4
A3
B3
A2
B2
A1
B1
A0
B0
== == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == ==
=
= == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == == ==
×
Sixteen 16-Bit
Partial Product
s
Altera Corporation 27
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For a typica l 16 × 16-bit binary tree multiplier, five stages are needed to
dete rmin e the fina l prod uct . Th e Mercury LE multi plie r mode allow s the
partial product formation stage (Stage 1) and the first sum of stages
(Stage 2) to be combined in a single stage, shown in Figure 13. This
fea ture, combi ned with the d irect connection between Ra pidLAB line s
and LEs in multip lier mode, allo ws the fast dedicated impleme nta tion of
multipliers.
28 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Figure 13. Mercury Binary Tree Implementation
A[15:0] B[15] A[15:0] B[14] A[15:0] B[13] A[15:0] B[12] A[15:0] B[11] A[15:0] B[10] A[15:0] B[9] A[15:0] B[8] A[15:0] B[7] A[15:0] B[6] A[15:0] B[5] A[15:0] B[4] A[15:0] B[3] A[15:0] B[2] A[15:0] B[1] A[15:0] B[0]
+
+
+
+
+ + + + + + +
+
+ + +
Stage 1
Stage 2
Stage 3
Stage 4
Stage 5
Stages 1 and 2 are
combined into one level
of LEs
Altera Corporation 29
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Clear & Preset Logic Control
LAB-wide signals control logic for the register’s clear and preset signals.
The LE directly supports an asynchronous clear and preset function. The
direct asynchro nous preset does not require a NOT-gate push-back
technique. Mercury devices support simultaneous preset, or
asynchronous load, and clear. Asynchronous clear takes precedence if
both signals are asserted simultaneously. Each LAB supports one clear
and one preset signal. Two clears are possible in a single LAB by using a
NOT-gate push-back technique on the preset port. The Quartus II
Compiler automatically performs this second clear emulation.
In add i ti o n to the clear and pr eset ports, Me rc ur y dev ice s p ro vi de a c hip-
wide reset pin (DEV_CLRn) that resets all registers in the device. Use of
this pin is controlled through an option in the Quartus II software that is
set before compilation. The chip-wide reset overrides all other control
signals.
Multi- Leve l Fas tTrack Int e r con nec t
The Mercury architecture provides connections between LEs, ESBs, and
device I/O pins via an innovative Multi-Level FastTrack Interconnect
struct ur e. The Multi-Le vel FastT r ack In terc onne ct stru ctu re is a series of
routing channels that traverse the device, providing a hierarchy of
interconnect lines. Regular resources provide efficient and capable
conne ctions while priority re sources and specialize d Rapi dLAB, leap line,
and FastLUT resources enhance performance by accelerating timing on
critical paths. The Quartus II Compiler automatically places critical design
paths on those faster lines to improve design performance.
This network of routing structures provides predictable performance,
even for complex designs. In contrast, the segmented routing in FPGAs
requires switch matrices to connect a variable number of routing paths,
incr easing the dela ys betwe en logic r esource s and r educing perfor mance.
The Multi-Level FastTrack Interconnect consists of regular and priority
lines t hat t raver se col umn a nd row i nter connec t chan nels to spa n sec tion s
and the entire devi ce length. Each ro w of LABs, ESBs, and I/O bands is
served by a dedicated row interconnect, which routes signals to and from
LABs, ESBs, an d I/O ro w ba nds in the same row. These row resourc es
include:
■Row interconnect traversing the entire device from left to right
■Priority row interconnect for high speed access across the length of
the device
■RapidLAB interconnect for horizontal routing that traverses a
10-LAB-wide region from a central LAB
30 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
The RapidLAB interconnect provides a specialized high-speed structure
to allow a cen tral LAB to drive oth er LABs wit hin a 10-LAB -wide re gion.
The RapidLAB line s driv e alternati ng local LAB in te rconnect r egio ns,
allowing communication to all LABs in the 10-LAB-wide region. Even
numbered LEs in a LAB directly drive a RapidLAB line that drives one set
of alternating local interconnect regions, while odd-numbered LEs drive
a RapidLAB line that drives the opposite set of alternating local
interconnect regions. Figure 14 shows RapidLAB interconnect
connections. This 10-LAB wide region of the RapidLAB interconnect is
repea ted for every LAB in the row. The reg ion cov ered by the RapidL AB
interconnect is smaller than 10 for source LABs that are four or five LABs
in from either edge of the LAB row. The RapidLAB row interconnect is
used for LAB-to-LAB routing; it is only used by I/O bands or ESBs
indirectly through other interconnects. The RapidLAB interconnect drives
an LE directly when that LE is in multiplier mode.
Altera Corporation 31
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Figure 14. R apidLA B I nter con nec t Connecti ons
The column interconnect vertically routes signals to and from LABs, ESBs,
and I/O bands. Each column of LABs is served by a dedicated c o lumn
interconnect. These column resources include:
■Column interconnect traversing the entire device from top to bottom
■Priorit y column interco nne ct for high speed acc ess across the devic e
vertically
■Leap line interconnect for vertical routing between adjacent LAB
rows and between adjacent ES P ro ws and LAB rows.
Leap lines are driven directly by LEs for fast access to adjacent row
inte rconnects. LAB s can drive a leap line to the row above and/ or below
(including ESB rows ). T he even -numbered LEs in a LAB driv e leap lines
down, while odd-numbered LEs drive leap lines up. This allows a single
LAB to access row an d Rapi dLAB interconnects with i n a three-row
region. Figure 15 shows the leap line interconnect.
LE 1
LE 3
LE 5
LE 7
LE 9
LE 2
LE 4
LE 6
LE 8
LE 10
RapidLAB Interconnect
Local Interconnect
RapidLAB interconnects driven by odd-numbered
LEs can drive out to the four LEs to the left and five
LEs to the right through local interconnects.
RapidLAB interconnects driven by even-numbered
LEs can drive out to the four LEs to the right and five
LEs to the left through local interconnects.
LAB
32 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Figure 15. Leap Line Interconnect
FastLUT Interconnec t
Mercury devices include an enhanced interc onnect struc ture within LABs
for faster routing of LE output to LE input connections. The FastLUT
connection allows the comb ina toria l outp ut of an LE to d ire ctly dri ve th e
fast input o f the LE directly below it, bypassing the local interconnect. This
resour ce ca n be use d as a hi gh spe ed conne ction for wid e fan-in functions
from LE 1 to LE 10 in th e same LAB. Figure 16 shows a FastLUT
interconnect.
LAB Row n-1
LAB Row n
LAB Row n+1
Priority Row
and Row
RapidLAB
Leap Line
Leap Line
LE 10
LE 9
LE 8
LE 7
LE 6
LE 5
LE 4
LE 3
LE 2
LE 1
LE 10
LE 9
LE 8
LE 7
LE 6
LE 5
LE 4
LE 3
LE 2
LE 1
LE 10
LE 9
LE 8
LE 7
LE 6
LE 5
LE 4
LE 3
LE 2
LE 1
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Figu re 16. FastLUT Intercon nect
ESB rows also ha ve their o wn interconnect resources to commu nicate
horizontally and vert i ca l l y with LAB rows. Th e ESB rows at the top an d
bottom of the device have their own set of row and priority row
inte rconn ect resour ce s. For vertic al communi cat ion, all LAB column
interconnect lines traverse to the ESBs. This includes leap lines, which
allow the adjacent LAB rows to communicate with the ESBs.
The row inter con nect resour c es ca n be driven direct ly by LEs or ESBs in
that row. Further, the column interconnect resources can drive a row line,
allow ing LEs, IOEs, a nd ES Bs to driv e eleme nts in a differe nt row via the
column and row re sources.
The colu mn intercon nect res ources can b e direc tly driven by LEs , IOEs, or
ESBs within that column. The p riority col umn and leap line resource s can
be driven directly by LEs. These lines enable high-speed vertical
communication in the device for timing-critical paths. The column
resources route signals between rows. A column resource can drive row
resources directly, allowing fast connections between rows.
LE 1
LE 2
LE 3
LE 4
LE 5
LE 6
LE 7
LE 8
LE 9
LE 10
FastLUT
Routing to
Adjacent LE
Local Interconnect
Routing Among LEs
in the LAB
34 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Table 9 summa ri ze s ho w various elements of the Merc ury architecture
drive each other.
Notes to Table 9:
(1) This direct connection is possible through the FastLUT connection.
(2) IOEs can connect to the adjacent LAB’s local interconnects in the associated LAB row.
(3) IOEs can connect to row and priority row interconnects in the associated LAB row.
(4) This connection is used for multiplier mode.
Embedded
System Block
The ESB can implement vario us types of memory blocks, inc luding quad-
port, tru e dual-port, dual - and sin gle-p o rt RAM, ROM, FIFO, and CAM
blocks.
The ESB includes input and output registers; the input registers
synchronize reads and/or writes, and the output registers can pipeline
designs to further increase system performance. The ESB offers a quad
port mod e, which s upports u p to four port o peration s, two rea ds and two
writes simultaneously , wi th the abil ity for a d iffere nt cloc k on e ac h of the
four ports. Figure 17 shows the ESB quad-port blo ck diagram.
Table 9. Mer cury Routing S cheme
Source Destination
LE Local
Interconnect IOE ESB Row
Interconnect ESB Row Priority
Row RapidLAB
Interconnect Column Priority
Column Leap
Lines
LE v
(1) v vvvvvv
Local
Interconnect vv
IOE v(2) v
(3) v(3) vv
ESB Row
Interconnect v
ESB vvvv
Row v
Priority Row v
RapidLAB
Interconnect v
(4) v
Column vvv v
Priority
Column v vvvv
Leap Lines v vvvv
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Figure 17. ESB Quad-Port Block D iagr am
In addition to quad port memory, the ESB also supports true dual-port,
dual-port, and single-port RAM. True dual-port RAM supports any
combination of two port operations: two reads, two writes, or one read
and one write. Dual-port memory supports a simultaneous read and
write . For single-por t memory, inde pendent read and writ e is supporte d.
Figure 18 shows these different RAM memory port configurations for an
ESB.
data
A
[ ]
wraddress
A
[ ]
wren
A
inclock
A
inclocken
A
inaclr
A
rdaddress
A
[ ]
rden
A
q
A
[ ]
outclock
A
outclocken
A
outaclr
A
data
B
[ ]
wraddress
B
[ ]
wren
B
inclock
B
inclocken
B
inaclr
B
rdaddress
B
[ ]
rden
B
q
B
[ ]
outclock
B
outclocken
B
outaclr
B
AB
36 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Figure 18. RAM Memory Port Configurations
Note to Figure 18:
(1) Two d ual- or single-por t memory bl o c ks c a n be imp leme nt ed in a single ESB .
The ESB also allows variable width data ports for reading and writing to
any of the RAM por ts in any RAM con figuration . For example , the ESB in
quad port configuration can be written in ×1 mode at port A, read in ×16
from port A, written in ×4 mode at por t B, and read in ×2 mode fr om
port B.
dataA[ ]
addressA[ ]
wrenA
clockA
clockenA
qA[ ]
aclrA
dataB[ ]
addressB[ ]
wrenB
clockB
clockenB
qB[ ]
aclrB
AB
data[ ]
wraddress[ ]
wren
inclock
inclocken
inaclr
rdaddress[ ]
rden
q[ ]
outclock
outclocken
outaclr
data[ ]
address[ ]
wren
inclock
inclocken
inaclr
q[ ]
outclock
outclocken
outaclr
True Dual-Port Memory
Single-Port Memory
(1)
Dual-Port Memory
(1)
Altera Corporation 37
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ESBs can implement synchronous RAM, which is easier to use than
asynchron ous RAM. A circuit using as ynchronous RAM must g en erate
the RAM write enable (WE) signal wh ile ensur ing that it s data and a ddress
signals meet setup and hold time specifications relative to the WE signal.
In co ntr as t, th e E SB ’s syn chr on ous R AM gen erates its own WE signal and
is se lf -timed wi th r e spe ct to the global cl ock . C ir cuit s using th e E SB ’ s self-
timed RAM must only meet the setup and hold time specifications relative
to the global clock.
ESBs are g rouped toget her in r ows at the top and b ottom of the d evice for
fast horizontal communication. The ESB row interconnect can be driven
by any ESB in the row. The row interco nne ct drives the ESB local
interconnect, which in turn drives the ESB ports. ESB outputs drive the
ESB local interconnect, which can drive row interconnect as well as all
types of column interconnect, including leap lines. The leap lines allow
fast access betw een ES Bs and the adjacent LA B ro w.
When implementing memory, each ESB can be configured in any of the
fol lowing s izes for quad por t and true dual- port mem ory mode s: 256 × 16;
512 × 8; 1,024 × 4; 2,048 × 2; or 4,096 × 1. For dual-port and single-port
mo des , the ES B can b e co nf igure d f or 12 8 × 32 in ad dition to th e list abo ve.
For varia ble port width RAMs, any port width ratio comb ination must be
1, 2, 4, 8, or 16. F or example, a RAM with dat a ports of wi d th 1 and 16 or
2 and 32 w ill wo rk, but not 1 and 32.
The ESB can also be split in half and used for two independent 2,048-bit
sing le-port or dual-port RA M block s. For example , one half of the ESB c an
be used as a 12 8 × 16 memory single-port memory while the other half can
be used for a 1,024 × 2 dual-port memory. This effectively doubles the
num ber of RAMs a Mercur y devi ce ca n implem e nt fo r its given num ber
of ESBs. The Quartus II software automatically merges two logical
memory function s in a desi gn into an ESB; the designer does not ne ed t o
merge the functions manually.
By combining multiple ESBs, the Quartus II software implements larger
memory blocks aut omatically. For exampl e, two 256 × 16 RAM blocks ca n
be com bi ned to fo r m a 25 6 × 32 RAM block, and two 512 × 8 RAM blo ck s
can be combine d to for m a 5 1 2 × 16 RAM block. Memory performance
does not degrade for memory blocks up to 4,096 words deep . Each ESB
can impl ement a 4,096-word -deep memory; the ESBs are used in parallel,
eliminating the need for any external control logic and its associated
delays. To c r eate a high -spe ed m emo ry bloc k more than 4, 096 w ords
deep, the Quartus II software will automatically combine ESBs with LE
control logic.
38 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
The ESB implements two forms of clocking modes for quad-port and
dual-port memory—read/write clock mode and input/output clock
mode.
Read/W rite Cloc k Mo de
An ESB implementing quad-port memory in read/write clock mode can
use up to four clocks. For port A, one clock controls all registers associated
with writing: data input, WE, and write address. The other clock controls
all registers associated with reading: read enable (RE), read address, and
data output. Another set of clocks can be used for port B of the RAM, or
the same clocks can be used. Each ESB port, A or B, also supports
independent read clock enable, write clock enable, and asynchronous
clear signals. Read/write clock mode is commonly used for applications
where re ad s and wr ite s o ccu r at di ff ere nt system freq uen c ie s. Figure 19
shows the ESB in read/write clock mode.
Altera Corporation 39
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Figure 19. ESB in R ead/W rite Clock Mode Notes ( 1), (2)
Notes to Figure 19:
(1) Only half of the ESB, either A or B, is used for dual-port configuration.
(2) All registers c an be asynchronously cleared by ES B l ocal interconnect signals, global signals, or the ch ip-wide reset.
(3) This configuration is supported for dual-port configuration.
Four Dedicated Clocks
46
D
ENA Q
D
ENA
Q
D
ENA Q
D
ENA
Q
D
ENA
Q
dataA[]
rdaddressA[]
wraddressA[]
RAM/ROM
128 × 32
(3)
256 × 16
512 × 8
1,024 × 4
2,048 × 2
4,096 × 1
Data In
Read Address
Write Address
Read Enable
Write Enable
Data Out[]
Data In
Read Address
Write Address
Read Enable
Write Enable
Data Out[]
outclkenA
inclkenA
inclockA
outclockA
D
ENA Q
Write
Pulse
Generator
rdenA
wrenA
Six Dedicated Inputs & Global Signals
qA[]
46
ENA
dataB[]
rdaddressB
[]
wraddressB
[]
outclkenB
inclkenB
inclockB
outclockB
Write
Pulse
Generator
rdenB
wrenB
qB[]
ENA
ENA
ENA
D
ENA
Q
ENA
AB
DQ
DQ
DQ
DQ
DQ
40 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Input /Out put C loc k Mode
An ESB using inpu t/output clock mode c an al so use up to four c locks. On
each of the two ports , A or B, on e clock co ntrols all r egist ers for inputs int o
the ESB: dat a input, WE, RE, read a ddress, and writ e address. The other
clock controls the ESB data output registers. Each ESB port, A or B, als o
supports independent read clock enable, write clock enable, and
asynchronous clear signals. Input/output clock mode is commonly used
for applications where the reads and writes occur at the same system
frequency, but require different clock enable signals for the input and
output reg iste r s. Figure 20 shows the ESB in input/output clock mode.
Altera Corporation 41
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Figure 20. ESB in I nput/Output Cloc k Mo de Notes (1) , (2)
Notes to Figure 20:
(1) Only half of the ESB, either A or B, is used for dual-port configuration.
(2) All registers c an be asynchronously cleared by ES B l ocal interconnect signals, global signals, or the ch ip-wide reset.
(3) This configuration is supported for dual-port configuration.
Four Dedicated Clocks
46
D
ENA Q
D
ENA
Q
D
ENA Q
D
ENA Q
D
ENA
Q
dataA[ ]
rdaddressA[ ]
wraddressA[ ]
RAM/ROM
128 × 32
(3)
256 × 16
512 × 8
1,024 × 4
2,048 × 2
4,096 × 1
Data In
Read Address
Write Address
Read Enable
Write Enable
Data Out[]
Data In
Read Address
Write Address
Read Enable
Write Enable
Data Out[]
outclkenA
inclkenA
inclockA
outclockA
D
ENA Q
Write
Pulse
Generator
rdenA
wrenA
Six Dedicated Inputs & Global Signals
qA[]
46
ENA
dataB[ ]
rdaddressB[ ]
wraddressB[ ]
outclkenB
inclkenB
inclockB
outclockB
Write
Pulse
Generator
rdenB
wrenB
qB[]
ENA
ENA
ENA
ENA
ENA
AB
DQ
DQ
DQ
DQ
DQ
DQ
42 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Sing le- P or t Mode
The Mercury device’s ESB also supports a single-port mode, which is used
when si mul taneous reads and writes are n ot requi red . See Figure 21. A
single ESB can support up to two single-port mode RAMs.
Figure 21. ESB in Single-Port Mode Note (1)
Notes to Figure 21:
(1 ) A ll r e g is t ers can be as yn c hro n o usly cl eared by ESB loca l inter c o n nect si gnals , glo bal signals , or ch ip-wide r es et .
(2) If there is only one single-port RAM block in an ESB, it can support the following configurations: 4,096 × 1; 2,048 ×2;
1,028 × 4; 512 × 8; 25 6 × 16; or 128 × 32.
Content-Addressable Memory
Mercury devices can implement CAM in ESBs. CAM can be thought of as
the inverse of RAM. RAM stores data in a specific location; when the
system submits an address, the RAM block provides the data. Conversely,
when the system submits data to CAM, the CAM block provides the
address where the data is found. For ex amp le, if the data FA12 is stored
in addr es s 14, the CAM outputs 14 whe n FA12 is driven into it.
Dedicated Clocks
46
D
ENA Q
D
ENA
Q
D
ENA Q
D
ENA
Q
data[ ]
address[ ]
RAM/ROM
(2)
128 × 16
256 × 8
512 × 4
1,024 × 2
2,048 × 1
Data In
Address
Write Enable
Data Out
outclken
inclken
inclock
outclock
Write
Pulse
Generator
wren
Dedicated Fast
Global Signals
To FastTrac
k
Interconnec
t
Altera Corporation 43
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CAM is used for high-speed search operations. When searching for data
within a RAM block, the search is performed serially. Thus, finding a
partic ular data w ord can take many cy cles. CAM se arches all a ddresses in
paral lel and outputs the a ddress stori ng a part icular wo rd. When a match
is found, a match flag is set high. CAM is ideally suited for applications
such as Ethernet address lookup, data compression, pattern recognition,
cache tags, fast routing table lookup, and high-bandwidth address
filtering. Figure 22 shows the CAM block diagram.
Figure 22. CAM Block Diagram
The Mercury on-chip CAM provides faster system performance than
traditional discrete CAM. Integrating CAM and logic into the Mercury
device eliminates off-chip and on-chip delays, improving system
performance.
When in CAM mode, the ESB implements a 32-word, 32-bit CAM. Wider
or deeper CAM, such as a 32-word, 64-bit or 128-word, 32-bit block, can
be imple men te d b y comb ining multiple CAM blocks with some ancilla r y
logic implemented in LEs. The Quartus II software automatically
combine s ESBs and LEs to cr ea te larger CA M bl o cks.
CAM supports writing “don’t care” bits into words of the memory. The
don’t-care bit can be used as a mask for CAM comparisons; any bit set to
don’t-care has no ef fe ct o n ma tch e s.
CAM can generate outputs in three different modes: single-match mode,
multiple-match mode, and fast multiple-match mode. In each mode, the
ESB outputs the ma tc h ed data’s location as an encoded or unencoded
ad dre ss. Whe n e ncod ed, the ESB ou tput s an enc ode d a ddre ss o f t he data ’s
locat ion. For instance, if the data is loca te d in ad dress 12, the ESB output
is 12. When unencoded, each ESB port uses its 16 outputs to show the
locat ion of the data over two clo ck cycles. In this case, if th e data is located
in address 12, the 12th output line goes high. Figures 22 and 23 show the
encoded CAM outputs and unencode d CAM outpu ts , r es pe ctively.
data[ ]
wraddress[ ]
wren
inclock
inclocken
inaclr
data_address[ ]
match
outclock
outclocken
outaclr
44 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Figure 23. Encoded CAM Address Outputs
Figure 24. Unencoded CAM Address Outputs
Notes to Figure 24:
(1) For an unencoded output, the ESB only supports 31 input data bits. One input bit
is used by the select line to choose one of the two banks of 16 outputs.
(2) If the select input is a 1, then CAM outputs odd words between 1 through 15. If
the select input is a 0, CAM ou tpu ts wor d s even wor ds betwe en 0 through 14.
In single-match mode, it takes two clock cycles to write into CAM, but
only one clock cycle to read from CAM. In this mode, both encoded and
unencoded outputs are available without external logic. Single-match
mode is better suited for designs without duplicate data in the memory.
CAM
data[31..0] = 45 addr[15..0] = 12 Encoded Outp
ut
match = 1
AddressData
10
11
12
13
15
27
45
85
CAM
data[30..0] =45
(1)
select
(2)
q0
Unencoded outputs.
q12 goes high to
signify a match.
q12
q13
q14
q15
AddressData
10
11
12
13
15
27
45
85
Altera Corporation 45
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If the same data is written into multi ple locati ons in the memor y, a CAM
block can be used in multiple-match or fast multiple-match modes. The
ESB outputs the ma tched data’s locations as an enc o ded or unencod ed
addre ss . In multiple-match mode, it ta kes tw o cloc k cy cl es t o write into a
CAM bloc k. For re ading, t here are 1 6 output s from each E SB at each clock
cycle. Therefore, it takes two clock cycles to represent the 32 words from
a single ESB port . In this mode, encoded and unenco ded outputs are
ava il able. To implement the encoded versio n, the Qu artus II soft ware
adds a priority encoder with LEs. Fast multiple-match is identical to the
multiple-match mode, however, it only takes one clock cycle to read from
a CAM block and generate va lid outputs. To do th is, the enti re ESB i s used
to represent 16 outputs. In fast multiple-match mode, the ESB can
implement a maximum CAM block size of 16 words.
A CAM block can be pr e -loade d wit h da ta dur ing c onfig ur ation, or it ca n
be written during system operation. In most cases, two clock cycles are
required to write each word in to C AM. Wh en don’t -care bits are used, a
third clock cycle is required.
fFor more information on CAM, see Application Note 119 (Implementing
High-Speed Search Applications with APEX CAM).
Driv ing into ESBs
ESBs pr ovide flex ible opt ions for drivin g c ontrol s ign als. Differ ent cloc ks
can be used for the ESB inputs and outputs. Registers can be inserted
independently on the data input, data output, read address, write
address, WREN, and RDEN signals on each port of the ESB. The fast global
signals and ESB l o cal intercon nect can drive t he WREN and RDEN sig nals.
The fast global signals, dedicated clock pins, and ESB local interconnect
can drive the ESB clock signals. The ESB local interconnect is driven by the
ESB row interconnects which, in turn, are driven by all types of column
interconnects, including high-speed leap lines. Because the LEs drive the
column in terconn ect to t he ESB loc al inter connect , the LEs ca n contr ol the
WREN and RDEN signals and the ESB clock, clock enable, and asynchronous
clear signals. Figure 25 shows the ESB control signal generation logic.
46 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Figu r e 25 . ESB Co nt rol Sign al Ge ne r at i on
The ESB can drive row interconnects within its own ESB row and can
directly d rive all the col umn interconne ct s: column, priorit y column , a nd
leap lines.
Implementi ng Logic in ROM
In add ition to imple menting RAM functi ons, the E SB can imp lement l ogic
functions when it is programmed with a read-only pattern during
configuration, creating a large LUT. With LUTs, combinatorial functions
are implemented by looking up the results, rather than by computing
them. This implementation of combinatorial functions can be faster than
using algorit hms implemented in genera l logic, a performa nce advantage
fur ther enhanced by th e fast access times of ES B s. The large c apacity of
ESBs ena bles d esigners to imple ment co mplex funct ions in one lo gic level
without the routing delays associated with linked LEs or distributed RAM
blocks. Para mete r ized function s such as LPM funct ions can take
advanta ge of the ES B autom at ica lly . Fur th er, the Qua rtus I I soft wa re can
implement portions of a design with ESBs where appropriate.
INCLOCK
INCLOCKEN
OUTCLOCK
OUTCLOCKEN
Dedicated
Clocks
Fast Global
Signals
L
ocal
I
nterconnect
L
ocal
I
nterconnect
L
ocal
I
nterconnect
L
ocal
I
nterconnect
4
6
L
ocal
I
nterconnect
L
ocal
I
nterconnect WREN
INCLR
OUTCL
R
RDEN
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Programmable Speed/Power Control
Mercury device ESBs offer the Turbo BitTM option, a high-speed mode that
supports fast operation on an ESB-by-ESB basis. When high speed is not
required, the Turbo Bit option can be turned off to reduce power
dissipation by up to 50%. ESBs that run at low power incur a nominal
timing delay adder. An ESB that is not used will be powered down so it
does not consume DC current.
Designers can program each ESB in the Mercury device for either high-
speed or low-power operation. As a result, speed-critical paths in the
design can run at high speed, while the remaining paths operate at
reduced power.
I/O Structure The IOE in Mercury devices contains a bidirectional I/O buffer and three
registers for a c omplete embedded bidirectional IOE. T he IOE con tains
individual input, output, and output enable registers. The input register
can be used for external data requiring fast setup times. The output
register can be used for data requiring fast clock-to-output performance.
The output enable (OE) register can be used for fast clock-to-output enable
timing. The Quartus II software automatically duplicates a single OE
register that controls multiple output or bidirectional pins.
For normal bidirectional operation, the input register can have its own
clock input se parate fr om the OE a nd output register s. The OE and outp ut
regis te r sha r e th e s am e clock so ur ce. Ea ch reg i ste r ca n ha ve its own clock
enable signal from local interconnect in the associated LAB, fast global
signa ls, or row gl obal sign al s.
48 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
The Mercury IOE includes programmable delays that can be activated to
ensure zero hold times, minimum clock-to-output times, input IOE
regist er-to-c ore regis ter tran sfers, or cor e-to-ou tput IOE re gister tr ansfers .
A path in which a pin directly drives a register may require the delay to
ensure zero hold time, whereas a path in which a pin drives a register
through combinatorial logic may not require the delay. Programmable
delays e xist for decr easing inp ut pin to c ore and IOE in put register d elays.
The Quartus II Compiler can program these delays automatically to
minimize setup time while providing a zero hold time. Delays are also
program mable for increa sing the registe r to pin de lays for o utput and/ or
output enable registers. A programmable delay exists for increasing the
tZX delay to the out put pin, which is required for ZBT interfac es. Table 10
shows the programmable delays for Mercury devices.
Note to Table 10:
(1) This delay has four settings: off and three levels of delay.
The IOE registers in Mercury devices share the same source for clear or
preset. Use of the preset/clear is programmable for each individual IOE.
The register(s) can be programmed to power up high or low after
configuration is complete. If programmed to power up low, an
asynchro n ous clear can contro l the re gi ster(s). If programmed to power
up high, an asynchronous preset can control the register(s). This feature
prevents the inadvertent activation of another device’s active-low input
upon power-up. Figure 26 shows the IOE for Mercur y devi ces .
Tab l e 10. Merc ur y Pr o gr a mma bl e De l ay Chai n
Programma ble Delays Quar tus II Logic Optio n
Input pin to core delay (1) Decr eas e input delay to inte rnal c ells
Input pin to inp ut reg is ter delay Decr eas e input delay to input regis t er
Output propagation delay Increas e delay to outp ut pin
Output enable regist er tCO delay I ncrease delay to OE pin
Output t ZX del ay I ncr ea s e tZX delay to output pin
Altera Corporation 49
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Figur e 26. Mercury I OE
Note to Figure 26:
(1) This p rogrammable delay has four settings: off and three levels of delay.
Double Data Rat e I/O
Merc ur y devic e’ s h ave th re e reg ister IO Es to supp or t t he DDRIO fe at ur e,
whic h makes do uble data rat e interfac es possible by cl ocking data on both
positive and negative clock edges. The IOE in Mercury devices supports
double data rate input and dou bl e da ta rat e ou tput modes.
CLRN/PRN
DQ
ENA
Chip-Wide Reset
OE Register
CLRN/PRN
DQ
ENA
CLRN/PRN
DQ
ENA
Output Register
Input Register
Output tZX
Delay
OE Register
tCO Delay
Output
Propagation Delay
Input Pin to
Core Delay
(1)
Drive Strength Control
Open-Drain Output
Slew Control
Input Pin to Input
Register Delay
VCCIO
VCCIO
Optional
PCI Clamp
Programmable
Pull-Up
Priority Row Interconnect (for Associated LAB Row)
Row Interconnect (for Associated LAB Row)
C
olumn and
Priority
Column
I
nterconnect
Associated LAB
Local Interconnect
Two Row
Local Fast
Signals
Six Fast
Global
Signals
Four
Dedicated
Clocks
Bus-Hold
Circuit
50 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
In Mercury device IOEs, the OE register is a multi-purpose register
available as a second input or output register. When using the IOE for
double data rate inputs, the input register and OE register are
automati cally config ured as inp ut regist ers to c lock input double ra te data
on alternating edges. An input latch is also used within the IOE for DDR
input a cquisit ion. Th e latch h olds t he data that is prese nt dur ing the clock
high times, driving it to the OE register. This allows the OE register and
input r egister to clock both bits of data into LEs , synchron ous to t he same
clock edge (either rising or falling). Figure 27 show s an IO E config ured for
DDR input.
Figure 27. IOE Configured for DDR Input
CLRN/PRN
DQ
ENA
Chip-Wide Reset
OE Register
CLRN/PRN
DQ
ENA
PRN
DQ
ENA
Input Register
Input Pin to Input
Register Delay
VCCIO
VCCIO
Optional
PCI Clamp
Programmable
Pull-Up
Priority Row (for Associated LAB Row)
Row (for Associated LAB Row)
Column and
Priority
Column
Associated LAB
Local Interconnect
Two Row
Local Fast
Signals
Six Fast
Global
Signals
Four
Dedicated
Clocks
Bus-Hold
Circuit
Latch
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When using the I OE fo r d oub le dat a ra te ou tput s, the ou tput regis ter and
OE register are automatically configured to clock two data paths from LEs
on rising c lock edg es. T hese r e giste r out put s are mult iple x ed by the c lock
to driv e the outp ut pin at a ×2 rate . T he output re gi ste r clock s the first bit
out on the c lock hig h t ime, w hile t he OE re gis te r clocks the s ec ond b it ou t
on the clock low time. Figure 28 shows the IOE configured for DDR
output.
Figure 28. IOE Configured for DDR Ou tpu t
Bidirectional DDR on an I/O pin is possible by using the IOE for DDR
output and using LEs to acquire the double data rate input. Bidirectional
DDR I/O pins support double data rate synchronous DRAM (DDR
SDRAM) at 16 6 MHz (334 Mbps), which tr ans fer d ata on a do ubl e data
rate bidirectional bus. QDR SRAMs are also supported with DDR I/O
pins on separa te read and write port s.
CLRN/PRN
DQ
ENA
Chip-Wide Reset
OE Register
CLRN/PRN
DQ
ENA
Output Register Output
Propagation Delay
Drive Strength Control
Open-Drain Output
Slew Control
VCCIO
VCCIO
Optional
PCI Clamp
Programmabl
e
Pull-Up
Associated LAB
L
ocal Interconnect
Two Row
Local Fast
Signals
Six Fast
Global
Signals
Four
Dedicated
Clocks
Bus-Hold
Circuit
0
1
52 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Zero Bus Turnaround SRAM Interface Support
In addition to DDR SDRAM support, Mercury device I/O pins also
support int erfacing with ZBT SRAM bloc ks at up to 200 MHz. ZBT SRAM
blocks are designed to eliminate dead bus cycles when turning a
bidi rectiona l bus ar ound between reads and wr ite s, or wr ite s and read s.
ZBT allows for 100% bus util ization because ZBT SRAM can read or write
on every clock cycle.
To avoid bus contention, the output tZX delay ensures that the clock-to-
low-impedance time (tZX) is greater than the clock-to-high-impedance
time (tXZ). Time delay control of clocks to the OE/output and input
regist er, using a s ingle gene ral p urpose PLL, enable the M ercury device to
meet ZBT tCO and tSU times.
Programmab le Driv e St re ngth
The output bu ffer for ea ch Mercury devi ce I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL standard has
several levels of drive strength that can be controlled by the user. SSTL-3
class I an d II, SSTL-2 class I and II, HST L class I and II, and 3.3-V GTL+
support a minimum or maximum setting. The minimum setting is the
lowest drive strength that guarantees the IOH/IOL of the standard. The
maximum setting provides higher drive strength that allows for faster
switching and is the default setting. Using settings below the maximum
provides signal slew-rate control to reduce system noise and signal
overshoot. Table 11 shows the possible settings for the I/O standards with
drive strength control.
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Open-Drain Output
Mercury devices provide an optional open-drain (equivalent to an open-
collector) output for each I/O pin. This open-drain output enables the
device to provide system-level cont rol signals (e.g., interrupt and write
enable signals) that can be asserted by any of several devices.
Slew-Ra te C ontrol
The output buffer for each Mercury device I/O pin has a programmable
output slew rate control that can be configured for low-noise or high-
spe ed performa nce. A faster slew rate provid es high-spe ed transit ions for
high-performance syst ems. However, these fast transitions may introduce
noise transients into the system. A slow slew rate reduces sy stem noise,
but a dds a no mi nal d ela y to r isin g and fal ling e d ges. Each I/O pin has a n
ind ividual slew r ate cont rol, al lowing the designer to specify the slew ra te
on a pin-by-pin basis. The slew rate control affects both the rising and
falling edges.
Table 11. Programmabl e Drive Strength
I/O Stan dard IOH/IOL Current Strength
Setting
LVTTL (3.3 V) 4 mA
8 mA
12 mA
16 mA
24 mA (def ault )
LVTTL (2.5 V) 4 mA
8 mA
12 mA
16 mA (def ault )
LVTTL (1.8 V) 2 mA
4 mA (default)
SSTL- 3 cla ss I and II
SSTL- 2 cla ss I and II
HSTL cla ss I and II
GTL+ (3.3 V)
Minimum
Ma ximum (d efau l t)
54 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Bus Hold
Each Mercury device I/O pin provides an optional bus-hold feature.
When this fea ture is enabled for an I/O pin, the bus-hold cir cuitr y weakl y
holds the signal at its last driven state. By holding the last driven state of
the pin until the next input signal is present, the bus-hold feature
eliminat es th e need t o add exte rnal pu ll-up or pull-down resi stors t o hold
a signal level when the bus is tri-stated. The bus-hold circuitry also pulls
undriven pins away from the input threshold volta ge where noise can
cause unintend e d high-freq ue ncy switc hing . This fea ture ca n be sele cted
individually for each I/O pin. The bus-hold output will drive no hig her
than VCCIO to prevent overdriving signals. If the bus-hold feature is
enabled, the pr ogra mmable pull-up opti on ca nnot be use d . The bus - hold
feature should also be disabled if open-drain outputs are used with the
GTL+ I/O sta nd ar d .
The bus- hold circui try weakly pul ls the signa l level to the last driven st ate
throu gh a resist or w ith a nomi nal r esist ance (RBH) o f approx imately 8 kΩ.
Table 42 giv es s pe cific sus taining current that will be dr ive n th ro ugh thi s
resistor an d overdrive current that will identify the next driven input
level. This information is provided for each VCCIO voltage level.
The bus-hold circuitry is active only after configuration. When going into
user mode, the bus-hold circuit captures the value on the pin present at
the end of configuration.
Programmab le Pu ll-Up Resist or
Each Mercury device I/O pin provides an op tional programmable pull-
up resis tor during us er mode . When this fea ture is e nabled for an I/ O pin,
the pu ll-up resis tor (5 0 k Ω) weak ly holds the out put to the VCCIO level of
the bank that the output pin resides in.
I/O Row Band s
The I/O row bands are one of the advanced features of the Mercury
architecture. All IOEs are grouped in I/O row bands across the device.
The number of I/O row bands depends on the Mercury device size. The
I/O row bands are designed for flip-chip technology, allowing I/O pins
to be distributed across the entire chip, not only in the periphery. This
array driver technology allows higher I/O pin density (I/O pins per
device area) than peripheral I/O pins.
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Each row of I/O pins has an associated LAB row for driving to and from
the core of the Mercury device . For a giv en I/O band ro w, its a ssociated
LAB row is located below it with the exception of the bottom I/O band
row. The bottom I/O band is located at the bottom periphery of the
device , he nce its associated L AB row is loca te d abo ve it. Figure 29 sho ws
an example of an I/O band to associated LAB row interconnect in a
Mercury device.
There is a maximum of two IOEs associated with each LAB in the
ass ocia ted LAB row. The local inte rcon nec t of the associat ed LAB drive s
the IOEs. Since local interconnect is shared with the LAB neighbor, any
given LAB ca n directly drive up to four IOEs. The local interco nnec t
drives the data and OE signals when the IOE is used as an output or
bidir e ctio nal pin.
Figure 29. IOE Connection to Interconnects and Adjacent LAB Note (1)
Note to Figure 29:
(1) INA: unregistered input; INB: reg is t er ed/u n r egister ed input; INC: registered/unregistered input or OE register
output in DDR mode.
The IO Es drive r egistere d or combina torial ver sions of in put data in to the
device . The unr egist ered input data can be driven to the loc al int erconnect
(for fast input se tup), r ow and priorit y row inte rconnec t, and col umn and
priority column interconnects. The registered data can also be driven to
the same row and column resources. The OE register output can be fed
back throug h column a nd row in terc onnect s to im plement DDR I/O p ins.
LAB LAB LAB
I/O Band
Row
Associated
LAB Row
IOE Pair
INA
INC
INBOUT INA
INC
INBOUT
Row Interconnec
t
Priority Row
Interconnect
All Column Interconnects
Associated LAB
to IOE Pair Local Interconnect
IOE pairs drive unregistered
inputs to the associated
LAB's local interconnect.
The associated LAB and its
neighbor can drive a given IOE
pair through the local interconnect.
IOEIOE
IOE Pair
INA
INC
INBOUT INA
INC
INBOUT
IOEIOE
IOE Pair
INA
INC
INBOUT INA
INC
INBOUT
IOEIOE
T
o Local
I
nterconnect To Next
LAB
56 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Dedicated Fast Lines & I/O Pins
Mercury device s incorporat e dedicate d bidir ectional pins for sig nals with
high internal fanout, such as PCI control signals. These pins are called
dedicat ed fa st I/O p ins (FAST1, FAST2, FAST3, FAST4, FAST5, and
FAST6) and can d rive th e six global fa st lin es thr oughout t he devi ce, ide al
for fast clock, clock enable, clear, preset, or high fanout logic signal
distribution. The dedicated fast I/O pins have the same IOE as a reg ular
I/O pin. The dedicated fast l i ne s can also be driven by a LE local
interconnect to generate internal global sig nals.
In addition to the device global fast lines, each LAB row has two dedicated
fast lines local to the row. This is ideal for high fanout control signals for
a section of a design that may fit into a single LAB row. Each I/O band
(with the exception of the top I/O band) has two dedicated row-global
fast I /O pins to drive the ro w-global f ast res ources for the associate d LAB.
The dedi cate d local fa st I/O pins ha ve the sam e IOE as a reg ular I/O pin.
The LE loca l interconnect can drive dedicated row-global fast lines to
generate internal global signals specific to a row. There are no pin
connections for buried LAB rows; LE local interconnects drive th e row-
global signals in those rows.
I/O Standa rd Suppo rt
Mercury device IOEs support the follow ing I/O standards:
■LVTTL
■LVCMOS
■1.8-V
■2.5-V
■3.3-V PCI
■3.3-V PCI-X
■3.3-V AGP (1×, 2×)
■LVDS
■LVPECL
■3.3-V PCML
■GTL+
■HSTL class I and II
■SS T L-3 class I and II
■SS T L-2 class I and II
■CTT
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Table 12 descri be s the I /O sta ndar d s sup por te d by Mercur y devic es.
Each regular I/O band row contains two I/O banks. The number of I/O
banks in a Mer cury device de pends on the numb er of I/O band rows . The
top I/O band contains four regular I/O banks specifically designed for
HSD I. Th e top I/O b and banks and dedi cated c lock inputs sup port LVD S,
LVPECL, and 3.3-V PCML. 3.3-V PCML is an open-drain standard and
therefore requires external termination to 3.3 V. All other standards are
supp orted by all I/ O banks. The top I/O ban ks 1, 2, 3, and 4 only s upport
non-HSDI I/O pins if the design does not use HSDI circuitry. If the design
uses any HS DI channel , banks 1, 2, 3, and 4 all do not sup port regular I/O
pins.
Additionally, the EP1M350 device includes the Flexible-LVDS feature,
provid ing su pport for up to 10 0 LVDS cha nne ls on a ll r e gu lar I/O b a nk s.
Regular I/O bank s in EP1M350 devices inc l ud e dedicated LVDS inpu t
and output buffers that do not require any external components except for
100-Ω termination resistors on receiver channels.
Table 12. Mercury Supported I/O Standards
I/O Standard Type Input
Reference
Voltage (V REF)
(V)
Output
Supply
Voltage
(VCCIO) (V)
Board
Termination
Voltage
(VTT) (V)
LVTTL Single-ended N/A 3.3 N/A
LVCMOS Single-ended N/A 3.3 N/A
2.5 V Single-ended N/A 2.5 N/A
1.8 V Single-ended N/A 1.8 N/A
3.3-V PCI Single-ended N/A 3.3 N/A
3.3-V PCI -X Single-ended N/A 3.3 N/A
LVDS Differential N/A 3.3 N/A
LVPECL Differential N/A 3.3 N/A
3.3-V PCML Differential N/A 3.3 3.3
GTL+ Voltage referenced 1.0 N/A 1.5
HSTL cla ss I and II Voltage refer enc ed 0.75 1.5 0.75
SSTL-2 class I and II Voltage referenced 1.25 2.5 1.25
SSTL-3 class I and II Voltage referenced 1.5 3.3 1.5
AGP Voltage referenced 1.32 3.3 N/A
CTT Voltage referenced 1.5 3.3 1.5
58 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
For the H S DI I /O band , ha lf of the d edica te d bank s support LVDS, 3. 3- V
PCML or LVPECL, and rece ive r inputs, whi le the other half supp ort
LVDS, PCML or LVPECL, and transmitter outputs. A single device can
suppor t 1.5-V, 1.8-V, 2.5-V , and 3.3-V inte r f ace s; each ba nk ca n support a
VCCIO standard independently. Each bank can also use a separate VREF
level so that each bank c an sup port any of the te rmina ted standar ds (such
as SSTL-3) independently. A bank can support a single VREF level. Each
bank con tai ns a fix ed VREF p in for vol tage r efere nced standa rds. This p in
can be used as a regular I/O if a VREF stand ard is n ot used. Table 13 shows
th e number of I/O banks i n each Merc ury devi ce.
Each bank can support multiple standards with the same VCCIO for output
pins. For EP1M120 devices, each bank can support one voltage-referenced
I/O standard, but can support multiple I/O stand ards with the same
VCCIO and VREF voltage levels. For example, when VCCIO is 3.3 V, a bank
can supp o rt LVTTL, LVCMOS, 3. 3-V P CI, and SSTL-3 for input s and
outputs. Figure 30 shows the I /O bank layou t for an EP1M1 20 device. For
EP1M350 devices, each bank can support two voltage-reverenced I/O
standards; each I/O bank is split into two voltage-referenced sub-banks.
When using the two HSDI transmitter banks as regular I/O banks in a
non-HSDI mode, those two banks require the same VCCIO level. However,
each HSDI transmitter bank supports its own V REF level.
Table 13 . Numbe r of I/O Banks per Devic e
Device Regular I/O Banks HSDI Band I/O Bank s
EP1M120 8 4
EP1M350 12 4
Altera Corporation 59
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Figure 30. I/O Bank La you t
Notes to Figure 30:
(1) If HSDI I/O channels are not used, the HSDI banks can be used as regular I/O banks.
(2) When used as regular I/O banks, these banks must be set to the same VCCIO leve l, but c an h ave sep arat e V REF bank
settings.
fFor more informati o n on I/O standards, se e App lication Note 11 7 (U s ing
Selectable I/O Standards in Altera Devic e s).
MultiVol t I/O Interfac e
The Mercury archite cture supports the MultiVolt I/O interface feature,
which allows Mercury devices in all packages to interface with devices
with different supply voltages. The devices have one set of VCC pins for
internal operation and input buffers (VCCINT), and another set for I/O
output drivers (VCCIO).
Input, Output, or HSDI Transmitter
(1), (2)
Input, Output, or HSDI Receiver
(1)
Input, Output, or HSDI Transmitter
(1), (2)
Input, Output, or HSDI Receiver
(1)
I/O Bank
ESB ESB ESB ESB ESB ESB
ESB ESB ESB ESB ESB ESB
I/O or HSDI
Banks
Regular I/O
Banks
I/O Bank
I/O Bank
I/O Bank
I/O Bank
I/O Bank
I/O Bank
I/O Bank
60 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
The Mercur y VCCINT pins must always be connected to a 1.8-V power
supply. With a 1.8-V VCCINT lev e l, i nput pins ar e 1.8-V, 2.5-V and 3.3 -V
toleran t. The VCCIO pins can be connected to either a 1.5-V, 1.8-V, 2.5-V or
3.3-V power supply, depending on the output requirements. When VCCIO
pi ns are conn e ct ed to a 1.5-V power supply , the out put levels are
compatible with HSTL systems. When VCCIO pins are conn ected to a
1.8-V power supply, the o utput levels are com p atible w ith 1.8-V sy stems.
When VCCIO pins are connected to a 2.5-V power supply, the output
level s are com pat ible with 2. 5-V systems. When the VCCIO pins are
connected to a 3.3-V power supply, the output high is 3.3 V and is
compatible with 3.3-V or 5.0-V systems.
Table 14 summarizes Mercury MultiVolt I/O support.
Notes to Table 14:
(1) The PCI clamping diode must be disabled to drive an input with voltages higher than VCCIO unless an external
resistor is used.
(2) These input levels are only available if the input standard is set to any VREF-based input standard (SSTL-2, SSTL-3,
HSTL , GTL+, AGP 2×). The input buffers are powered from VCCINT when us ing VREF-based input standards.
LVTTL, PCI, PCI-X, AGP 1× input buffers are powered by VCCIO. Ther ef or e, t he se s ta nda rds can no t be driv en wit h
inpu t lev els below the VCCIO setting except for when VCCIO = 3.3 V and the in pu t volt ag e (V I) = 2.5 V.
(3) When VCCIO = 1.8 V, th e M erc u ry dev i c e ca n driv e a 1.5-V dev ice with 1.8-V t ole ra nt in p uts .
(4) When VCCIO = 2.5 V, th e M erc u ry dev i c e ca n driv e a 1.8-V dev ice with 2.5-V t ole ra nt in p uts .
(5) When VCCIO = 3.3 V, th e M erc u ry dev i c e ca n driv e a 2.5-V dev ice with 3.3-V t ole ra nt in p uts .
(6) Designers can set Mercury devices to be 5.0-V tolerant by adding an external resistor and enabling the PCI clamping
diode.
Power Sequencing & Hot-Socketing
Because Mercury devices can be used in a m ixed -vo ltage envi r onm ent,
the devices are designed specifically to tolerate any possible power-up
sequen ce. Therefor e, the VCCIO and VCCINT power supplies may be
powered in any order.
Signals can be driven i nto Mercury devi ces before an d du ri ng power-up
without damaging the device. In ad dition, Mercury devices do not drive
out during power-up. Once operating conditions are reached a nd the
device is configured, Mercury devices operate as specified by the user.
Table 14. Mercury MultiVolt I/O Support Note (1)
VCCIO
(V) Inpu t Si g nal Ou tp ut Signal
1.5 V 1.8 V 2 .5 V 3.3 V 5 .0 V 1.5 V 1 .8 V 2.5 V 3.3 V 5.0 V
1.5 vvvv v
1.8 v(2) vvv v(3)
2.5 v(2) v(2) vv v(4) v
3.3 v(2) v(2) v(2) vv(6) v(5) vv
Altera Corporation 61
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General
Purpose PLL
Mercury devices have ClockLockTM, ClockBoostTM, and advanced
ClockShiftTM features, which use up to four general-purpose PLLs
(separate from the two HSDI PLLs) to province clock management and
clock -frequen cy synth esis. EP1 M120 dev ices conta in two gen eral purpo se
PLLs; EP1M35 0 devices contain four general purpose PLLs. These P LLs
allow designers to increase performance and provide clock-frequency
synthesis. The PLL reduces the clock delay within a device. This reduction
minimizes clock-to-output and setup times while maintaining zero hold
times. The PLLs, which provide programmable multiplication, allow the
designer to distribute a low-speed clock and multiply that clock on-
device. Mercury devices include a high-speed clock tree: unlike ASICs, the
user does not have to design and optimize the clock tree. The PLLs work
in conjunction with the Mercury device’s high-speed clock to provide
significant improvements in system performance and bandwidth.
Table 15 shows the general purpose PLL features for Mercury devices.
Figure 31 shows a Mercury PLL.
Note to Table 15:
(1) n represents the prescale divider for the PLL input. k, p, q, and v re pr esen t the d ifferen t post scale divid ers f or the
four possible PLL outputs. m, k, p, and q are integ er s t ha t ran g e fr om 1 t o 160. n an d v are integers that ca n range
from 1 to 16.
Figure 31. Mercury G eneral-Purpos e PLL
Table 1 5. M ercur y General Purpose PL L Fea t ures
De vice Num ber of P LLs ClockBoost
Feature (1) Number of External
Clock Outputs Number of
Feed ba ck In puts Advanced
ClockShift
EP1M120 2 m/(n × k, p, q, v) 2 2 v
EP1M350 4 m/(n × k, p, q, v)4 4 v
m
n
kTime
Delay/Shift
Time
Delay/Shift
Time
Delay/Shift
Time
Delay/Shift
p
q
v
Phase
Comparator Voltage-Controlled
Oscillator
i
nclock
fbin
clock1
clock0
clock2
clock_e
xt
ClockLock
Phase Shift
Circuitry
62 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
The PLLs in Mercury devices are enabled through the Quartus II software.
External devices are not required to use these features.
Advanc ed C loc k Bo ost Mul tipl ic ation & Divisi on
Each M ercur y PL L inc l udes circuitry th at pr ovides clock synthesis for up
to four outputs (three internal outputs and one external output) using
m/(n × output divider) scaling. When a PLL is locked, the locked output
clock aligns to the rising e dge of the i nput cl ock. The close d loop e quation
for Figure 31 gives an output frequency fclock0 =(m/(n × k))fIN,
fclock1 =(m/(n × p))fIN, fclock2 =(m/(n × q))fIN, a n d
fclock_ext =(m/(n×v))fIN or fclock1. These equations allow the
multiplication or division of clocks by a programmable number. The
Quartus II software automa tically ch ooses th e appropria te scaling factors
according to the frequency, multiplication, and division values entered.
A single PLL in a Mercury device allows for multiple use r-defined
multiplica tion and division r atios that are not possible eve n with multipl e
delay-locked loops (DLLs). For example, if a frequency scaling factor of
3.75 is needed for a given input clock, a multiplica tion factor of 15 and a
division factor of 4 can be entered. This advanced multiplication scaling
can be performed with a single PLL, mak ing it unnecessary to cascade
PLL out puts.
Exte rn al C loc k Output s
Mercury devices have four low-jitter external clocks available for external
clock sources. Other devices on the board can use these outputs as clock
sources.
There are three modes for external clock outputs. Multiplication is
allowed in all external clock output modes.
■Zero Delay Buffer: The external clock output pin is phase aligned
with the clock input pin for zero dela y. Programmable pha se shift
and time delay shift are not allowed in this configuration.
Multiplication is allowed with the zero delay buffer mode. The
MegaWizard in terface for altclklock should be used to verify
possible clock settings.
■Ex tern al Feedback: The ex ternal fe edback in put pin is phase aligned
with cloc k input pin. By aligning these clocks, you can actively
remove clock delay and skew between devices. Multiplication is
allowed with the external feedback mode. This mode has the same
restrictions as zero delay buffer mode.
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■Normal Mode: The external clock output pin will have phase delay
relative to the clock input pin. If an internal clock is used in this mode,
the IOE register clock will be phase aligned to the input clock pin.
Multiplication is allowed with the normal mode.
Advanc ed Cloc k S hift C ircuitry
General purpose PLLs in Mercury devices have advanced ClockShiftTM
circuitry that provides programmable phase shift and fine tune time delay
shift. For phase shifting, users can enter a phase shift (in degree s or time
units) that affects all PLL outputs. Phase shifts of 90, 180, and 270 can be
implemented exactly. Other values of pha se shifting, or delay shifting in
time units, are allowed with a resolution range of 0.3 ns to 1.0 ns. This
resolution varies with frequency input and the user-entered
multipl ication and di vision factors. The phase shift a bility is only pos sible
on a multiplied or divided clock if the input and output frequency have
an integer multiple relation ship (i.e., fIN/fOUT or fOUT/fIN must be an
integer).
In addition to the phase shift feature that affects all outputs, there is an
advanced fine time delay shift control on each of the four PLL outputs.
Each P LL ou tput ca n be shif ted i n 250-p s incr ements for a rang e of –2 .0 ns
to +2.0 ns. This ability ca n be used in conjunction with the phase shiftin g
ability that affects all outputs. fIN/fOUT does not ne ed to have an integer
relationship for the advanced fine time delay shift control.
Clock Enable S ignal
Merc ury PLLs have a CLKLK_ENA pin for enabling/disabling all of the
device PLLs. When the CLKLK_ENA pin is high, the PLL drive s a clock to
all its output ports. When the CLKLK_ENA pin is low, the clock0,
clock1, clock2 and extclock ports are driven by GND and all of the
PLLs go out of lock. When the CLKLK_ENA pin g oes high again, the PL L
must relock.
The individ ual enable port for each gene ral purpose PLL is
programmable. If more than one general-purpose PLL is instantiated,
each one does not have to use the clock enable. To enable/disable the
device PLLs with the CLKLK_ENA pin, the inclocken port on the
altclklock instance must be connected to the CLKLK_ENA input pin.
64 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Lock Signals
The Mercury device general purpose PLL circuits s upport individual
LOCK sig nals. Th e LOCK signal dri ves high when the PLL has locke d onto
the input clock. Lock remains high as long as the input remains within
specifi cation. I t w ill go low if t he inp ut is out of specification . A LOCK pin
is optiona l for each PL L used in the M ercur y devices ; when not used, they
are I/O pin s. Th is signal is not a vailable interna lly; if it i s used i n the core,
it must be fed back in with an input pin.
SignalTap
Embedded
Logic Analyzer
Mercury devices include device enhancements to support the SignalTap
embedde d log ic a na lyz er. B y including this circuitry, t he M ercury d e vice
provides the ability to monitor design operation over a period of time
thro ug h the IEEE Std. 11 49.1 JTAG circ uitry; a des i gner can analyze
interna l logic at spe ed without bringin g inte r nal signa ls to the I/O pins .
This feature is particularly important for advanced packages such as
FineL in e B GA packag es, b ec aus e it can be d if ficult to add a connection to
a pin du ri ng the debuggi ng proc es s a f ter a board is de signed and
manufactured.
IEEE Std.
1149.1 (J TAG)
Boundar y-Scan
Support
All Mercury devices provide JTAG BST circuitry that complies with the
IEEE Std. 1149.1-1990 sp ecification. JTAG bou ndary-scan testing can be
performed before or after configuration, but not during configuration.
Mercury devices can also use the JTAG port for configuration with the
Quart us II softwa re or wi th har dware using eithe r Jam St anda rd Test a nd
Programming Language (STAPL) Files (.jam) or Jam STAPL Byte-Code
Files (.jbc). Mercury devices also use the JTAG port to monitor the logic
operation of the device with the SignalTap embedded logic analyzer.
Mercury devices support the JTAG instructions shown in Table 16.
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The Mercury device instruction register length is 10 bits. The Mercury
device USERCODE register length is 32 bits. Tables 17 and 18 show the
boundary-scan register length and device IDCODE i n for m ati o n for
Mercury devices.
Notes to Table 18:
(1) The most si gni fic a n t bit (MSB) is o n the le f t .
(2) Th e ID CODE ’ s least sig n ifi c an t bit (L SB) is alwa ys 1.
Table 16. Mercury JTAG Instructions
JTA G Inst ruc t io n Des cri pt ion
SAMP LE/ PR ELOAD Allows a sn aps hot of signa ls at the dev ice pins to be capt ured and exam ined during
normal device operation and permits an initial data pattern to be output at the device pins.
Also used by th e SignalTap em bedded logic analyzer.
EXTEST Allows the external circuitry and board-level interconnections to be tested by forcing a test
pattern at the output pins and capturing test results at the input pins.
BYPASS Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data
to pass synchronously through selected devices to adjacent devices during normal device
operation.
USERC OD E Selects the 32-bit US ER CO D E regis t er and places it between the TDI and TDO pins ,
allowi ng th e USE R CO D E to be serially shifte d out of TDO.
IDCO DE Selects the IDCO D E regis t er and places it between TDI and TDO, allowing the IDCODE
to be serially shi fted out of TDO.
ICR Instruc t ions These ins tru ctions are used when configu ring a Me rcu ry device vi a the JTA G port with a
ByteBlasterMVTM downlo ad c able, or us ing a Ja m STAP L or Ja m Byt e-C ode file via an
embedded processor.
SignalTap
Instructions T hes e ins tr uc tio ns moni tor inter nal dev ic e operation wi th the SignalTap em bedded logic
analyzer.
Table 17. Mercury Boundary-Sca n Register Length
Device Boundary-Scan Register Length (Bits)
EP1M120 1,125
EP1M350 1,695
Table 18. 32-Bit Mercury Device IDCODE
De vice IDCODE (32 B its) (1)
Version
(4 Bits) Part Numbe r (16 Bits) Manufacturer Identity
(11 Bits) 1 (1 Bit) (2)
EP1M120 0000 0011 0000 0000 0000 000 0110 1110 1
EP1M350 0000 0011 0000 0000 0001 000 0110 1110 1
66 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Figure 32 shows the timing requir ements for the JTAG sig nals.
Figure 32. Mercury JTAG Waveforms
Table 19 shows the JTAG timin g p ara meters and value s for Mercury
devices.
Table 19. Me rcury JTAG Timin g Par amete rs & Va lues
Symbol Parameter Min Max Unit
tJCP TCK clock period 100 ns
tJCH TCK clo ck high t im e 50 ns
tJCL TCK clock low time 50 n s
tJPSU J T AG port se tu p time 20 ns
tJPH JTAG port hold time 45 ns
tJPCO J T AG port clo ck to outp ut 25 ns
tJPZX J T AG port high impedanc e t o val id out put 25 ns
tJPXZ J T AG port va lid out put to hig h im pedance 25 ns
tJSSU Capture register setup time 20 ns
tJSH Capture register hold time 45 ns
tJSCO Update register clock to output 35 ns
tJSZX Update register high impedance to valid output 35 ns
tJSXZ Update register valid output to high impedance 35 ns
TDO
TCK
tJPZX tJPCO
tJPH
tJPXZ
tJCP tJPSU
tJCL
tJCH
TDI
TMS
Signal
to Be
Captured
Signal
to Be
Driven
tJSZX
tJSSU tJSH
tJSCO tJSXZ
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fFor more information, see the following documents:
■Application Note 39 (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in
Altera Devices)
■Jam Programming & Test Language Specification
Generic Testing Each Mercury device is functionally tested. Complete testing of each
configurable static random access memory (SRAM) bit and all logic
functionality ensures 100% yield. AC test measurements for Mercury
devices are made under conditions equivalent to those shown in
Figure 33. Multiple test patterns can be used to configure devices during
all stages of the production flow .
68 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Fig ure 33. Merc ury AC Test Co nd it ions
Operating
Conditions
Table 20 through 43 provide information on absolute maximum ratings,
recommended operating conditions, DC operating conditions, and
capacitance for 1.8 -V M erc ury devices.
Syste
m
C1 (includes
jig capacitance)
Device input
rise and fall
times < 3 ns
D
evice
O
utput To Te
st
Power supply transients can affect AC
measurements. Simultaneous transitions
of multi ple outputs should be avoided for
accurate measurement. Threshold tests
must not be performed under AC
conditions. Large-amplitude, fast-ground-
current transients normally occur as the
device outputs discharge the load
capa citanc es. When these tra nsients flow
throu gh the parasitic in ductance between
the device ground pin and the test system
groun d, signif icant red uctions in
observable noise immunity can result.
Tabl e 20. M ercur y Devic e Absolute M aximu m R ati ngs Note (1)
Symbol Parameter Conditions Minimum Maximum Unit
VCCINT Supply vol tag e With respe ct to gro und (2) –0.5 2.5 V
VCCIO –0.5 4.6 V
VIDC input voltage –0.5 4.6 V
IOUT D C outp ut current, per pin –34 34 mA
TSTG Storage temp erat ure No bias –65 150 ° C
TAMB Ambient temperature Under bias –65 135 ° C
TJJunct ion te mp erat ure BGA packag es un der bias 135 ° C
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Table 21. Mercury Device Recommended Operating Conditions
Symbol Parameter Conditions Minimum Maximum Unit
VCCINT Supply volta ge fo r inte rnal logic
and input buffers (3) 1.71 1.89 V
VCCIO Supply voltage for output buffers,
3.3-V operation (3), (4) 3. 00 (3. 135) 3.60 (3.465) V
Supply voltage for output buffers,
2.5-V operation (3) 2.375 2.625 V
Supply voltage for output buffers,
1.8-V operation (3) 1.71 1.89 V
Supply voltage for output buffers,
1.5-V operation (3) 1.4 1.6 V
VIInput vo lta ge (2), (5) –0.5 4.1 V
VOOutp ut volt age 0 VCCIO V
TJOperating temperature For commercial
use 085° C
For industrial use –40 100 ° C
tRInput rise time 40 ns
tFInput fall time 40 ns
Table 22. Mercury Device DC Operating Co nd itions Note (6), (7)
Symbol Parameter Conditions Minimum Typical Maximum Unit
IIInput pin lea ka ge
current VI = VCCIOmax to 0 V (5) –10 10 µA
IOZ Tri-stat ed I/O pin
leak age c urrent VO = VCCIOmax to 0 V (5) –10 10 µA
ICC0 VCC supply cur rent
(standby) for
EP1M120 devices
For com m erc ial us e (8) 30 mA
For Indus t rial us e (8) 40 mA
VCC su pply cur rent
(standby) for
EP1M350 devices
For com m erc ial us e (8) 50 mA
For Indus t rial us e (8) 60 mA
RCONF Value of I/O pin pull-
up resistor before
and during
configuration
VCCIO = 3.0 V (9) 20 50 kΩ
VCCIO = 2.375 V (9) 30 80 kΩ
VCCIO = 1.71 V (9) 60 150 kΩ
70 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Table 23 . LVTTL Specific ations Note (10)
Symbol Parameter Conditions Minimum Maximum Units
VCCIO Outpu t supply vo lta ge 3 .0 3.6 V
VIH High-level input voltage 1.7 4.1 V
VIL Low-level input voltage –0.5 0.7 V
IIInput pin leak age current VIN = 0 V or VCCIO –10 10 µA
VOH High-level output voltage IOH = –4 mA 2.4 V
VOL Low-level output voltage IOL = 4 mA 0.45 V
Table 24 . LVCMOS Spec i fications
Symbol Parameter Conditions Minimum Maximum Units
VCCIO Power supply voltage range 3.0 3.6 V
VIH High-level input voltage 1.7 4.1 V
VIL Low-level input voltage –0.5 0.7 V
IIInput pin leak age current VIN = 0 V or VCCIO –10 10 µA
VOH High-level output voltage VCCIO = 3.0,
IOH = –0.1 mA VCCIO – 0.2 V
VOL Low-level output voltage VCCIO = 3. 0,
IOL = 0.1 mA 0.2 V
Table 25. 2.5-V I/O Sp ecifications Note (10)
Symbol Parameter Conditions Minimum Maximum Units
VCCIO Outpu t supply vo lta ge 2.37 5 2.6 25 V
VIH High-level input voltage 1.7 4.1 V
VIL Low-level input voltage –0.5 0.7 V
IIInput pin leak age current VIN = 0 V or VCCIO 10 10 µA
VOH High-level output voltage IOH = –0.1 mA 2 .1 V
IOH = –1 mA 2.0 V
IOH = –2 mA 1.7 V
VOL Low-level output voltage IOL = 0.1 m A 0.2 V
IOH = 1 mA 0.4 V
IOH = 2 mA 0.7 V
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Figures 34 and 35 show receiver inp ut and trans mitter outpu t waveforms,
respective ly, for al l differen tial I/O standards (LV P ECL, 3.3-V PCML,
LVDS, and Hype rTransport te chn ology).
Figure 34. Receiver Input Waveforms for Differential I/O Standards
Table 26. 1.8-V I/O Specifications Note (10)
Symbol Parameter Conditions Minimum Maximum Units
VCCIO Output supply voltage 1.71 1.89 V
VIH High -lev el input voltage 0.6 5 × VCCIO 4.1 V
VIL Low -lev el input voltage –0.5 0. 35 × VCCIO V
IIInput pin leaka ge c urrent VIN = 0 V or VCCIO –10 10 µA
VOH High -lev el out put vo lta ge IOH = –2 mA V CCIO – 0.45 V
VOL Low -lev el out put vo lta ge IOL = 2 mA 0.45 V
Single-Ended Waveform
Differential W aveform
Positive Channel (p) = VIH
Negative Channel (n) = VIL
Ground
±VID
+VID
− VID
VID (Peak-to-Peak)
VCM
p − n = 0 V
72 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Figure 35. Transmi tter Ou tput Waveforms for Differenti al I/O Standards
Single-Ended Waveform
Differential W aveform
Positive Channel (p) = VOH
Negative Channel (n) = VOL
Ground
±VOD
+VOD
− VOD
VOD (Peak-to-Peak)
p − n = 0 V
VCM
Table 27. 3.3-V LVDS I / O Specification s
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supp ly volt age 3.13 5 3.3 3.465 V
VOD Differe nt ial out put vol tag e RL = 100 Ω250 510 600 mV
∆ VOD Change in VOD bet w een
high and low RL = 100 Ω50 mV
VOS Outpu t offset vo lta ge RL = 100 Ω1.125 1.25 1.375 V
∆ VOS Change in VOS bet w een
high and low RL = 100 Ω50 mV
VTH Differe nt ial input th res hold V CM = 1.2 V –100 100 mV
VIN Receiv er input voltage
range 0.0 2.4 V
RLReceiv er dif fe rent ial input
resistor (external to
Mercury dev ic es )
90 100 110 Ω
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Table 28. 3.3-V PCML Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I / O sup ply voltage 3.135 3.3 3 .4 65 V
VIL Low -lev el input voltage VCCIO –
0.4 V
VIH High -lev el input voltage VCCIO V
VOL Low -lev el out put vo lta ge VCCIO –
0.4 V
VOH High -lev el out put vo lta ge VCCIO V
VTOutput termination voltage VCCIO V
VID Diffe rent ial input voltage 400 800 mV
VOD Diffe rent ial output volt age 400 700 8 00 mV
tRRise ti me (20 to 80%) 200 ps
tFFall time (20 to 80%) 200 ps
tDSKEW Dif fe rent ial s ke w 25 ps
R1 (11) Output load 90 100 110 Ω
R2 (11) Receiver dif f erential input
resistor 45 50 55 Ω
Table 29. LVPECL Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I / O sup ply voltage 3.135 3.3 3 .4 65 V
VIL Low -lev el input voltage 0 2,0 00 mV
VIH High -lev el input voltage 400 2,470 mV
VOL Low -lev el out put vo lta ge 1,400 1,6 50 mV
VOH High -lev el out put vo lta ge 2,275 2,4 70 mV
VID Diffe rent ial input voltage 400 600 1 ,2 00 mV
VOD Diffe rent ial output volt age 525 1, 050 1,200 mV
tRRise ti me (20 to 80%) 85 325 ps
tFFall time (20 to 80%) 85 325 ps
tDSKEW Dif fe rent ial s ke w 25 ps
RLReceiv er dif f erential input
resistor 100 Ω
74 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Table 30. 3.3-V PCI Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supp ly volt age 3.0 3.3 3.6 V
VIH High-level input voltage 0.5 ×
VCCIO
VCCIO +
0.5 V
VIL Low-level input voltage –0.5 0.3 ×
VCCIO
V
IIInput pin leak age current 0 < VIN < VCCIO –10 10 µA
VOH High-level output voltage IOUT = –500 µA0.9 ×
VCCIO
V
VOL Low-level output voltage IOUT = 1,500 µA0.1 ×
VCCIO
V
Table 31. PCI-X Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supp ly volt age 3.0 3.6 V
VIH High-level input voltage 0.5 ×
VCCIO
VCCIO +
0.5 V
VIL Low-level input voltage –0.5 0.35 ×
VCCIO
V
VIPU Input pull-up voltag e 0.7 ×
VCCIO
V
IIL Input leakage current 0 < VIN < VCCIO –10 10 µA
VOH High-level output voltage IOUT = –500 µA0.9 ×
VCCIO
V
VOL Low-level output voltage IOUT = 1,500 µA0.1 ×
VCCIO
V
LPIN Pin induc tance 15 nH
Table 32. GTL+ I/O Specific ations Note (10)
Symbol Parameter Conditions Minimum Typical Maximum Units
VTT Termination voltage 1.35 1.5 1.65 V
VREF Referenc e v olt age 0.88 1.0 1.12 V
VIH High-level input voltage VREF + 0.1 V
VIL Low-level input voltage VREF – 0. 1 V
VOL Low-level output voltage IOL = 34 mA 0.65 V
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Table 33. SSTL-2 Class I Specifications Note (10)
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supply voltage 2.375 2.5 2.625 V
VTT Termination vo ltage VREF – 0.04 VREF VREF + 0.04 V
VREF Reference voltage 1.15 1.25 1.35 V
VIH High -lev el input voltage VREF + 0.18 3. 0 V
VIL Low -lev el input voltage –0.3 VREF – 0.1 8 V
VOH High -lev el out put vo lta ge IOH = –7.6 m A VTT + 0.57 V
VOL Low -lev el out put vo lta ge IOL = 7. 6 mA VTT – 0.57 V
Table 3 4. SSTL- 2 Class II Spe cificat ions Note (10)
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supply voltage 2 .3 2.5 2.7 V
VTT Termination vo ltage VREF – 0.04 VREF VREF + 0.04 V
VREF Reference voltage 1.15 1.25 1.35 V
VIH High -lev el input voltage VREF + 0.18 VCCIO + 0.3 V
VIL Low -lev el input voltage –0.3 VREF – 0.1 8 V
VOH High -lev el out put vo lta ge IOH = –15 .2 mA VTT + 0.76 V
VOL Low -lev el out put vo lta ge IOL = 15. 2 m A VTT – 0.76 V
Table 35. SSTL-3 Class I Specifications Note (10)
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supply voltage 3 .0 3.3 3.6 V
VTT Termination vo ltage VREF – 0.05 VREF VREF + 0.05 V
VREF Reference voltage 1.3 1.5 1.7 V
VIH High -lev el input voltage VREF + 0 .2 VCCIO + 0.3 V
VIL Low -lev el input voltage –0.3 VREF – 0.2 V
VOH High -lev el out put vo lta ge IOH = –8 mA VTT + 0. 6 V
VOL Low -lev el out put vo lta ge IOL = 8 m A VTT – 0. 6 V
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Mercury Programmable Logic Device Family Data Sheet
Table 36 . SSTL-3 Cla ss II Speci f ications Note (10)
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supp ly volt age 3.0 3.3 3. 6 V
VTT Termination voltage VREF – 0.05 VREF VREF + 0. 05 V
VREF Referenc e v olt age 1.3 1.5 1. 7 V
VIH High-level input voltage VREF + 0.2 VCCIO + 0.3 V
VIL Low-level input voltage –0.3 VREF – 0.2 V
VOH High-level output voltage IOH = –16 mA VTT + 0.8 V
VOL Low-level output voltage IOL = 16 mA VTT – 0.8 V
Table 37 . 3.3-V AGP -2X Specif i cations
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supp ly volt age 3.1 5 3.3 3.45 V
VREF Referenc e v olt age 0. 39 × VCCIO 0.41 × VCCIO V
VIH High-level input voltage
(12) 0.5 × VCCIO VCCIO + 0.5 V
VIL Low-level input voltage
(12) 0.3 × VCCIO V
VOH High-level output voltage IOUT = –20 µA0.9 × VCCIO 3.6 V
VOL Low-level output voltage IOUT = 20 µA0.1 × VCCIO V
IIInput pin leak age current 0 < VIN < VCCIO ±10 µA
Table 38 . 3.3-V AGP -1X Specif i cations
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supp ly volt age 3.1 5 3.3 3.45 V
VIH High-level input voltage
(12) 0.5 × VCCIO VCCIO + 0.5 V
VIL Low-level input voltage
(12) 0.3 × VCCIO V
VOH High-level output voltage IOUT = –20 µA0.9 × VCCIO 3.6 V
VOL Low-level output voltage IOUT = 20 µA0.1 × VCCIO V
IIInput pin leak age current 0 < VIN < VCCIO ±10 µA
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Table 3 9. 1.5-V HSTL Class I Spec ificatio ns Note (10)
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supply voltage 1 .4 1.5 1.6 V
VREF I nput referenc e voltage 0.68 0.75 0.9 V
VTT Termination vo lta ge 0.7 0.75 0.8 V
VIH (DC) D C high-level input vo lta ge VREF + 0.1 V
VIL (DC) DC low-lev el input voltage –0.3 VREF – 0.1 V
VIH (AC) AC high-lev el input voltage VREF + 0.2 V
VIL (AC) AC low-level input voltage VREF – 0. 2 V
VOH High -lev el out put vo lta ge IOH = 8 mA VCCIO – 0.4 V
VOL Low -lev el out put vo lta ge IOH = –8 m A 0.4 V
Table 4 0. 1.5-V HSTL Class II Spec ificatio ns Note (10)
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supply voltage 1 .4 1.5 1.6 V
VREF I nput referenc e voltage 0.68 0.75 0.9 V
VTT Termination vo lta ge 0.7 0.75 0.8 V
VIH (DC) D C high-level input vo lta ge VREF + 0.1 V
VIL (DC) DC low-lev el input voltage –0.3 VREF – 0.1 V
VIH (AC) AC high-lev el input voltage VREF + 0.2 V
VIL (AC) AC low-level input voltage VREF – 0. 2 V
VOH High -lev el out put vo lta ge IOH = 16 mA VCCIO – 0.4 V
VOL Low -lev el out put vo lta ge IOH = –16 mA 0.4 V
Table 41. CTT I/O Spe cifications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supply voltage 3 .0 3.3 3.6 V
VTT/VREF Termination and inp ut
refe renc e v olta ge 1.35 1.5 1.65 V
VIH High -lev el input voltage VREF + 0 .2 V
VIL Low -lev el input voltage VREF – 0. 2 V
IIInput pin leaka ge c urrent 0 < VIN < VCCIO ±10 µA
VOH High -lev el out put vo lta ge IOH = –8 mA VREF + 0.4 V
VOL Low -lev el out put vo lta ge IOL = 8 m A VREF – 0. 4 V
IOOutput leakage current
(whe n out put is hig h Z)GND ð VOUT ð
VCCIO
±10 µA
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Mercury Programmable Logic Device Family Data Sheet
Table 42. Bus H old Parame t ers
Parame ter Conditions VCCIO Leve l Units
1.8 V2.5 V3.3 V
Minimum Maximum Minimum Maximum Minimum Maximum
Low sustaining
current VIN > VIL
(maximum) 30 50 70 µA
High sustaining
current VIN < VIH
(minimum) –30 –50 –70 µA
Low overdrive
current 0 V < VIN <
VCCIO
200 300 500 µA
High overdriv e
current 0 V < VIN <
VCCIO
–200 –300 –500 µA
Table 43. M ercury Devic e Capaci t ance Note (13)
Symbol Parameter Minimum Typical Maximum Unit
CIO I/O pin capa citance 13.5 pF
CCLK I nput capacitance on CLK[4..1] pins 16.9 pF
CRXHSDI In put cap ac ita nc e on HS DI rec eiv er pins 8.0 pF
CTXHSDI In put cap ac ita nc e on HS DI tra ns m itter pins 18.0 pF
CCLKHSDI Input cap ac ita nc e on HS DI cl ock pins 7.5 pF
CFLEXLVDSRX Input capacitance on flexible LVDS receiver
pins 13.4 pF
CFLEXLVDSTX Input capacitance on flexible LVDS
transm itter pins 13.4 pF
Altera Corporation 79
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Notes to Tables 20 – 43.:
(1) See the Opera t i ng Re qui rements for Al t era Devic es Data Sh eet.
(2) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –0.5 V or overshoot to 4 .1 V for input
currents less than 100 mA and periods shorter than 20 ns.
(3) Maximum VCC rise time is 100 ms, and VCC must rise monotonically.
(4) VCCIO maximum and minimum conditions for LVPECL, LVDS, RapidIO, and 3.3-V PCML are shown in
parentheses.
(5) Al l pins, including dedicated inputs, clock, I/O, and JTAG pins, m ay be driven before VCCINT and VCCIO are
powered.
(6) Typical values are for TA = 25° C, VCCINT = 1.8 V, and VCCIO = 1.8 V, 2.5 V, and 3.3 V.
(7) T h ese values are s pecifi ed un d er the M er c u r y D ev i c e Rec omm ended Operat i ng C onditions shown in Table 3 on
page 3.
(8) Input pins are g rounded. In t he test design, i nternal logic do es not toggle. The test design does not use PLL or HSDI
circuitry . All ESBs are in power-down mode.
(9) Pin pu ll-up re s is t ance values wil l lower if an ext er nal so ur c e d rive s th e pin hig h er tha n VCCIO.
(10 ) D rive stren gth is progr ammab le ac c o r d ing to valu es in Table 11 on page 5 3.
(11) For more information on termination, see AN 13 4: Using Prog ram mable I /O Stan d a rds i n M ercur y Dev ices or
AN 159: U sin g H S D I in Sou rce-Syn chrono us M o de in Mercury De vi ce s.
(12) VREF specifi e s t he center point of t he s wit c hing range.
(13) Capacitance is sample-tested only. Capacitance is measured using time-doma in reflections (TDR). Measurement
accuracy is within ±5%.
T i mi ng Model The high-performance multi-level FastTrack Interconnect routing
resour c es en sur e pred ic ta ble perf orm an ce, accur a te simulation, and
accurate timing analysis. The predictable performance o f Mercury devices
offer an advantage over FPGAs, which use a segmented connection
scheme and therefore have unpredictable perf ormanc e.
Figure 36 shows the timin g model for bidir e cti onal IOE pin timing. All
registers are within the IOE.
Figure 36. Synchronous Bidi rectional Pin Ext ernal Ti ming Model
PRN
CLRN
DQ
PRN
CLRN
DQ
PRN
CLRN
DQ
D
edicated
C
lock
Bidirection
al
Pin
Output Register
Input Register
OE Register
tINSUBIDIR
tOUTCOBIDIR
tXZBIDIR
tZXBIDIR
tINHBIDIR
80 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Tables 44 and 45 describe the Me rcury device’s external timin g
parameters.
Notes to Tables 44 and 45:
(1) These timing parameters are sample-tested only.
(2) All timing parameters are either to and/or from pins, i ncluding global clock pins.
Table 44. Mercury External Timing Parameters Notes (1 ), (2)
Symbol Parameter Conditions
tINSU Set up t ime with global clock at IOE reg ister
tINH Ho ld time w it h global clock at IOE regis t er
tOUTCO Clo ck-t o-output delay with global clock at IOE reg is ter C1 = 35 pF
tINSUPLL Set up t ime with PLL clock at IOE input register
tINHPLL Ho ld time w it h PLL c loc k at IOE input regis t er
tOUTCOPLL Clock-t o-output delay with PLL clock at IOE out put regis t er C1 = 35 pF
Tabl e 45. M er cury Ex ternal B idi rect ional Ti ming Parameters Notes (1), (2)
Symbol Parameter Conditions
tINSUBIDIR Setup t ime for bid irec tio nal pins with gobal c loc k at IO E input regis t er
tINHBIDIR Ho ld time f or bidirection al pins with global clock at IOE input regis te r
tOUTCOBIDIR Clock-t o-output delay for bid irec tio nal pins with global c loc k at IOE
output register C1 = 35 pF
tXZBIDIR Sy nc hronous IOE ou tpu t ena ble register to outp ut buffer dis able delay C1 = 35 pF
tZXBIDIR Sy nc hronous IOE outp ut en able register outp ut bu ffer enable dela y C 1 = 35 pF
tINSUBIDIRPLL Setup t ime for bid irec tio nal pins with PLL clock at IOE input regis te r
tINHBIDIRPLL Hold time f or bidirectional pins with PLL clock at IOE input register
tOUTCOBIDIRPLL Clock-to-output delay for bidirectional pins with PLL clock at IOE output
register C 1 = 35 pF
tXZBIDIRPLL Synchronous IOE output enable register to output buffer disable delay
with PLL C1 = 35 pF
tZXBIDIRPLL Sync hronous IOE outp ut enable regis ter output buffer enable dela y
with PLL C1 = 35 pF
Altera Corporation 81
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Tables 46 through 51 show extern al timin g p ara met ers for Mercury
devices.
Tabl e 46. EP1M12 0 Ext e r na l Timi ng Par a met e r s Note (1)
Sym bol -5 Speed Gr ade -6 Sp eed Grade -7 Speed G rade Unit
Min Max Min Max Min Max
tINSU 0.67 0.70 0.73 ns
tINH 0.00 0.00 0.00 ns
tOUTCO 2.00 3.30 2.00 3.32 2.00 3.49 ns
tINSUPLL 0.59 0.64 0.62 ns
tINHPLL 0.00 0.00 0.00 ns
tOUTCOPLL 0.50 2.08 0.50 2.08 0.50 2.15 ns
Table 47. EP1M120 External Bidirectional Timing Parameters Note (1)
Symbol -5 Speed Grade -6 Speed Grade -7 Speed Grade Unit
Min Max Min Max Min Max
tINSUBIDIR 0.67 0.70 0.73 ns
tINHBIDIR 0.00 0.00 0.00 ns
tOUTCOBIDIR 2.00 3.30 2.00 3.32 2.00 3.49 ns
tXZBIDIR 3.52 3.53 3.74 ns
tZXBIDIR (2) 3.52 3.53 3.74 ns
tZXBIDIR (3) 3.72 3.73 3.99 ns
tINSUBIDIRPLL 0.59 0.64 0.62 ns
tINHBIDIRPLL 0.00 0.00 0.00 ns
tOUTCOBIDIRPLL 0.50 2.08 0.50 2.08 0.50 2.15 ns
tXZBIDIRPLL 2.29 2.29 2.39 ns
tZXBIDIRPLL (2) 2.29 2.29 2.39 ns
tZXBIDIRPLL (3) 2.49 2.49 2.64 ns
82 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Table 48. EP1M12 0 External Timing Parameters No te (1)
Symbol -7A Speed G rade -8A Speed Gr ade Unit
Min Max Min Max
tINSU 0.74 0.79 ns
tINH 0.00 0.00 ns
tOUTCO 2.00 3.50 2.00 4.10 ns
tINSUPLL 0.62 0.75 ns
tINHPLL 0.00 0.00 ns
tOUTCOPLL 0.50 2.15 0.50 2.43 ns
Table 49. EP1M120 External Bidirectional Timing Parameters Note (1)
Symbol -7A Speed G rade -8A Speed Gr ade Uni t
Min Max Min Max
tINSUBIDIR 0.74 0.79 ns
tINHBIDIR 0.00 0.00 ns
tOUTCOBIDIR 2.00 3.50 2.00 4.10 ns
tXZBIDIR 3.75 4.30 ns
tZXBIDIR (2) 3.75 4.30 ns
tZXBIDIR (3) 4.00 4.58 ns
tINSUBIDIRPLL 0.62 0.75 ns
tINHBIDIRPLL 0.00 0.00 ns
tOUTCOBIDIRPLL 0.50 2.15 0.50 2.43 ns
tXZBIDIRPLL 2.39 2.67 ns
tZXBIDIRPLL (2) 2.39 2.67 ns
tZXBIDIRPLL (3) 2.64 2.95 ns
Table 50. EP1M35 0 External Timing Parameters No te (1)
Symbol -5 Speed Grade -6 Speed Grade -7 Speed Grade Unit
Min Max Min Max Min Max
tINSU 0.60 0.57 0.71 ns
tINH 0.00 0.00 0.00 ns
tOUTCO 2.00 3.95 2.00 3.97 2.00 4.75 ns
tINSUPLL 0.69 0.70 0.82 ns
tINHPLL 0.00 0.00 0.00 ns
tOUTCOPLL 0.50 2.23 0.50 2.23 0.50 2.69 ns
Altera Corporation 83
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Notes to Tables 46 – 51:
(1) T i ming will vary by I/O pin placem ent. Ther e f or e, use the Qu ar t u s II soft ware t o de t er mine ex ac t I/O tim in g for
eac h p in .
(2) This parameter is measured with the Increase tZX Delay to Output Pi n option set to Off.
(3) This parameter is measured with the Increase tZX Delay to Output Pi n option set to On.
Power
Consumption
Detailed power consumption information for Mercury devices will be
released when available.
Configuration &
Operation
The Mercury architecture supports several configuration schemes. This
section summarizes the device operating modes and available device
config urat ion sche mes.
Operating Modes
The Mer cury architectur e uses SRAM config uration elements t hat require
configuration data to be loaded each time the circuit powers up. The
process of physically loading the SRAM data into the device is called
configuration. During initialization, which occurs immediately after
conf igur at ion, the device r es ets r egisters, enabl es I/O pin s, a nd beg ins to
operate as a logic device. The I/O pins are tri-stated during power-up and
before and during configuration. Together, the configuration and
initialization processes are called command mode; normal device
operation is called user mode.
Table 51. EP1M350 External Bidirectional Timing Parameters Note (1)
Symbol -5 Speed Grade -6 Speed Grade -7 Speed Grade Unit
Min Max Min Max Min Max
tINSUBIDIR 0.60 0.57 0.71 ns
tINHBIDIR 0.00 0.00 0.00 ns
tOUTCOBIDIR 2.00 3.95 2.00 3.97 2.00 4.75 ns
tXZBIDIR 3.90 3.93 4.70 ns
tZXBIDIR (2) 3.90 3.93 4.70 ns
tZXBIDIR (3) 4.10 4.13 4.94 ns
tINSUBIDIRPLL 0.69 0.70 0.82 ns
tINHBIDIRPLL 0.00 0.00 0.00 ns
tOUTCOBIDIRPLL 0.50 2.23 0.50 2.23 0.50 2.69 ns
tXZBIDIRPLL 2.19 2.18 2.63 ns
tZXBIDIRPLL (2) 2.19 2.18 2.63 ns
tZXBIDIRPLL (3) 2.39 2.38 2.87 ns
84 Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Before and during device configurat ion, all I/O pins are pulled to VCCIO
by a built-in weak pull-up resistor.
SRAM configuration ele ments allow Mercury devices to be reconfig ured
in-circuit by loading new configuration data into the device. Real-time
reconfiguration is performed by forcing the device into command mode
with a device pin, loading different configuration data, reinitializing the
device, and resuming user-mode ope r ation. In -field upgrades can b e
performed by distributing new configuration files.
Configuration Schemes
The configuration data for a Mercury device can be loaded with one of five
configuration schemes (see Table 52), chosen on th e basis of the target
application. A configuration device, intelligent controller, or the JTAG
port ca n be us ed to control the c onfigurat ion of a Mercu ry device. When a
configuration device is used, the system can configure automatically at
system power-up.
By connecting the configuration e nable (nCE) and configuration enable
output (nCEO) pins on each device, multiple Mercury devices can be
configure d in any of five configuration schemes.
fFor more information on configuration, see Applica tion Note 116
(Configuring APEX 20K, FLEX 10K & FLEX 6000 Devices).
Device Pin-
Outs
See the Alte r a web site (http://www.altera.com) or the Altera Digital
Library for pin-out information.
Table 52. Data Sources for C onfiguration
Configuration Scheme Dat a Source
Configuration device Configuration device
Passi ve serial ( PS) Master Bla sterTM or ByteBlasterMVTM downlo ad c able
or seri al dat a so urc e
Passive parallel asynchronous (PPA) Parallel data source
Passi ve parall el syn ch r o nou s ( PPS ) Para l l el data so urce
JTAG MasterBlaster or ByteBlasterMV download cable or a
microproces so r with a Ja m STAP L or JB C file
Altera Corporation 85
Mercury Pr o grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
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Revision
History
The information cont ained in the Mercury Programmable Logic Device
Fami ly Data Shee t version 2.2 supersedes information published in
previous versions.
Version 2.2
The follow ing changes were made to the Mercury Programmable L ogic
Device Family Data Sh eet version 2 .2:
■Updated the condition values (symbols II and IOZ) in Table 22.
Version 2.1
The follow ing changes were made to the Mercury Programmable L ogic
Device Family Data Sh eet version 2 .1:
■Updated Table 8.
■Upda te d EP1M3 50 r eg ular I/O bank s in Table 13.
■Updated Note (6) in Table 14.
Version 2.0
The follow ing changes were made to the Mercury Programmable L ogic
Device Family Data Sh eet version 2 .0:
■Change d all references to PCML to 3.3 -V PCM L.
■Updated Table 4.
■Updated “High-Speed Differential Interface” on page 8.
■Added Tables 6 through 8.
■Added Figures 34 and 35.
■Updated I/O specifications in Tables 28 and 29.
■Updated Mercury device capacitance in Table 43.
■Updated EP1M120 device timing in Tables 46 through 49.
■Added EP1M350 device timing in Tables 50 and 51.
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