PIC32MX1XX/2XX 32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog Operating Conditions Timers/Output Compare/Input Capture * 2.3V to 3.6V, -40C to +105C, DC to 40 MHz * Five General Purpose Timers: - Five 16-bit and up to two 32-bit Timers/Counters * Five Output Compare (OC) modules * Five Input Capture (IC) modules * Peripheral Pin Select (PPS) to allow function remap * Real-Time Clock and Calendar (RTCC) module Core: 40 MHz MIPS32(R) M4K(R) * * * * MIPS16e(R) mode for up to 40% smaller code size 1.56 DMIPS/MHz (Dhrystone 2.1) performance Code-efficient (C and Assembly) architecture Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply Communication Interfaces Clock Management * * * * * * USB 2.0-compliant Full-speed OTG controller * Two UART modules (10 Mbps) - Supports LIN 2.0 protocols and IrDA(R) support * Two 4-wire SPI modules (20 Mbps) * Two I2C modules (up to 1 Mbaud) with SMBus support * Peripheral Pin Select (PPS) to allow function remap * Parallel Master Port (PMP) 0.9% internal oscillator Programmable PLLs and oscillator clock sources Fail-Safe Clock Monitor (FSCM) Independent Watchdog Timer Fast wake-up and start-up Power Management * * * * Low-power management modes (Sleep, Idle) Integrated Power-on Reset and Brown-out Reset 0.5 mA/MHz dynamic current (typical) 20 A IPD current (typical) Direct Memory Access (DMA) * Four channels of hardware DMA with automatic data size detection * Two additional channels dedicated for USB * Programmable Cyclic Redundancy Check (CRC) Audio Interface Features * Data communication: I2S, LJ, RJ, DSP modes * Control interface: SPI and I2CTM * Master clock: - Generation of fractional clock frequencies - Can be synchronized with USB clock - Can be tuned in run-time Input/Output * * * * 15 mA source/sink on all I/O pins 5V-tolerant pins Selectable open drain, pull-ups, and pull-downs External interrupts on all I/O pins Qualification and Class B Support Advanced Analog Features * ADC Module: - 10-bit 1.1 Msps rate with one S&H - Up to 10 analog inputs on 28-pin devices and 13 analog inputs on 44-pin devices * Flexible and independent ADC trigger sources * Charge Time Measurement Unit (CTMU): - Supports mTouchTM capacitive touch sensing - Provides high-resolution time measurement (1 ns) - On-chip temperature measurement capability * Comparators: - Up to three Analog Comparator modules - Programmable references with 32 voltage points * AEC-Q100 REVG (Grade 2 -40C to +105C) planned * Class B Safety Library, IEC 60730 Debugger Development Support * * * * In-circuit and in-application programming 4-wire MIPS(R) Enhanced JTAG interface Unlimited program and six complex data breakpoints IEEE 1149.2-compatible (JTAG) boundary scan Packages Type SOIC SSOP SPDIP QFN VTLA TQFP Pin Count 28 28 28 28 44 36 44 I/O Pins (up to) 21 21 21 21 34 25 34 34 Contact/Lead Pitch 1.27 0.65 0.100'' 0.65 0.65 0.50 0.50 0.80 Dimensions 17.90x7.50x2.65 10.2x5.3x2 1.365x.285x.135'' 6x6x0.9 8x8x0.9 5x5x0.9 6x6x0.9 10x10x1 Note: 44 All dimensions are in millimeters (mm) unless specified. (c) 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 1 PIC32MX1XX/2XX TABLE 1: PIC32MX1XX GENERAL PURPOSE FAMILY FEATURES Device Pins Program Memory (KB)(1) Data Memory (KB) Remappable Pins Timers(2)/Capture/Compare UART SPI/I2S External Interrupts(3) Analog Comparators USB On-The-Go (OTG) I2CTM PMP DMA Channels (Programmable/Dedicated) CTMU 10-bit 1 Msps ADC (Channels) RTCC I/O Pins JTAG Packages Remappable Peripherals PIC32MX110F016B 28 16+3 4 20 5/5/5 2 2 5 3 N 2 Y 4/0 Y 10 Y 21 Y SOIC, SSOP, SPDIP, QFN PIC32MX110F016C 36 16+3 4 24 5/5/5 2 2 5 3 N 2 Y 4/0 Y 12 Y 25 Y VTLA PIC32MX110F016D 44 16+3 4 32 5/5/5 2 2 5 3 N 2 Y 4/0 Y 13 Y 34 Y VTLA, TQFP, QFN SOIC, SSOP, SPDIP, QFN PIC32MX120F032B 28 32+3 8 20 5/5/5 2 2 5 3 N 2 Y 4/0 Y 10 Y 21 Y PIC32MX120F032C 36 32+3 8 24 5/5/5 2 2 5 3 N 2 Y 4/0 Y 12 Y 25 Y VTLA Y VTLA, TQFP, QFN SOIC, SSOP, SPDIP, QFN PIC32MX120F032D 44 32+3 8 32 5/5/5 2 2 5 3 N 2 Y 4/0 Y 13 Y 34 PIC32MX130F064B 28 64+3 16 20 5/5/5 2 2 5 3 N 2 Y 4/0 Y 10 Y 21 Y PIC32MX130F064C 36 64+3 16 24 5/5/5 2 2 5 3 N 2 Y 4/0 Y 12 Y 25 Y VTLA Y VTLA, TQFP, QFN SOIC, SSOP, SPDIP, QFN PIC32MX130F064D 44 64+3 16 32 5/5/5 2 2 5 3 N 2 Y 4/0 Y 13 Y 34 PIC32MX150F128B 28 128+3 32 20 5/5/5 2 2 5 3 N 2 Y 4/0 Y 10 Y 21 Y PIC32MX150F128C 36 128+3 32 24 5/5/5 2 2 5 3 N 2 Y 4/0 Y 12 Y 25 Y VTLA Y VTLA, TQFP, QFN PIC32MX150F128D Note 1: 2: 3: 44 128+3 32 32 5/5/5 2 2 5 3 N 2 Y 4/0 Y 13 Y 34 This device features 3 KB of boot Flash memory. Four out of five timers are remappable. Four out of five external interrupts are remappable. DS61168D-page 2 Preliminary (c) 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 2: PIC32MX2XX USB FAMILY FEATURES Device Pins Program Memory (KB)(1) Data Memory (KB) Remappable Pins Timers(2)/Capture/Compare UART SPI/I2S External Interrupts(3) Analog Comparators USB On-The-Go (OTG) I2CTM PMP DMA Channels (Programmable/Dedicated) CTMU 10-bit 1 Msps ADC (Channels) RTCC I/O Pins JTAG Packages Remappable Peripherals PIC32MX210F016B 28 16+3 4 19 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 9 Y 19 Y SOIC, SSOP, SPDIP, QFN PIC32MX210F016C 36 16+3 4 23 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 12 Y 23 Y VTLA PIC32MX210F016D 44 16+3 4 31 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 13 Y 33 Y VTLA, TQFP, QFN SOIC, SSOP, SPDIP, QFN PIC32MX220F032B 28 32+3 8 19 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 9 Y 19 Y PIC32MX220F032C 36 32+3 8 23 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 12 Y 23 Y VTLA Y VTLA, TQFP, QFN SOIC, SSOP, SPDIP, QFN PIC32MX220F032D 44 32+3 8 31 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 13 Y 33 PIC32MX230F064B 28 64+3 16 19 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 9 Y 19 Y PIC32MX230F064C 36 64+3 16 23 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 12 Y 23 Y VTLA Y VTLA, TQFP, QFN SOIC, SSOP, SPDIP, QFN PIC32MX230F064D 44 64+3 16 31 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 13 Y 33 PIC32MX250F128B 28 128+3 32 19 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 9 Y 19 Y PIC32MX250F128C 36 128+3 32 23 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 12 Y 23 Y VTLA Y VTLA, TQFP, QFN PIC32MX250F128D Note 1: 2: 3: 44 128+3 32 31 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 13 Y 33 This device features 3 KB of boot Flash memory. Four out of five timers are remappable. Four out of five external interrupts are remappable. (c) 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 3 PIC32MX1XX/2XX Pin Diagrams 28-Pin SOIC, SPDIP, SSOP(1,2) = Pins are up to 5V tolerant MCLR PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3 VSS OSC1/CLKI/RPA2/RA2 OSC2/CLKO/RPA3/PMA0/RA3 SOSCI/RPB4/RB4 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 VDD TMS/RPB5/USBID/RB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Note 1: 2: 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PIC32MX210F016B PIC32MX220F032B PIC32MX230F064B PIC32MX250F128B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC32MX110F016B PIC32MX120F032B PIC32MX130F064B PIC32MX150F128B MCLR VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 VREF-/CVREF-/AN1/RPA1/CTED2/RA1 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 VSS OSC1/CLKI/RPA2/RA2 OSC2/CLKO/RPA3/PMA0/RA3 SOSCI/RPB4/RB4 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 VDD PGED3/RPB5/PMD7/RB5 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AVSS AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 AN11/RPB13/CTPLS/PMRD/RB13 AN12/PMD0/RB12 PGEC2/TMS/RPB11/PMD1/RB11 PGED2/RPB10/CTED11/PMD2/RB10 VCAP VSS TDO/RPB9/SDA1/CTED4/PMD3/RB9 TCK/RPB8/SCL1/CTED10/PMD4/RB8 TDI/RPB7/CTED3/PMD5/INT0/RB7 PGEC3/RPB6/PMD6/RB6 AVDD AVSS AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 CVREF/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14 AN11/RPB13/CTPLS/PMRD/RB13 VUSB3V3 PGEC2/RPB11/D-/RB11 PGED2/RPB10/D+/CTED11/RB10 VCAP VSS TDO/RPB9/SDA1/CTED4/PMD3/RB9 TCK/RPB8/SCL1/CTED10/PMD4/RB8 TDI/RPB7/CTED3/PMD5/INT0/RB7 VBUS The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 "I/O Ports" for more information. DS61168D-page 4 Preliminary (c) 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX Pin Diagrams (Continued) 28-Pin QFN(1,2,3) Note VREF-/CVREF-/AN1/RPA1/CTED2/RA1 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 MCLR AVDD AVSS AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 28 27 26 25 24 23 22 = Pins are up to 5V tolerant PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 1 21 AN11/RPB13/CTPLS/PMRD/RB13 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 2 20 AN12/PMD0/RB12 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 3 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 4 1: 2: 3: 10 11 12 13 14 VDD PGED3/RPB5/PMD7/RB5 PGEC3/RPB6/PMD6/RB6 TDI/RPB7/CTED3/PMD5/INT0/RB7 TCK/RPB8/SCL1/CTED10/PMD4/RB8 7 9 OSC2/CLKO/RPA3/PMA0/RA3 8 6 SOSCI/RPB4/RB4 5 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 VSS OSC1/CLKI/RPA2/RA2 PIC32MX110F016B PIC32MX120F032B PIC32MX130F064B PIC32MX150F128B 19 PGEC2/TMS/RPB11/PMD1/RB11 18 PGED2/RPB10/CTED11/PMD2/RB10 17 VCAP 16 VSS 15 TDO/RPB9/SDA1/CTED4/PMD3/RB9 The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 "I/O Ports" for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. (c) 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 5 PIC32MX1XX/2XX Pin Diagrams (Continued) 28-Pin QFN(1,2,3) Note 1: 2: 3: PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 MCLR AVDD AVSS AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 CVREF/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14 27 26 25 24 23 22 10 11 12 13 14 VDD TMS/RPB5/USBID/RB5 VBUS TDI/RPB7/CTED3/PMD5/INT0/RB7 TCK/RPB8/SCL1/CTED10/PMD4/RB8 OSC1/CLKI/RPA2/RA2 OSC2/CLKO/RPA3/PMA0/RA3 PIC32MX210F016B PIC32MX220F032B PIC32MX230F064B PIC32MX250F128B 9 3 4 5 6 7 8 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3 VSS SOSCI/RPB4/RB4 1 2 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 28 = Pins are up to 5V tolerant 21 20 AN11/RPB13/CTPLS/PMRD/RB13 VUSB3V3 19 18 17 16 15 PGEC2/RPB11/D-/RB11 PGED2/RPB10/D+/CTED11/RB10 VCAP VSS TDO/RPB9/SDA1/CTED4/PMD3/RB9 The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 "I/O Ports" for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS61168D-page 6 Preliminary (c) 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX Pin Diagrams (Continued) 36-Pin VTLA(1,2,3) PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 VREF-/CVREF-/AN1/RPA1/CTED2/RA1 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 MCLR AVDD AVSS AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 AN11/RPB13/CTPLS/PMRD/RB13 = Pins are up to 5V tolerant 36 35 34 33 32 31 30 29 28 27 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 1 26 AN12/PMD0/RB12 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 2 25 PGEC2/TMS/RPB11/PMD1/RB11 PGED(4)/AN6/RPC0/RC0 3 24 PGED2/RPB10/CTED11/PMD2/RB10 PGEC(4)/AN7/RPC1/RC1 4 23 VDD VDD 5 22 VCAP VSS 6 21 VSS 20 RPC9/CTED7/RC9 19 TDO/RPB9/SDA1/CTED4/PMD3/RB9 Note 1: 2: 3: 4: 12 13 14 15 16 17 18 PGEC3/RPB6/PMD6/RB6 TCK/RPB8/SCL1/CTED10/PMD4/RB8 TDI/RPB7/CTED3/PMD5/INT0/RB7 11 PGED3/RPB5/PMD7/RB5 10 VDD 9 VDD SOSCI/RPB4/RB4 VSS 8 RPC3/RC3 7 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 OSC1/CLKI/RPA2/RA2 OSC2/CLKO/RPA3/PMA0/RA3 PIC32MX110F016C PIC32MX120F032C PIC32MX130F064C PIC32MX150F128C The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 "I/O Ports" for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. This pin function is available on PIC32MX130F064C and PIC32MX150F128C devices only. (c) 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 7 PIC32MX1XX/2XX Pin Diagrams (Continued) 36-Pin VTLA(1,2,3) PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 MCLR AVDD AVSS AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 CVREF/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14 AN11/RPB13/CTPLS/PMRD/RB13 = Pins are up to 5V tolerant 36 35 34 33 32 31 30 29 28 27 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2 1 26 VUSB3V3 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3 2 25 PGEC2/RPB11/D-/RB11 PGED4(4)/AN6/RPC0/RC0 3 24 PGED2/RPB10/D+/CTED11/RB10 23 VDD 22 VCAP 21 VSS 20 RPC9/CTED7/RC9 19 TDO/RPB9/SDA1/CTED4/PMD3/RB9 Note 1: 2: 3: 4: 8 SOSCI/RPB4/RB4 9 10 11 12 13 14 15 16 17 18 TCK/RPB8/SCL1/CTED10/PMD4/RB8 OSC2/CLKO/RPA3/PMA0/RA3 TDI/RPB7/CTED3/PMD5/INT0/RB7 7 VBUS OSC1/CLKI/RPA2/RA2 TMS/RPB5/USBID/RB5 6 VDD VSS VSS 5 VDD VDD AN12/RPC3/RC3 4 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 PGEC4(4)/AN7/RPC1/RC1 PIC32MX210F016C PIC32MX220F032C PIC32MX230F064C PIC32MX250F128C The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 "I/O Ports" for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. This pin function is available on PIC32MX230F064C and PIC32MX250F128C devices only. DS61168D-page 8 Preliminary (c) 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX Pin Diagrams (Continued) 44-Pin QFN(1,2,3) RPB8/SCL1/CTED10/PMD4/RB8 RPB7/CTED3/PMD5/INT0/RB7 PGEC3/RPB6/PMD6/RB6 PGED3/RPB5/PMD7/RB5 VDD VSS RPC5/PMA3/RC5 RPC4/PMA4/RC4 RPC3/RC3 TDI/RPA9/PMA9/RA9 SOSCO/RPA4/T1CK/CTED9/RA4 44 43 42 41 40 39 38 37 36 35 34 = Pins are up to 5V tolerant RPB9/SDA1/CTED4/PMD3/RB9 1 33 SOSCI/RPB4/RB4 RPC6/PMA1/RC6 2 32 TDO/RPA8/PMA8/RA8 RPC7/PMA0/RC7 3 31 OSC2/CLKO/RPA3/RA3 RPC8/PMA5/RC8 4 30 OSC1/CLKI/RPA2/RA2 RPC9/CTED7/PMA6/RC9 5 29 VSS VSS 6 VCAP 7 PIC32MX110F016D PIC32MX120F032D PIC32MX130F064D PIC32MX150F128D 28 VDD 27 AN8/RPC2/PMA2/RC2 Note 1: 2: 3: 4: 16 17 18 19 20 21 22 AVDD MCLR VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 VREF-/CVREF-/AN1/RPA1/CTED2/RA1 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 AVSS AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 23 15 24 11 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 10 14 AN12/PMD0/RB12 AN11/RPB13/CTPLS/PMRD/RB13 CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 AN6/RPC0/RC0 13 AN7/RPC1/RC1 25 12 26 9 PGEC(4)/TCK/CTED8/PMA7/RA7 8 PGEC2/RPB11/PMD1/RB11 PGED4(4)/TMS/PMA10/RA10 PGED2/RPB10/CTED11/PMD2/RB10 The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 "I/O Ports" for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. This pin function is available on PIC32MX130F064D and PIC32MX150F128D devices only. (c) 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 9 PIC32MX1XX/2XX Pin Diagrams (Continued) 44-Pin QFN(1,2,3) RPB8/SCL1/CTED10/PMD4/RB8 RPB7/CTED3/PMD5/INT0/RB7 VBUS RPB5/USBID/RB5 VDD VSS RPC5/PMA3/RC5 RPC4/PMA4/RC4 AN12/RPC3/RC3 TDI/RPA9/PMA9/RA9 SOSCO/RPA4/T1CK/CTED9/RA4 44 43 42 41 40 39 38 37 36 35 34 = Pins are up to 5V tolerant RPB9/SDA1/CTED4/PMD3/RB9 1 33 SOSCI/RPB4/RB4 RPC6/PMA1/RC6 2 32 TDO/RPA8/PMA8/RA8 RPC7/PMA0/RC7 3 31 OSC2/CLKO/RPA3/RA3 RPC8/PMA5/RC8 4 30 OSC1/CLKI/RPA2/RA2 RPC9/CTED7/PMA6/RC9 5 29 VSS 28 VDD VSS 6 VCAP 7 PGED2/RPB10/D+/CTED11/RB10 8 PGEC2/RPB11/D-/RB11 PIC32MX210F016D PIC32MX220F032D PIC32MX230F064D PIC32MX250F128D 27 AN8/RPC2/PMA2/RC2 26 AN7/RPC1/RC1 Note 1: 2: 3: 4: 15 16 17 18 19 20 21 22 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 AVSS AVDD MCLR PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/CNB2/RB2 14 23 CVREF/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14 11 13 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/CNB3/RB3 AN11/RPB13/CTPLS/PMRD/RB13 12 AN6/RPC0/RC0 24 PGEC(4)/TCK/CTED8/PMA7/RA7 25 10 PGED(4)/TMS/PMA10/RA10 9 VUSB3V3 The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 "I/O Ports" for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. This pin function is available on PIC32MX230F064D and PIC32MX250F128D devices only. DS61168D-page 10 Preliminary (c) 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX Pin Diagrams (Continued) 44-Pin TQFP(1,2,3) RPB8/SCL1/CTED10/PMD4/RB8 RPB7/CTED3/PMD5/INT0/RB7 PGEC3/RPB6/PMD6/RB6 PGED3/RPB5/PMD7/RB5 VDD VSS RPC5/PMA3/RC5 RPC4/PMA4/RC4 RPC3/RC3 TDI/RPA9/PMA9/RA9 SOSCO/RPA4/T1CK/CTED9/RA4 44 43 42 41 40 39 38 37 36 35 34 = Pins are up to 5V tolerant RPB9/SDA1/CTED4/PMD3/RB9 1 33 SOSCI/RPB4/RB4 RPC6/PMA1/RC6 2 32 TDO/RPA8/PMA8/RA8 RPC7/PMA0/RC7 3 31 OSC2/CLKO/RPA3/RA3 RPC8/PMA5/RC8 4 30 OSC1/CLKI/RPA2/RA2 RPC9/CTED7/PMA6/RC9 5 29 VSS VSS 6 VCAP 7 PIC32MX110F016D PIC32MX120F032D PIC32MX130F064D PIC32MX150F128D 28 VDD 27 AN8/RPC2/PMA2/RC2 Note 1: 2: 3: 4: 21 22 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 20 VREF-/CVREF-/AN1/RPA1/CTED2/RA1 18 MCLR 19 17 AVDD VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 16 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 AVSS AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 23 15 24 11 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 10 14 AN12/PMD0/RB12 AN11/RPB13/CTPLS/PMRD/RB13 CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 AN6/RPC0/RC0 13 AN7/RPC1/RC1 25 12 26 9 PGEC(4)/TCK/CTED8/PMA7/RA7 8 PGEC2/RPB11/PMD1/RB11 PGED(4)/TMS/PMA10/RA10 PGED2/RPB10/CTED11/PMD2/RB10 The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 "I/O Ports" for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. This pin function is available on PIC32MX130F064D and PIC32MX150F128D devices only. (c) 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 11 PIC32MX1XX/2XX Pin Diagrams (Continued) 44-Pin VTLA(1,2,3) RPB8/SCL1/CTED10/PMD4/RB8 RPB7/CTED3/PMD5/INT0/RB7 PGEC3/RPB6/PMD6/RB6 PGED3/RPB5/PMD7/RB5 VDD VSS RPC5/PMA3/RC5 RPC4/PMA4/RC4 RPC3/RC3 TDI/RPA9/PMA9/RA9 SOSCO/RPA4/T1CK/CTED9/RA4 SOSCI/RPB4/RB4 = Pins are up to 5V tolerant 44 43 42 41 40 39 38 37 36 35 34 33 RPB9/SDA1/CTED4/PMD3/RB9 1 32 TDO/RPA8/PMA8/RA8 RPC6/PMA1/RC6 2 31 OSC2/CLKO/RPA3/RA3 RPC7/PMA0/RC7 3 30 OSC1/CLKI/RPA2/RA2 RPC8/PMA5/RC8 4 29 VSS RPC9/CTED7/PMA6/RC9 5 28 VDD VSS 6 27 AN8/RPC2/PMA2/RC2 VCAP 7 26 AN7/RPC1/RC1 PGED2/RPB10/CTED11/PMD2/RB10 8 25 AN6/RPC0/RC0 PGEC2/RPB11/PMD1/RB11 9 24 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 AN12/PMD0/RB12 10 23 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 Note 1: 2: 3: 4: 19 20 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 VREF-/CVREF-/AN1/RPA1/CTED2/RA1 21 22 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 18 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 17 MCLR AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 16 AVDD 15 AVSS 14 CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 PGED(4)/TMS/PMA10/RA10 13 PGEC /TCK/CTED8/PMA7/RA7 12 (4) 11 AN11/RPB13/CTPLS/PMRD/RB13 PIC32MX110F016D PIC32MX120F032D PIC32MX130F064D PIC32MX150F128D The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 "I/O Ports" for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. This pin function is available on PIC32MX130F064D and PIC32MX150F128D devices only. DS61168D-page 12 Preliminary (c) 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX Pin Diagrams (Continued) 44-Pin TQFP(1,2,3) RPB8/SCL1/CTED10/PMD4/RB8 RPB7/CTED3/PMD5/INT0/RB7 VBUS RPB5/USBID/RB5 VDD VSS RPC5/PMA3/RC5 RPC4/PMA4/RC4 AN12/RPC3/RC3 TDI/RPA9/PMA9/RA9 SOSCO/RPA4/T1CK/CTED9/RA4 44 43 42 41 40 39 38 37 36 35 34 = Pins are up to 5V tolerant RPB9/SDA1/CTED4/PMD3/RB9 1 33 SOSCI/RPB4/RB4 RPC6/PMA1/RC6 2 32 TDO/RPA8/PMA8/RA8 RPC7/PMA0/RC7 3 31 OSC2/CLKO/RPA3/RA3 RPC8/PMA5/RC8 4 30 OSC1/CLKI/RPA2/RA2 RPC9/CTED7/PMA6/RC9 5 29 VSS 28 VDD VSS 6 VCAP 7 PGED2/RPB10/D+/CTED11/RB10 8 PGEC2/RPB11/D-/RB11 PIC32MX210F016D PIC32MX220F032D PIC32MX230F064D PIC32MX250F128D 27 AN8/RPC2/PMA2/RC2 26 AN7/RPC1/RC1 Note 1: 2: 3: 4: 15 16 17 18 19 20 21 22 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 AVSS AVDD MCLR PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/CNB2/RB2 14 23 CVREF/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14 11 13 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/CNB3/RB3 AN11/RPB13/CTPLS/PMRD/RB13 12 AN6/RPC0/RC0 24 PGED(4)/TMS/PMA10/RA10 25 10 PGEC(4)/TCK/CTED8/PMA7/RA7 9 VUSB3V3 The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 "I/O Ports" for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. This pin function is available on PIC32MX230F064D and PIC32MX250F128D devices only. (c) 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 13 PIC32MX1XX/2XX Pin Diagrams (Continued) 44-Pin VTLA(1,2,3) VDD VSS RPC5/PMA3/RC5 RPC4/PMA4/RC4 AN12/RPC3/RC3 TDI/RPA9/PMA9/RA9 SOSCO/RPA4/T1CK/CTED9/RA4 SOSCI/RPB4/RB4 43 VBUS RPB7/CTED3/PMD5/INT0/RB7 44 RPB5/USBID/RB5 RPB8/SCL1/CTED10/PMD4/RB8 = Pins are up to 5V tolerant 42 41 40 39 38 37 36 35 34 33 RPB9/SDA1/CTED4/PMD3/RB9 1 32 TDO/RPA8/PMA8/RA8 RPC6/PMA1/RC6 2 31 OSC2/CLKO/RPA3/RA3 RPC7/PMA0/RC7 3 30 OSC1/CLKI/RPA2/RA2 RPC8/PMA5/RC8 4 29 VSS RPC9/CTED7/PMA6/RC9 5 28 VDD VSS 6 27 AN8/RPC2/PMA2/RC2 26 AN7/RPC1/RC1 PIC32MX210F016D PIC32MX220F032D PIC32MX230F064D PIC32MX250F128D 1: 2: 3: 4: 15 16 17 18 19 20 21 22 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 14 (4) PGED /TMS/PMA10/RA10 (4) AN11/RPB13/CTPLS/PMRD/RB13 Note 13 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/CNB2/RB2 12 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 23 11 MCLR 10 PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/CNB3/RB3 VUSB3V3 AVDD AN6/RPC0/RC0 24 AVSS 25 9 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 8 PGEC2/RPB11/D-/RB11 PGEC /TCK/CTED8/PMA7/RA7 7 CVREF/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14 VCAP PGED2/RPB10/D+/CTED11/RB10 The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 "I/O Ports" for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. This pin function is available on PIC32MX230F064D and PIC32MX250F128D devices only. DS61168D-page 14 Preliminary (c) 2011-2012 Microchip Technology Inc.