April 2011 208031-05 1
Numonyx® Axcell™ M29EW
Datasheet
128-Mbit, 64-Mbit, 32-Mbit (x8 / x16, page read)
3 V supply flash memory
Features
Supply voltage
—V
CC = 2.7 to 3.6 V for Program, Erase and
Read
—V
CCQ = 1.65 to 3.6 V for I/O buffers
Asynchronous Random/Page Read
— Page size: 8 words or 16 bytes
— Page access: 25 ns
— Random access: 60 ns (BGA); 70 ns
(TSOP)
Buffer Program
— 256-word program buffer
Programming time
— 0.56µs per byte (1.8MB/s) typical when
using 256-word buffer size in buffer
program without VPPH
— 0.31µs per byte (3.2MB/s) typical when
using 256-word buffer size in buffer
program with VPPH
Memory organization
— 128Mbit: 128 main blocks, 128 Kbytes
each
— 64Mbit: 128 main blocks, 64 Kbytes each
or eight 8-Kbyte boot blocks (top or
bottom) and 127 main blocks, 64 Kbytes
each
— 32Mbit: 64 main blocks, 64 Kbytes each or
eight 8-Kbyte boot blocks (top or bottom)
and 63 main blocks, 64 Kbytes each
Program/Er ase controller
— Embedded byte/word program algorithms
Program/ Erase Suspend and Resume
— Read from any block during Program
Suspend
— Read and Program another block during
Erase Suspend
Blank Check to verify an erased block
Unlock Bypass/Block Erase/Chip Erase/Write
to Buffer
— Faster Buffered/Batch Programming
— Faster Block and Chip Erase
VPP/WP# pin protection
—V
PPH voltage on VPP to accelerate
programming performance
— Protects highest/lowest block (H/L
uniform) or top/bottom two blocks (T/B
boot)
Software protection
— Volatile Protection
— Non-Volatile Protection
— Password Protection
— Password Access
Extended Memory block
— 128-word/256-byte block for permanent,
secure identification.
— Programmable and lockable by Numonyx
factory or customer.
Low power consumption
— Standby
Minimum 100,000 Program/Erase cycles per
block
65 nm technology
Density and Packaging
— 56-Lead TSOP (128-Mbit, 64-Mbit)
— 48-Lead TSOP (64-Mbit, 32-Mbit)
— 64-Ball Fortified BGA (128-Mbit, 64-Mbit)
— 48-Ball BGA (64-Mbit, 32-Mbit)
JESD47E compliant
Green packages available
—RoHS Compliant
— Halogen Free
Table of Contents Numonyx® Axcell™ M29EW
2 208031-05
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 Address inputs (A0-A22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 Data inputs/outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 Data inputs/outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4 Data input/output or address input (DQ15/A-1) . . . . . . . . . . . . . . . . . . . . 15
2.5 Chip Enable (CE#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6 Output Enable (OE#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.7 Write Enable (WE#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.8 VPP/Write Protect (VPP/WP#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.9 Reset (RST#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.10 Ready/Busy output (RY/BY#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.11 Byte/Word organization select (BYTE#) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.12 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.13 VCCQ input/output supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.14 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6 Auto Select mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6.1 Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.6.2 Verify Extended Memory Block protection indicator . . . . . . . . . . . . . . . .20
3.6.3 Verify block protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.6.4 Hardware Block Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4 Hardware Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5 Software Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 Volatile Protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2 Non-Volatile Protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Numonyx® Axcell™ M29EW Table of Conte n ts
208031-05 3
5.2.1 Non-Volatile Protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5.2.2 Non-Volatile Protection Bit Lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.3 Password Protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6 Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1 Standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1.1 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
6.1.2 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
6.1.3 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
6.1.4 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
6.1.5 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
6.1.6 Blank Check command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
6.1.7 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
6.1.8 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
6.1.9 Program Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
6.1.10 Program Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
6.1.11 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
6.2 Fast Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2.1 Double Byte/Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . .37
6.2.2 Quadruple Byte/Word Program command . . . . . . . . . . . . . . . . . . . . . . .38
6.2.3 Octuple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
6.2.4 Write to Buffer Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
6.2.5 Enhanced Buffer Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
6.2.6 Buffered Program Abort and Reset command . . . . . . . . . . . . . . . . . . . .43
6.2.7 Write to Buffer Program Confirm command . . . . . . . . . . . . . . . . . . . . . .44
6.2.8 Enhanced Buffer Program Confirm command . . . . . . . . . . . . . . . . . . . .44
6.2.9 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
6.2.10 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
6.2.11 Unlock Bypass Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . .45
6.2.12 Unlock Bypass Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . .45
6.2.13 Unlock Bypass Write to Buffer Program command . . . . . . . . . . . . . . . .45
6.2.14 Unlock Bypass Enhanced Buffer Program command . . . . . . . . . . . . . .45
6.2.15 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
6.3 Protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.3.1 Enter Extended Memory Block command . . . . . . . . . . . . . . . . . . . . . . .48
6.3.2 Exit Extended Memory Block command . . . . . . . . . . . . . . . . . . . . . . . .48
6.3.3 Lock Register command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table of Contents Numonyx® Axcell™ M29EW
4 208031-05
6.3.4 Password Protection mode command set . . . . . . . . . . . . . . . . . . . . . . .49
6.3.5 Non-Volatile Protection mode command set . . . . . . . . . . . . . . . . . . . . .50
6.3.6 NVPB Lock Bit command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
6.3.7 Volatile Protection mode command set . . . . . . . . . . . . . . . . . . . . . . . . .52
6.3.8 Exit Protection command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.1 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.1.1 Password Protection Mode Lock bit (DQ2) . . . . . . . . . . . . . . . . . . . . . .57
7.1.2 Non-Volatile Protection Mode Lock bit (DQ1) . . . . . . . . . . . . . . . . . . . . .57
7.1.3 Extended Memory Block Protection bit (DQ0) . . . . . . . . . . . . . . . . . . . .57
7.2 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7.2.1 Data Polling bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
7.2.2 Toggle bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
7.2.3 Error bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
7.2.4 Erase Timer bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
7.2.5 Alternative Toggle bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
7.2.6 Buffered Program Abort bit (DQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
8 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9 DC and AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
10 Programming and Erase Performance . . . . . . . . . . . . . . . . . . . . . . . . . 81
11 Package Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
12 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Appendix A 128-Mbit Memory Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Appendix C Extended Memory Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
C.1 Numonyx pre-locked Extended Memory Block . . . . . . . . . . . . . . . . . . . . . 96
C.2 Customer-lockable Extended Memory Block. . . . . . . . . . . . . . . . . . . . . . . 97
Appendix D Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Numonyx® Axcell™ M29EW List of Tables
208031-05 5
Table 1. Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. VPP/WP# functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3. Bus operations, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 4. Bus operations, 16-bit mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 5. Read electronic signature - auto select mode - programmer method (8-bit mode) . . . . . . 23
Table 6. Read electronic signature - auto select mode - programmer method (16-bit mode) . . . . . 23
Table 7. Block protection - auto select mode - programmer method (8-bit mode) . . . . . . . . . . . . . . 24
Table 8. Block protection - auto select mode - programmer method (16-bit mode) . . . . . . . . . . . . . 24
Table 9. Standard commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 10. Standard commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 11. Fast Program commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 12. Fast Program commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 13. Block Protection commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 14. Block Protection commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 15. Lock Register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 16. Block Protection Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 17. Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 18. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 19. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 20. Power-up wait timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 21. Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 22. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 23. Read AC characteristics (Sheet of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 24. Write AC characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 25. Write AC characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 26. Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 27. Accelerated Program and Data Polling/Da ta Toggle AC characteristics . . . . . . . . . . . . . . 80
Table 28. Programming and Erase Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 29. TSOP56 – 56 lead thin small-out line package, 14 x 20 mm, package mechanical data . . 82
Table 30. TSOP48 – 48 lead thin small-out line package, 12 x 20 mm, package mechanical data . . 83
Table 31. BGA48 6 x 8 mm - 6 x 8 active ball array, package mechanical data. . . . . . . . . . . . . . . . . 84
Table 32. Fortified BGA64 11 x 13 mm - 8 x 8 active ball array, package mechanical data. . . . . . . . 85
Table 33. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 34. Valid Combinations of SBC M29EW Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 35. Block Address Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 36. Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 37. CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 38. CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 39. Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 40. Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 41. Extended Memory Block address and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 42. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
List of Figures Numonyx® Axcell™ M29EW
6 208031-05
Figure 1. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. 56-Lead TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. 48-Lead TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. 48B BGA connections (top and bottom views) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. 64B Fortified BGA connections (top and bottom views) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. 128-Mbit Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. 64-Mbit and 32-Mbit Uniform Block addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. 64-Mbit and 32-Mbit Boot Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Software protection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 10. Boundary condition of program buffer size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 11. Write to Buffer Program fletcher and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 12. NVPB Program/Erase algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 13. Lock Register program flow chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 14. Data polling flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 15. Toggle flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 16. Status Register polling flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 17. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 18. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 19. Power-up wait timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 20. Random Read AC waveforms (8-bit mo de) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 21. Random Read AC waveforms (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 22. Byte Transition AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 23. Page Read AC waveforms (16-bit mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 24. Write Enable Controlled Program waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 25. Write Enable Controlled Program waveforms (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 26. Chip Enable Controlled Program waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 27. Chip Enable Controlled Program waveforms (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 28. Chip/Block Erase waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 29. Reset AC waveforms (no program/erase in progress) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 30. Reset AC waveforms (during program/erase operation) . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 31. Accelerated program timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 32. Data polling AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 33. Toggle/Alternative Toggle bit polling AC waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . 79
Figure 34. TSOP56 – 56 lead thin small-outline package,14 x 20 mm, package outline. . . . . . . . . . . 82
Figure 35. TSOP48 – 48 lead thin small-outline package, 12 x 20 mm, package outline . . . . . . . . . . 83
Figure 36. BGA48 6 x 8 mm - 6 x 8 active ball array, package outline . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 37. Fortified BGA64 11 x 13 mm - 8 x 8 active ball array, package outline . . . . . . . . . . . . . . . 85
Numonyx® Axcell™ M29EW Description
208031-05 7
1 Description
The Numonyx® AxcellTM 128-Mbit, 64-Mbit and 32-Mbit M29EW flash memories, based on
65nm SBC (Single Bit per Cell) technology is the world’s leading line of parallel NOR flash
for embedded applications. They can be read, erased and reprogrammed; and these
operat ions can be performed using a single low voltage ( 2.7 to 3.6 V) supply. Upon power-
up, these memories default to their array read mode.
The main memory array is divided into 64-Kwor d/128-Kbyte blocks or 32-Kword/64-Kbyte
bl ocks that can be erased independently so that valid data can be preserved while old data
is purged. Prog ram and Erase commands are written to the command interface of the
memory. An on-chip Program/Erase controller simplifies the process of programming or
erasing the memory by taking care of all of the special operations that are required to
update the m emory contents. The e nd of a prog ram or erase op erati on can be detected and
any error condition can be identified. The command set required to control the memory is
consistent with JEDEC standards.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the
memory. They allow simple connection to most microprocessors, often without additional
logic.
The M29EW supports Asynchronous Random Read and Page Read from all blocks of the
memory array. It also features an internal program buffer which improves throughput by
programming up to 256 words via one command sequence.
The M29EW contains a 128-word Extended Memory Block which overlaps addresses with
array block 0. The user can program this additional space; then protect it to permanently
secure its contents.
The device features different levels of hardware and software protection to secure blocks
from unwanted modification (program or erase):
lHardware protection:
–V
PP/WP# provides har dware protection f or the highest (M29EWH), lowest
(M29EWL), top t wo (M29EWT) or bottom two (M29EWB) blocks of the main
memory array.
lSoftware protection:
– Volatile Protection
– Non-Volatile Protection
– Password Protection
– Password Access
The M29EW is offered in TSOP56 (14 x 20 mm), TSOP48 (12 x 20 mm), Fortified BGA6 4
(11 x 13 mm, 1 mm pitch) and BGA48 (6 x 8 mm, 0.8 mm pitch) packages.
The memories are delivered with all bits erased (set to ‘1’).
Description Numonyx® Axcell™ M29EW
8 208031-05
Figure 1. Logic diagram
1. A22, A21 and A20 are maximum address pins for 128-Mbit, 64-Mbit and 32-Mbit density respectively.
Table 1. Signal descriptions
Name Description Direction
A0-Amax Address inputs Inputs
DQ0-DQ7 Data inputs/outputs I/O
DQ8-DQ14 Data inputs/outputs I/O
DQ15/A−1 Data input/output or address input I/O or input
CE# Chip Enable Input
OE# Output Enab le Input
WE# Write Enab le Input
RST# Reset Input
RY/BY# Ready/Busy output Output
BYTE# Byte/word organization select Input
VCCQ Input/output buffer supply voltage Supply
VCC Supply voltage Supply
VPP/WP#(1) VPP/Write Protect Input
VSS Ground -
NC Not connected -
1. VPP/WP# may be left unconnected as it is internally connected to a pull-up resistor, which enables Program/Erase
operations.
M29EW
V
CC
V
CCQ
A0 – Amax
WE#
V
PP
/WP#
DQ0 – DQ14
DQ15 / A-1
V
SS
15
CE#
OE#
RST#
BYTE#
RY/BY#
Numonyx® Axcell™ M29EW Description
208031-05 9
Figure 2. 56-Lead TSOP connections
1. A-1 is the least significant address bit in x8 mode.
2. A21 is valid for 64-Mbit density and above; otherwise, it is RFU.
3. A22 is valid for 128-Mbit density; otherwise, it is RFU.
4. RFU stands for Reserved for Future Use.
56-Lead TS OP P inout
14 mm x 20 mm
Top View
1
3
4
2
5
7
8
6
9
11
12
10
13
15
16
14
17
19
20
18
21
23
24
22
25
27
28
26
56
54
53
55
52
50
49
51
48
46
45
47
44
42
41
43
40
38
37
39
36
34
33
35
32
30
29
31
RFU
A21
A20
CE#
A19
A17
A16
A18
VCC
A14
A13
A15
A12
VPP/WP#
A11
A9
A8
A10
A6
A5
A7
A4
A2
A1
A3
OE#
RST#
WE#
DQ15 / A-1
DQ14
DQ6
DQ7
VSS
DQ5
DQ12
DQ13
DQ4
VSS
DQ11
VCCQ
DQ3
DQ2
DQ10
DQ9
DQ8
DQ0
DQ1
A0
A22
BYTE#
RY/BY#
RFU
RFU RFU
RFU
RFU
Description Numonyx® Axcell™ M29EW
10 208031-05
Figure 3. 48-Lead TSOP connections
1. A-1 is the least significant address bit in x8 mode.
2. A21 is valid for 64-Mbit density; otherwise, it is RFU.
3. RFU stands for Reserved for Future Use.
48-Lea d TSOP P inout
12 mm x 20 mm
Top View
3
4
5
7
8
6
9
11
12
10
13
15
16
14
17
19
20
18
21
23
24
22
48
46
45
47
44
42
41
43
40
38
37
39
36
34
33
35
32
31
A1
A2
A3
A5
A6
A4
A7
A18
RY/BY#
A17
VPP/WP#
RST#
WE#
A21
A20
A8
A9
A19
A10
A12
A13
A11
A14
A15
A0
CE#
Vss
DQ8
DQ1
DQ0
DQ9
DQ2
DQ10
DQ3
DQ11
DQ4
DQ12
DQ5
DQ6
DQ14
DQ13
DQ7
DQ15/A-1
OE#
Vcc
A16
BYTE#
Vss
1
2
30
28
27
29
26
25
Numonyx® Axcell™ M29EW Description
208031-05 11
Figure 4. 48B BGA connections (top and bottom vi ews)
1. A-1 is the least significant address bit in x8 mode.
2. A21 is valid for 64-Mbit density; otherwise, it is RFU.
3. RFU stands for Reserved for Future Use.
123456
BGA
Top V iew- Ball si de down BGA
Bo ttom View- Bal l sid e up
123
4
56
H
G
F
E
D
C
B
A
A1A5A19 A20A15 A11
A3A7WE# RY/BY#A13 A9
A2A6A21 A18A14 A10
A0D0D5 D2A16 D7
CE#D8D12 D10BYTE#D14
OE#D9Vcc D11
D15
/A-1 D13
H
G
F
E
D
C
B
A
A4A17RST# Vpp/
WP#
A12 A8A4 A17 RST#
Vpp/
WP# A12A8
Vss D1 D4D3 VssD6 VssD1D4 D3Vss D6
A2 A6 A21A18 A14A10
A1 A5 A19A20 A15A11
A0 D0 D5D2 A16D7
CE# D8 D12D10 BYTE#D14
OE# D9 VccD11 D15/
A-1
D13
A3 A7 WE#
RY/BY# A13A9
Description Numonyx® Axcell™ M29EW
12 208031-05
Figure 5. 64B Fortified BGA connec tions (top and bottom views)
1. A-1 is the least significant address bit in x8 mode.
2. A21 is valid for 64-Mbit density and above; otherwise, it is RFU.
3. A22 is valid for 128-Mbit density; otherwise, it is RFU.
4. RFU stands for Reserved for Future Use.
RFU
18
234567
F o rtifi e d BGA
Top Vi ew - Ball si de down F o rtifi e d BGA
Bottom Vi ew - Ball side up
1
8234
5
67
H
G
F
E
D
C
B
A
RFUA1A5A19 A20A15Vccq A11
RFUA3A7WE# RY/BY#A13RFU A9
RFUA2A6A21 A18A14 A10
Vss RFUA0D0D5 D2A16 D7
VccqD8D12 D10BYTE# D14
D9Vcc D11D13
H
G
F
E
D
C
B
A
RFUA4A17RST# Vpp/
WP#
A12A22 A8RFU A4 A17 RST#
Vpp/
WP# A12 A22A8
RFU Vss D1 D4D3 Vss RFUD6 RFUVssD1D4 D3VssRFU D6
RFU A2 A6 A21A18 A14A10
RFU A1 A5 A19A20 A15 VccqA11
VssRFU A0 D0 D5D2 A16D7
Vccq CE# D8 D12D10 BYTE#D14
RFU OE# D9 VccD11 D15/
A-1
D13
RFU A3 A7 WE# A13 RFUA9
RFU
RFU D15/
A-1
CE#
OE#
RY/BY#
RFU
RFU
RFU RFU
Numonyx® Axcell™ M29EW Description
208031-05 13
Figure 6. 128-Mbit Block address es
Figure 7. 64-Mbit and 32-Mbit Uniform Block ad dresses
64-Kword Block
64-Kword Blo ck
64-Kword Blo ck
Word Wide (x16) Mode
7FFFFF
7F0000
01FFFF
010000
00FFFF
000000
128-Kbyte Bl ock
128-Kbyte Block
128-Kbyte Block
By te -W ide (x8) Mode
0FFFFFF
0FE0000
003 FFFF
0020000
001 FFFF
0000000
A<22:-1> 128 Mbit
3FFFFF
3F0000
07FFFFF
07E0000
1
0
63
1
0
63
64-Kword Block128-Kbyte Bl ock
127 127
A<22:0> 128 Mbit
32-Kword Bl ock
32-Kword Bl ock
32-Kword Bl ock
Word Wide (x1 6) Mode
00FFFF
008000
007FFF
000000
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
Byte-W ide (x8) Mode
001FFFF
0010000
000FFFF
0000000
A<21:-1> 64 M b it
A<20:-1> 32 M b it
32-Mbit
32-Kword Bl ock
3FFFFF
3F0000
64-Kbyte Block
07FFFFF
07E0000
1
0
127
63
1
0
127
63
64-Mbit
1FFFFF
1F0000
03FFFFF
03E0000
A<21:0> 64 Mbit
A<20:0> 32 Mbit
Description Numonyx® Axcell™ M29EW
14 208031-05
Figure 8. 64-Mbit and 32-Mbit Boot Block addresses
Bottom Boot
Word Wide (x16) Mode
000000 – 000 FFF
001000 – 001 FFF
002000 – 002 FFF
003000 – 003 FFF
7F8000 – 7F9FFF
7FA000 – 7FBFFF
7FC000 – 7FDFFF
7FE000 – 7FFFFF
8KB/4KW Block
8KB/4KW Block
Top Boot 64Mbit
Byte Wi de (x8) Mode
64KB /32K W Bloc k
132
131
A<21:-1> 64 Mbit
8KB/4KW Block
8KB/4KW Block
64KB /32K W Bloc k
64KB /32K W Bloc k
133
134
0
1
126
000000 – 00FFFF
010000 – 01FFFF
7E0000 – 7EFFFF
8KB/4KW Block
64KB/32KW Block
8KB/4KW Block
Bottom Boot
Byte Wide ( x8) Mode
7F0000 – 7FFFFF
000000 – 001 FFF
64KB/32KW Block
3F0000 – 3FFFFF
1
0
70
64KB/32KW Block
010000 - 01FFFF
134
A<21:-1> 64 Mbit
A<20:-1> 32 Mbit
8KB/4KW Block
8KB/4KW Block
002000 – 003 FFF
004000 – 005 FFF
006000 – 007 FFF
008000 – 09FFFF
00A000 – 00BFFF
2
3
8
00 C 000 – 00 D F FF
00 E000 – 00 F F FF
8KB/4KW Block
8KB/4KW Block
5
4
8KB/4KW Block
8KB/4KW Block
6
7
32-Mbit
64-Mbit
004000 – 004 FFF
005000 – 005 FFF
006000 – 006 FFF
007000 – 007 FFF
008000 – 00FFFF
1F8000 – 1FFFFF
3F8000 – 3FFFFF
7F0000 – 7F1FFF
7F2000 – 7F3FFF
7F4000 – 7F5FFF
7F6000 – 7F7FFF
8KB/4KW Block
8KB/4KW Block
128
127
8KB/4KW Block
8KB/4KW Block
129
130
3F8000 – 3F9FFF
3F A 000 – 3F BF FF
3FC000 – 3FDFFF
3FE000 – 3FFFFF
8KB/4KW Block
8KB/4KW Block
Top Boot 32Mbit
Byte Wide (x8) Mode
64KB/32KW Block
68
67
A<20:-1> 32 Mbi t
8KB/4KW Block
8KB/4KW Block
64KB/32KW Block
64KB/32KW Block
69
70
0
1
62
000000 – 00FFFF
010000 – 01FFFF
3E0000 – 3EFFFF
3F0000 – 3F1FFF
3F2000 – 337FFF
3F4000 – 3F5FFF
3F6000 – 3F7FFF
8KB/4KW Block
8KB/4KW Block
64
63
8KB/4KW Block
8KB/4KW Block
65
66
A<21:0> 64 Mbit
A<20:0> 32 Mbit
A<21:0> 64 Mbit
3F8000 – 3F8FFF
3F9000 – 3F9FFF
3 F A000 – 3 F AF FF
3 F B000 – 3 F BF FF
3FC000 – 3FCFFF
3FD000 – 3FDFFF
3 F E000 – 3 F EF FF
3FF000 – 3FFFFF
000000 – 007FFF
008000 – 00FFFF
Top Boot 64Mbit
Word Wide (x16) Mode Top Boot 32Mbit
Word Wide (x16) Mode
1F8000 – 1F8FFF
1F9000 – 1F9FFF
1FA000 – 1FAFFF
1FB000 – 1FBFFF
1F C000 – 1FC FF F
1F D000 – 1FD FF F
1FE000 – 1FEFFF
1FF000 – 1 FFFFF
000000 – 007 FFF
008000 – 00FFFF
3F0000 – 3F7FFF
A<20:0> 32 Mbit
1F0000 – 1F7FFF
Numonyx® Axcell™ M29EW Signal Descriptions
208031-05 15
2 Signal Descriptions
See Figure 1: Logic diagram, and Table 1: Signal descriptions, for a brief overview of device
signals.
2.1 Address inputs (A0-A22)
The Address inputs select the cells in the memory arra y, CFI space to access during Bus
Read operations. During Bus Write operations t hey direct the commands sent to the
command interface of the Program/Erase controller.
2.2 Data inputs/outputs (DQ0-DQ7)
During Bus Read operations, the data lines output the data stored at the selected address
or register. During Bus Write operat ions, the data line s ar e used to in put dat a or command s.
2.3 Data inputs/outputs (DQ8-DQ14)
During Bus Read operations, the data lines output the data stored at the selected address
when BYTE# is High, VIH. When BYTE# is Low, VIL, these pins are not used and are high
impedance. During Bus Write operations the Command Register does not use these bits.
Ignore these bits when reading the Status Register .
2.4 Data input/output or address input (DQ15/A−1)
When the device operates in x16 bus mode, this pin behaves as a Da ta input/output pin,
together with DQ8-DQ14. When the device operates in x8 bus mode, this pin behaves as
the least significant bit of the address. Throughout this document, when both references
occur, consider the DQ15 functio n add ing to t he oth er data lin es when in X16 mode and the
A-1 function addin g to the othe rs addresses when in X8 mode, except when e xplicitly stated
otherwise.
2.5 Chip Enable (CE#)
The Chip Enable pin, CE#, activates the memory when it’s low, VIL, allowing Bus Read and
Bus Write operations to be performed. When Chip Enable is High, VIH, the memory is
deselected and power is reduced to standby level.
2.6 Output Enable (OE#)
The Output Enable pin, OE#, controls the Bus Read operation of the memory.
Signal Descriptions Numonyx® Axcell™ M29EW
16 208031-05
2.7 Write Enable (WE#)
The Write Enable pin, WE#, controls the Bus Write operation of the memory’s command
interface.
2.8 VPP/Write Protect (VPP/WP#)
The VPP/WP# pin provides three functions: write protect function, programming
acceleration, and the unlock b ypass mode entry.
When VPP/WP# is low, the write protect function provides hardware protection for the
highest M29EWH block, the lowest M29EWL block, the top two M29EWT blocks, or the
bottom two M29EW blocks (see Section 1: Description). Program and Erase operations on
this block are ignored while VPP/Write Protect is Low.
When VPP/WP# pin is Hig h, VIH, the memory re v erts to the pre v ious protec tion status of the
highest, lowest, top two or bottom two blocks . Program and Erase operations can now
modify the data in this block unless the bloc k is protected using other block protection
method.
When VPP/WP# pin is raised to VPPH in read mode, the memory automatically enters the
Unlock Bypass mode (see Section 6.2.9).
When VPP/WP# returns to VIH or VIL normal operation resumes. See th e description of the
Unlock Bypass command in the command interface section.
When VPP/WP# pin is raised to VPPH during programming, it will accelerate the
programming speed.
The transitions from VIH to VPPH and from VPPH to VIH must be slower than tVHVPP (see
Figure 31: Accelera ted program tim ing waveforms).
Never raise VPP/WP# to VPPH from any mode ex ce pt in r e ad mo de or du ring programming,
otherwise the memory may be left in an indeterminate state. A 0.1 µF capacitor should be
connected between the VPP/Write Protect pin and the VSS ground pin to decouple the
current surges from the power supply. The PCB track widths must be sufficient to carry the
currents required during programming (see IPP1, IPP2, IPP3, IPP4 in Table 22: DC
characteristics).
The VPP/WP# pin may be left unconnected because it features an internal pull-up resistor.
Refer to Table 2 for a summary of VPP/WP# functions.
Table 2. VPP/WP# functions
VPP/WP# Function
VIL Highest block protected or lowest block protected.
VIH Highest and lowest block unprotected unless software protection is activated (see
Section 4: Hardware Protection).
VPPH Unlock bypass mode.
VPPH Programming speed acceleration.
Numonyx® Axcell™ M29EW Signal Descriptions
208031-05 17
2.9 Reset (RST#)
The Reset pin can be used to apply a Hardware Reset to the memory. A hardware reset is
achieved by holding Reset Low, VIL, for at least tPLPX. After Reset goes High, VIH, the
memor y will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL (or tPHGL
or tRHGL), whichever occurs last. See Sect ion 2.10: Ready/Busy output ( RY/BY#), Table 26:
Reset AC char acteristics, Figure 29 and Figure 30 for more details.
2.10 Ready/Busy output (RY/BY#)
The Ready/Busy pin is an open-drain output that can be used to identify when the device is
performing a program or erase operation. During program or erase operations Ready/Busy
is Low, VOL (see Table 17: Status Register bits). Ready/Busy is high-impedance during
Read mode, Aut o Select mode and Erase Suspend mode.
After a Hardw are Reset, Bus Read and Bus Write oper ations cannot beg in until Ready/Busy
becomes high-impedance. See Table 26: Reset AC characteristics, Figure 29 and
Figure 30.
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A low v alue will then indicate that one , or more , of the
memories is busy. The 10K ohm or bigger resistor is recommended as pull-up resistor to
achieve 0.1V VOL.
2.11 Byte/Word organization select (BYTE#)
The BYTE# pin is used to switch between the x8 a nd x16 Bu s mod es of t he memo ry. When
Byte/Word organization select is Low, VIL, the memory is in x8 mode, when it is High, VIH,
the memory is in x16 mode.
2.12 VCC supply voltage
VCC provides the power supply for all operations (Read, Program and Erase). The
command interface is disabled when VCC is ≤ Lockout voltage, VLKO. This prevents Bus
Write operations from accidentally corrupting the data during power-up, power-down and
power surges. The operation will abort, and the memory contents being altered will thus be
invalid, if the VCC drops below VLKO while the Program/Erase controller is running.
A 0.1 µF capacitor should be connected between the VCC supply voltage pin and the VSS
ground pin to decouple the current surges from the power supply. The PCB track widths
must be suf ficient to carry the currents required during program and erase operations (see
ICC1, ICC2, ICC3 in Table 22: DC characteristics).
2.13 VCCQ input/output supply voltage
VCCQ provides the power supply to the I/O pins; it enables the I/Os to be powered
independently fr om VCC.
Signal Descriptions Numonyx® Axcell™ M29EW
18 208031-05
2.14 VSS ground
VSS is the ref erence for a ll voltag e measurements . The de vice f eatures two VSS pins; both of
which must be connected to the system ground.
Numonyx® Axcell™ M29EW Bus Operations
208031-05 19
3 Bus Operations
There are four standard bus operations that control the device. These are Bus Read
(Random and Page modes), Bus Write, Output Disable, Standby.
See Table 3: Bus operations, 8-bit mode and Tab le 4: Bus operations, 16-bit mode for a
summary. Typical glitches of less than 3ns on Chip Enable, Write Enable, and Reset pins
are ignored by the memory and do not affect bus operations.
3.1 Bus Read
Bus Read operations read from the memory cells, re gisters or CFI space. To speed up the
read oper ation the memory arra y can be read in Page mode where data is internally read
and stored in a page buffer. The page has a size of 8 words (or 16 bytes) and is addressed
by the address inputs A2-A0 in x16 bus mode and A2-A0 plus DQ15/A−1 in x8 bus mode.
The Extended Memory Blocks and CFI area do not support Page Read mode.
A valid Bus Read operation inv olves setting the desired address on the Address inputs,
applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable
High, VIH. The Data inputs/outputs will output the value, see Figure 20: Random Read AC
waveforms (8-bit mode), Figure 23: Page Read AC waveforms (16-bit mode), and Table 23:
Read AC characteristics (Sheet of 2), for details of when the output becomes valid.
3.2 Bus Write
Bus Write operations write to the comm and interface. A v alid Bus Write oper ation b egins by
setting the desired address on the Address inputs. The Address inputs are latched by the
command interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data inputs/outputs are latched by the command interface on the rising edge of
Chip Enable or Write Enable, whichever occurs firs t. Output Enable must remain High, VIH,
during the entire Bus Write operation. See Figure 24, and Figure 25, Write AC waveforms,
and Table 24 and Table 25, Write AC characteristics, for details of the timing requirements.
3.3 Output Disable
The Data inputs/outputs are in the high impedance state when Output Enable is High, VIH.
3.4 Standby
Driving Chip Enable High in Read mode, causes the memory to enter Standby mode and
the data inputs/outputs pins are placed in the high-impedan ce state. To reduce the Supply
current to the St andby Supply current, ICC2, Chip Enable should be held within VCC ±0.3V.
For the Standby current level see Table 22: DC characteristics.
During program or erase operations the memory will continue to use the Program/Erase
Supply current, ICC3, for Program or Erase operations until the operation completes.
Bus Operations Numonyx® Axcell™ M29EW
20 208031-05
3.5 Reset
During Reset mode the memory is deselected and the outputs are high impedance. The
memory is in Reset mode when RST# is at VIL. The power consumption is reduced to the
standby level, independently from the Chip Enable, Output Enable or Write Enable inputs.
3.6 Auto Select mode
The Auto Select mode allows the system or the programming equipment to read the
electronic signature, verify the protection status of the Extended Memory Block, and
apply/remove Block protect i on . For example, this mode can be use d by programming
equipment to automatically match a device and the application code to be progr ammed.
At power-up, the device is in Read mode, and can then be put in Auto Select mode by
issuing the Auto Select command (see Section 6.1.2).
The device cannot enter Auto Select mode when a program or erase operation is in
progress (RY/BY# Low). Ho w e v er, A uto Select mode can be ente red if the pro gr am or era se
operat ion has been suspended b y issuing a Progr am Suspend or Era se Suspend command
(see Section 6.1.7).
The A uto Select mode is e xited b y perf orming a reset. The de vice is returned to Read mode,
e xcep t if the Auto Select mode was entered aft er an Er ase Su spend or a Prog r am Suspend
command. In this case, it returns to the Erase or Progr am Suspend mode.
3.6.1 Read electronic signature
The memory has two codes , the manuf actu rer code and the de vice code used to id entify the
memory. These codes can be accessed by performing read operations with control signals
and addresses set as shown in Table 5: Read electronic signature - auto select mode -
progr ammer me thod (8-bit mode) and Tab le 6: Read electronic signatur e - auto select mode
- programmer method (1 6- bit mode).
These codes can also be accessed b y issuin g an A uto Select co mmand (see Section 6.1.2:
Auto Select command).
3.6.2 Verify Extended Memory Block protection indicator
The Extended Memory Block is either Numonyx pre-locked or customer-lockable.
The protection status of t he Extend ed Me mory Block (pr e-locked or customer- l ockable) can
be accessed by reading the Extended Memory Block protection indicator. It can be read in
Auto Select mode using either the programmer (see Table 7 and Table 8) or the in-system
method (see Table 9 and Table 10).
The protection status of the Extended Memory Block is th en output on bit DQ7 of the Data
input/outputs (see Table 3 and Table 4, Bus operations in 8-bit and 16-bit mode).
3.6.3 Verify block protection status
The protection status of a block can be determined by performing a read operation with
control signals and addresses set as shown in Table 7 and Table 8.
If the block is protected, then 01h (in x 8 mode) is output on Data input/outputs DQ0-DQ7,
otherwise 00h is output.
Numonyx® Axcell™ M29EW Bus Operations
208031-05 21
3.6.4 Hardware Block Protect
Hardware protection of certain memory b locks is supported via the VPP/WP# write
protection fun c t ion . When VPP/WP# is V IL, the highest (M29EWH), lowest (M29EWL), top
two (M29EWT), or bo tt om two (M29 E WB) blocks are protected ; these, and othe r blocks,
may also be ena bled with software protection.
Bus Operations Numonyx® Axcell™ M29EW
22 208031-05
Table 3. Bus operations, 8-bit mode
Operation(1) CE# OE# WE# RST# VPP/WP# Address In put s Data Inputs/O u tputs
A[max:-1] DQ[14:8] DQ[7:0]
Bus Read VIL VIL VIH VIH X Byte address Hi-Z Data output
Bus Write VIL VIH VIL VIH VIH(2) Command address Hi-Z Data input(3)
Standby VIH XXV
IH VIH X Hi-Z Hi-Z
Output Disable VIL VIH VIH VIH X X Hi-Z Hi-Z
Reset X X X VIL X X Hi-Z Hi-Z
1. X = VIL or VIH.
2. If WP# is Low, VIL, the highest, lowest, top two or bottom two blocks (depending on line item) remain protected.
3. Data input as required when issuing a command sequence, performing data polling or block protection.
Table 4. Bus operations, 16-bit mode
Operation(1) CE# OE# WE# RST# VPP/WP# Address Inputs Data Inputs/Outputs
A[max:0] DQ[15:0]
Bus Read VIL VIL VIH VIH X Word address Data output
Bus Write VIL VIH VIL VIH VIH(2) Command address Data input(3)
Standby VIH XXV
IH VIH X Hi-Z
Output Disable VIL VIH VIH VIH X X Hi-Z
Reset X X X VIL X X Hi-Z
1. X = VIL or VIH.
2. If WP# is Low, VIL, the highest, lowest, top two or bottom two blocks (depending on line item) remain protected.
3. Data input as required when issuing a command sequence, performing data polling or block protection.
Numonyx® Axcell™ M29EW Bus Operations
208031-05 23
Table 5. Read electronic signature - auto select mode - programmer method (8-bit mode)
Read
cycle(1) CE# OE# WE# Address inputs Data inputs/outputs
Amax-A11 A10-A4 A3 A2 A1 A0 A-1 DQ[14:8] DQ[7:0]
Manufacture
r code
VIL VIL VIH XV
IL
VIL VIL VIL VIL XX 89h
Device code
(cycle 1) VIL VIL VIL VIH XX 7Eh
Device code
(cycle 2) VIH VIH VIH VIL XX
21h (128-Mbit)
10h (64-Mbit, boot)
0Ch (64-Mbit, uniform)
1Ah (32-Mbit, boot)
1Dh (32-Mbit, uniform)
Device code
(cycle 3) VIH VIH VIH VIH XX
01h (128- and 64-Mbit
uniform, 64- and 32-Mbit
top)
00h (64- and 32-Mbit
bottom, 32-Mbit uniform)
1. X = VIL or VIH.
Table 6. Read electronic signature - auto select mode - programmer method (16-bit mode)
Read
cycle(1) CE# OE# WE# Address inputs Data inputs/outputs
Amax-A11 A10-A4 A3 A2 A1 A0 DQ[15:0]
Manufacturer
code
VIL VIL VIH XV
IL
VIL VIL VIL VIL 0089h
Device code
(cycle 1) VIL VIL VIL VIH 227Eh
Device code
(cycle 2) VIH VIH VIH VIL
2221h (128-Mbit)
2210h (64-Mbit, boot)
220Ch (64-Mbit, uniform)
221Ah (32-Mbit, boot)
221Dh (32-Mbit, uniform)
Device code
(cycle 3) VIH VIH VIH VIH
2201h (128- and 64-Mbit
uniform, 64- and 32-Mbit
top)
2200h (64- and 32-Mbit
bottom, 32-Mbit uniform)
1. X = VIL or VIH.
Bus Operations Numonyx® Axcell™ M29EW
24 208031-05
Table 7. Block protection - auto select mode - programmer me thod (8-bit mode)
Operation(1) CE# OE# WE# Address inputs Data inputs/outputs
Amax-A15 A14-A11 A10-A2 A1 A0 A-1 DQ[14:8] DQ[7:0]
Verify
Extended
Memory
Block
protection
indicator
(bit DQ7)
M29EWL
128-Mbit
VIL VIL VIH
XXV
IL VIH
VIH XX
89h (Numonyx pre-
locked)
09h (customer-
lockable)
M29EWH
128-Mbit
99h (Numonyx pre-
locked)
19h (customer-
lockable)
M29EWL/B
64-Mbit
32-Mbit
8Ah (Numonyx pre-
locked)
0Ah (customer-
lockable)
M29EWH/T
64-Mbit
32-Mbit
9Ah (Numonyx pre-
locked)
1Ah (customer-
lockable)
Verify block protection
status BBA(2) VIL 01h (protected)
00h (unprotected)
1. X = VIL or VIH.
2. BBA = Block Base Address. For 128-M bit, BBA shou ld be Amax-A16 and A15 is X.
Table 8. Block protection - auto select mode - programmer me thod (16-bit mode)
Operation(1) CE# OE# WE# Address inputs Data inputs/outputs
Amax-A15 A14-A11 A10-A2 A1 A0 DQ[15:0]
Verify
Extended
Memory
Block
indicator
(bit DQ7)
M29EWL
128-Mbit
VIL VIL VIH
X
XV
IL VIH
VIH
0089h (Numonyx pre-
locked)
0009h (customer-lockable)
M29EWH
128-Mbit
0099h (Numonyx pre-
locked)
0019h (customer-lockable)
M29EWL/B
64-Mbit
32-Mbit
008Ah (Numonyx pre-
locked)
000Ah (customer-lockable)
M29EWH/T
64-Mbit
32-Mbit
009Ah (Numonyx pre-
locked)
001Ah (customer-lockable)
Verify block protection
status BBA(2) VIL 0001h (protected)
0000h (unprotected)
1. X = VIL or VIH. BBA = Block Base Address.
2. BBA = Block Base Address. For 128-M bit, BBA shou ld be Amax-A16 and A15 is X.
Numonyx® Axcell™ M29EW Hardware Protection
208031-05 25
4 Hardware Protection
The M29EW f eatures a VPP/WP# pin that protects the highest, lowest, top tw o or bottom two
blocks. Refer to Section 2: Signal Descriptions for a detailed description of the signal.
5 Software Protection
The M29EW has four different software protection modes:
– Volatile Protection
– Non-Volatile Protection
– Password Protection
– Password Access
On first use all parts default to operate in non-volatile Protection mode and the customer is
free to activate the non-volatile or the password protection mode.
The desired pr ot ec tion mo de is activated by setting either the one-tim e pr ogramma ble Non-
Volatile Protection Mode Lock bit, or the Password Pro tection Mode Lock bit of the Lock
Register (see Section 7.1: Lo ck Register ). Programming the Non-Volatile Protection Mode
Lock bit or the Password Protection Mode Lock bit, to ‘0’ will permanently activate the Non-
volatile or the Password Protection mode, respectiv ely. These two bits are one-time
programmable an d non -volatile: once the protection mod e has been pr ogrammed, it can not
be changed and the device will permanently operate in the selected protection mode. It is
recommended to act ivate the desired soft w are pr otecti on mode when f irst pro gr am ming the
device.
The Non-volatile and Password Protection modes both provide non-volatile Protection.
Volatilely protected b locks and non-volatilely protected blocks can co-exist within the
memory arra y. Howe v er, the v olatile Pr otection only co ntrol the prote ction scheme for bloc ks
that are not protected using the non-volatile or password protection.
If the user attempts to program or erase a protected block, the device ignores the command
and returns to read mode.
The device is shipped with all blocks unprotected. The block protection status can be read
either by performing a read electronic signature (see Table 5 and Table 6) or by issuing an
Auto Select command (see Table 16: Block Protection Status).
For the low est and highest bl ocks, an even higher level of block protection can be achieved
by loc king the blocks using the non-volatile Protection and then by holding the VPP/WP# pin
Low.
Password Access is a security enhancement offered on the M29E W device. This feature
protects inf ormation stored in th e main-arra y bl ocks b y pre venti ng content alterat ion or reads
until a valid 64-bit password is received. Pa ssword Access may be combined with Non-
Volatile and/or Volatile Protection to create a multi-tiered solution.
Please contact your Numonyx Sales representative for further details concerning Password
Access feature.
Software Protection Numonyx® Axcell™ M29EW
26 208031-05
5.1 Volatile Protection mode
The volatile Protection allows the software application to easily protect blocks against
inadvertent change. However, the protection can be easily disabled when changes are
needed. Volatile Protection bits, VPBs, are volatile and unique for each block and can be
individually modified. VPBs only control the protection scheme for unprotected blocks that
have their non-v o latile Protection bits , NVPBs, cleared (erased to ‘1’) (see Section 5.2: Non-
Volatile Protection mode and Section 6.3.5: Non-Volatile Protection mode command set).
By issuing the VPB Program or VPB Clear commands, the VPBs are set (programmed to
‘0’) or cleared (er a sed to ‘1’), thu s placing associat ed blocks in the protecte d or u nprotect ed
state respectively. The VPBs can be set (programmed to ‘0’) or cleared (era sed to ‘1’) as
often as neede d.
When the parts are first shipped, or after a power-up or hardw are reset, the VPBs default to
be cleared.
Refer to Section 6.3.7 for a description of the volatile Protection mode command set.
5.2 Non-Volatile Protection mode
5.2.1 Non-Volatile Protection bits
A non-volatile Protection bit (NVPB) is assigned to each block.
When a NVPB is set to ‘0’, the associated block is protected, preventing any program or
erase operations in this block.
The NVPB bits can be set individually by issuing a NVPB Program command. They are non-
v olatile and will remain set through a hardware reset or a power-down/power-up sequence.
The NVPBs cannot be cleared in dividually, they can only be all cleared at the same time by
issuing a Clear all Non-Volatile Protection bits command.
The NVPBs can be protected all at a time by setting a volatile bit, the NVPB Lock bit (see
Section 5.2.2: Non-Volatile Protection Bit Lock bit).
If one of the non-volatile protected blocks needs to be unprotected (corresponding NVPB
set to ‘1’), a few more steps are required:
1. First, the NVPB Loc k b it must be ‘1’ b y e ith er pu tt ing the device through a power cycle,
or hardware reset.
2. The NVPBs can then be changed to reflect the desired settings.
3. The NVPB Lock bit must be set to ‘0’ once again to lock the NVPBs by associated
command. The device operate s normally again.
Note: 1 To achieve the best protection, it is recommended to execute the NVPB Lock Bit Program
command early in the boot code and to protect the boot code by holding VPP/WP# Low, V IL.
2 The NVPBs and VPBs have the same function when VPP/WP# pin is High, VIH, as they do
when VPP /WP# pin is at the voltage for progra m acceleration (VPPH).
Refer to Table 16: Block Protection Status and Figure 9: Software protection scheme for
details on the bloc k protect ion mecha nism, and to Section 6.3.5 f o r a d escription of the Non-
Volatile Protection mode command set.
Numonyx® Axcell™ M29EW Software Protection
208031-05 27
5.2.2 Non-Volatile Protection Bit Lock bit
The Non-Volatile Protection Bit Loc k bit (NVPB Lo c k b it) is a global volatile bit for all NVPBs .
When set (programmed to ‘0’), it prevents changing the state of the NVPBs. When reset to
‘1’, the NVPBs can be set and reset using the NVPB Program command and Clear all
NVPBs command, respectiv ely.
There is only one NVPB Lock bit per device.
Refer to Section 6.3.6 for a description of the NVPB Lock bit command set.
Note: 1 No software command unlocks this bit unless t he device is in password protection mode; in
standard non-volatile Protection mode, it can be clea red only by taking the de vice thro ugh a
hardware reset or a power-up.
2 The NVPB Lock bit must be set (programmed to ‘0’) only after all NVPBs are configured to
the desired settings.
5.3 Password Protection mode
The password protection mode provides an even higher level of security than the Non-
Volatile Protection mode by requiring a 64-bit pass w ord f or unlocking the de vice NVPB Loc k
bit.
In addition to this password requirement, the NVPB Lock bit is set ‘0’ after power-up and
reset to maintain the device in password protection mode. Successful execution of the
Password Unlock command by entering the correct password clears the NVPB Lock bit,
allowing for block NVPBs to be modified.
If the password provid ed is incorre ct, the NVPB Lock bit remains locked and th e state of the
NVPBs cannot be modified.
To place the device in password protecti on mode, the following steps are required:
1. Prior to activating the password protection mode, it is necessary to set a 64-bit
password and to verify it (see Password Program command and Password Read
command). Passw ord verification is only allowed before the pass word protection mode
is activated.
2. The password protection mode is then activated by programming the Password
Protection Mode Lock bit to ‘0’. This operation is not reversible and once the bit is
programmed it cannot be erased, the device permanently remains in password
protection mod e, and the 64 -b it pa ssword can neither be retrieve d no r re pr ogramme d .
Moreover, all commands to the ad dress where the password is stored, are disabled.
Refer to Table 16: Block Protection Status and Figure 9: Software prot ection scheme
for details on the block protection scheme.
Refer to Section 6.3.4 for a description of the Password Protection mode command set.
Note: There is no means to verify the password after Passw ord Protection mode is enabled. If the
password is lost after enabling the Password Protection mode, there is no way to clear the
NVPB Lock bit.
Software Protection Numonyx® Axcell™ M29EW
28 208031-05
Figure 9. Software protection scheme
1. NVPBs default to ‘1’ (block unprotected) when shipped from Numonyx. A block is protected or unprotected when its NVPB
is set to ‘0’ and ‘1’, respectively. NVPBs are programmed individually and cleared collectively.
2. VPB default status depends on ordering option. A block is protected or unprotected when its VPB is set to ‘0’ and ‘1’,
respectively. VPBs can be programmed and cleared individually.
3. The NVPB Lock bit is volatile and default to ‘1’ (NVPB bits unlocked) after power-up or hardware reset. NVPB bits are
locked by setting the NVPB Lock bit to ‘0’. Once programmed to ‘0’, the NVPB Lock bit can onl y be reset to ‘1’ by taking the
device through a power-up or hardware reset.
AI13676
A rra y block NVPB(1)
VPB(2)
Non-volatile
protec tion mode
Vola tile prote c tion
N on- v ola tile prote c tion
Pa s sword protec tion
mode
NVPB L ock bit(3)
Numonyx® Axcell™ M29EW Command Interface
208031-05 29
6 Command Interface
All Bus Write operations to the memory are interpreted by the command interface.
Commands consist of one or more sequential Bus Write operations. Failure to obse rve a
v alid sequence of Bus Write operations will result in the memory returning to Read mode.
The long command sequences are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16-
bit or 8-bit mode.
6.1 Standard commands
See either Table 9, or Table 10, depending on the configuration that is being used, for a
summary of the standard comman ds.
6.1.1 Read/Reset command
The device enters read mode of main array memory after a reset or power-up sequence.
The Read/Reset command returns the memory to Read mode. It also resets the errors in
the Status Register. Either one or three Bus Write operations can be used to issue the
Read/Reset command.
The Read/Reset command can be issued, between Bus Write cycles before the start of a
program or erase operation, to return the de vice to Read mode. If the Read/Reset command
is issued during the time-out of a Block erase operation, the memory will take up to 10 µs to
abort. During the abort period no valid data can be read from the mem ory.
The Read/Reset command will not abort an Erase operation when issued while in Erase
Suspend.
6.1.2 Auto Select command
The Auto Select command puts the device in Auto Select mode, once in Auto Select mode,
the system can read the manufacturer code, the device code, the protection status of each
block (Block Protection status) and the Extended Mem ory Block protection indicato r.
Three consecutive Bus Write operations are required to issue the Auto Select command.
Once the A uto Select command is issu ed Bus Read operations to spec ific addresses output
the manufacturer code, the device code, the Extended Memory Block protection indicator
and a b lock protection status (s ee Table 9 and Table 10 in conjunction with Table 5, Table 6,
Table 7, and Table 8). The memory remains in A uto Select mode until a Read/Reset or CFI
Query command is issued.
Command Interface Numonyx® Axcell™ M29EW
30 208031-05
6.1.3 Read CFI Query command
The memory contains an information area, named CFI data structure, which contains a
description of various electrical and timing parameters, density information and f unctions
supported by the memory. See Appendix B, Table 36, Table 37, Table 38, Table 39 and
Table 40 for details on the information conta i ne d in th e Com m o n Fla sh Inte rface (CFI)
memory area.
The Read CFI Query command is used to put the memory in Read CFI Query mode. Once
in Read CFI Query mode, Bus Read operations to the memory will output data from the
Common Flash Interface (CFI) memory area. One Bus Write cycle is required to issue the
Read CFI Query command. This command is valid only when the device is in the Read
Array or Auto Select mode.
The Read/Reset command must be issued to return the device to the previous mode (the
Read Array mode or Auto Select mode). A seco nd Read/Reset command is required to put
the device in Read Array mode from Auto Select mode.
6.1.4 Chip Erase command
The Chip Erase comman d can be used to erase the entire chip. Six Bus Write operations
are required to issue the Chip Erase command and start the Program/Erase controller.
If some b loc k are prote cted, then these ar e ignored and all t he other b loc ks ar e er ased. If all
of the blocks are protected the Chip Erase operation appears to start but will terminate
within about 100 µs, le aving the da ta unchanged. No er ror condition is giv en when protected
blocks are ignored.
During the Erase operation the memory will ignore all commands, including the Erase
Suspend command. It is not possible to issue any command to abort the operation. Typical
Chip Erase times are given in Table 28. All Bus Read operations during the Chip Erase
operation will output the Status Register on the Data inputs/outputs. See Section 7.2: Status
Register for more details.
After the Chip Erase operation has completed the memory will return to the Read mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read mode.
The Chip Erase command sets all of the bits in unprotected blocks of the memory to ‘1’. All
previous data is lost.
The Chip Erase operation is aborted by performing a reset or powering down the device. In
this case , data integrity cannot be ensured, and it is recommended to erase ag ain the entire
chip.
6.1.5 Block Erase command
The Block Erase command can be used to er ase a list of one or more blocks. It sets all of
the bits in the unprotected selected blocks to ‘1’. All previous data in the selected blocks is
lost.
Six Bus Write operations are required to select the first block in the list. Each additional
bl ock in the list can be selected b y repeating the sixth Bus Write oper ation using the ad dress
of the addition al block. After the command sequence is written, a Block Erase time-out
occurs. During the time-out period, additional sector addresses and sector erase commands
may be written. Once the Program/Erase controller has started, it is not possible to select
Numonyx® Axcell™ M29EW Command Interface
208031-05 31
any more b locks . Each additional blo ck must theref ore be selected within the tim e-out period
of the last block. The time-out timer restarts when an additional block is selected. After the
sixth Bus Write operation, a Bus Read operation outp uts the Status Register . See Figure 24:
Write Enable Controlled Program waveforms (8-bit mode) and Figure 25: Write Enable
Controlled Program waveforms (16-bit mode) for details on how to identify if the
Program/Erase controller has started the Block Erase operati on.
After the Block Erase operation has completed, the memory returns to the Read mode,
unless an error has occurred. When an error occurs, Bus Read operations will continue to
output the Status Register. A Read/Reset command must be issued to reset the error
condition and return to Read mode.
If an y selected b l oc ks are prote cted then t hese are ignored and all the other selected b locks
are erased. If all of the selected blocks are protected the Block Erase operation appears to
start but will terminate within about 100 µs, leaving the data unchanged. No error condition
is given when protected bl ocks are ignored.
During the Block Erase operation the memory ignores all commands except the Erase
Suspend command and the Read/Reset command which is only accepted during the time-
out period. Typical Block Erase time and Block Erase time-o ut a r e given in Table 28.
The Bloc k Er ase oper ation is ab orted by performing a reset or po w ering do wn the device. In
this case , data integrity cannot be ensured, and it is recommended to er ase again the bl ocks
aborted.
6.1.6 Blank Check command
The Blank Check operation determines whether a specified block is blank (i.e. completely
erased). Wit hout Blank Chec k, Bloc k Er ase w ould be the only other w ay to ensure a b loc k is
completely erased. Blank Check can be used to determine whether or not a prior erase
operat ion w as succe ssful; this includ es erase op er ations tha t may hav e been int errupted b y
power-loss. The Blank Check operation checks for cells that are programmed as well as
cells that are over-erased. If any cells are programmed or over-erased, Blank Check will
return a failure status, indicating tha t the block is not blank. I f a Blank Check operation
returns a passing status, the block is guaranteed blank (all 1's) and ready to program. The
erase algorithm will do Blank Check for the target bloc k firstly. If it's blank (all 1's) then the
actual erase operation will be skipped. Otherwise, the actual erase operation will continue.
This could benefit the overall cycle performance when erase happens on a blank block.
Blank check can occur in only one block at a time, and no operation s ot he r th an Statu s
Register Reads are allowed durin g Blan k Che ck (e.g. reading array data, program, erase
etc). Blank Check is not supported during any suspended operations. The status register
can be examined for Blank Check progress and errors by readin g any address within the
device.
After the Blank Check operation has completed the memory will return to the Read mode,
unless an error has occurred. When an error occurs, Bus Read operations to the memory
continue to output the Status Register. A Read/Reset command must be issued to reset the
error conditio n an d retu rn to Read mode.
Command Interface Numonyx® Axcell™ M29EW
32 208031-05
6.1.7 Erase Suspend command
The Erase Suspe nd command can be used to tempora rily suspend a Block Era se operation.
One Bus Write operat io n is re quir ed to issu e the com mand to gethe r with the block address .
After the command sequence is written, a minimum Block Erase time-out occurs (see
Table 28). During the time-out period, additional block addr esses and block erase
commands can be written.
The Program/Erase controller suspends the erase operation within the Erase Suspend
Latency time of the Erase Suspe nd com m an d be in g issu ed . Howeve r, when the Erase
Suspend command is written during the Block Erase time-out, the de vice immediately
terminates the time-out period and suspends the erase operation.
Once the Program/Erase controller has stopped, the memory operates in Read mode and
the Erase is suspended.
During Erase Suspend it is possible to read and e xecute Program or Write to Buffer Program
operations in blocks that are not suspended; both read and program operations behave as
normal on these blocks. Reading from blocks that are suspended will output the Status
Register. If any attempt is made to prog ram in a protected block or in the suspended block
then the Program command is ignored and the data remains unchanged. In this case the
Status Register is not read and no error condition is given.
It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands
during an Erase Suspend. The Read/Reset command must b e issued to return the de vice to
Read Array mode before the Resume command will be acce pted.
During Erase Suspend a Bus Read operation to the Extended Memory Block will output the
Extended Memory Block data. Once in the Extended Memory Block mode, the Exit
Extended Memory Block command must be issued before the erase operation can be
resumed.
The Erase Suspend command is ignored if written during Chip Erase operations.
Refer to Table 28: Programming and Erase Performance for the values of Block Erase time-
out and Block Erase Suspend latency time.
If the Erase Suspend operation is aborted by performing a reset or powering do wn the
device, data integrity cannot be ensured, and it is recommended to erase again the blocks
suspended.
6.1.8 Erase Resume command
The Erase Resume co mmand is used to restart the Program/Er ase controller af ter an Erase
Suspend.
The de vice must be in Read Arra y mode before the Resume command will be accepted. An
erase can be suspended and resumed more than once.
Numonyx® Axcell™ M29EW Command Interface
208031-05 33
6.1.9 Program Suspend command
The Progr am Suspend command allo ws the system to int errupt a progra m operation so that
data can be read from any block. When the Program Suspend command is issued during a
progr am operation, the device suspends the prog ram opera tion within the Prog ram Suspend
latency time (see Table 28: Programming and Erase Performance) and updates the Status
Register bits.
After the prog ram operation has been suspend ed, th e system ca n rea d arra y data f rom any
address. However, data read from program-suspended addresses is not valid.
The Program Suspend command may also be issued during a program operation while an
erase is suspended. In this case, data may be read from any addresse s not in Erase
Suspend or Program Suspend. If a read is needed from the Extended Memory Block area
(one-time program area), the user must use the proper command sequences to enter and
exit this region.
The system may also issue the Auto Select command sequence when the device is in the
Program Suspend mode. The system can read as many Auto Select codes as required.
When the device exits the Auto Select mode, the device reverts to the Program Suspend
mode, and is ready f or another valid operation. See Auto Select command sequence for
more information.
If the Program Suspend operation is aborted b y performing a reset or powering down the
device , data integrity cannot be ensured, and it is recommended to progr am again the words
or bytes aborted.
6.1.10 Program Resume command
After the Program Resume command is issued, the device reverts to programming. The
controller can determine the status of the program operation using the DQ7 or DQ6 status
bits, just as in the standard program operation. Refer to Figure 24: Write Enable Controlled
Program waveforms (8-bit mode) and Figure 25: Write Enable Controlled Program
wavefor m s (1 6- bit mod e ) for details.
The system must issue a Program Resume command, to exit the Program Suspend mode
and to continue the programming operation.
Further issuing of the Resume command is ignored. Another Program Suspend command
can be written after the device has resumed programming.
6.1.11 Program command
The Prog ram command can be used to prog ram a v alue to one address in the memory arra y
at a time. The command requir es f our Bus Write operation s, th e final write operation latches
the address and data in the internal state ma chine and starts the Program/Erase controller.
Programming can be suspended and then resumed by issuing a Program Suspend
command and a Program Resume command, respectively (see Section 6.1.9: Program
Suspend command and Section 6.1.10: Progr am Resume command).
If the address falls in a protected bloc k then the Program command is ignored, the data
remains unchanged. The Status Register is never read and no error condition is given.
After programming has started, Bus Read operatio ns output the Status Register conte nt.
See Figure 24: Write Enable Controlled Program waveforms (8-bit mode) and Figure 25:
Command Interface Numonyx® Axcell™ M29EW
34 208031-05
Write Enab le Controlled Prog ram wa v ef orms (16 -bit mode) f or mo re details. Typical progr am
times are given in Table 28: Programming and Erase Performance.
After the progr am operation has completed the memory will return to the Read mode , unless
an error has occurr ed. When a n err or occu rs , Bus Read oper atio ns to the me mory continue
to output th e Status Register. A Read/Reset command m ust be issued to reset the error
condition and return to Read mode.
One of the Erase commands must be used to set all the bits in a block or in the whole
memory from ‘0’ to ‘1’.
The Program operation is aborted by performing a reset or powering-down the device. In
this case data integ rity cannot be ensured , and it is recomm ended to repro gr am the w ord or
byte aborted.
Numonyx® Axcell™ M29EW Command Interface
208031-05 35
Table 9. Standard commands, 8-bit mode
Command
Length
Bus opera t io ns(1)
1st 2nd 3rd 4th 5th 6th
Add Data Add Data Add Data Add Data Add Data Add Data
Read/Reset 1XF0- - - - - - - - - -
3 AAA AA 555 55 X F0 - - - - - -
Auto
Select
Manuf acturer code
3 AAA AA 555 55 AAA 90 (2)(3) (2)(3) ----
Device code
Extended Memory
Bloc k pr otection
indicator
Block protection
status
Program(4) 4AAA AA 555 55 AAA A0 PA PD - - - -
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BAd 30
Erase/Progra m Suspend 1 X B0 - - - - - - - - - -
Erase/Progr am Resume 1 X 30 - - - - - - - - - -
Read CFI Query 1 AA 98 - - - - - - - - - -
Blank Check setup 6 AAA AA 555 55 BAd EB BAd 76 BAd 00 BAd 00
Blank Check confirm and
read 2 BAd 29 BAd (2) --------
1. X = Don’t care, PA = Program Address, PD = Program Data, BAd = Any address in the Block. All values in the table are in
hexadecimal.
2. These cells represent Read cycles. The other cells are Write cycles.
3. The Auto Select addresses and data are given in Table 5: Read electronic signature - auto select mode - programmer
method (8-bit mode), and Table 7: Block protection - auto select mode - programmer method (8-bit mode), except for A9
that is ‘Don’t care’.
4. In Unlock Bypass, the first two unlock cycles are no more needed (see Table 11: Fast Program commands, 8-bit mode and
Table 12: Fast Program commands, 16-bit mode).
Command Interface Numonyx® Axcell™ M29EW
36 208031-05
Table 10. Standard commands, 16-bit mode
Command
Length
Bus operations(1)
1st 2nd 3rd 4th 5th 6th
Add Data Add Data Add Data Add Data Add Data Add Data
Read/Reset 1XF0-- - - - -- - --
3555AA2AA55 X F0 - - - - - -
Auto
Select
Manufacturer code
3 555 AA 2AA 55 555 90 (2)(3) (2)(3) ----
Device code
Extended Memory
Block protection
indicator
Block protection
status
Program(4) 4555 AA 2AA 55 555 A0 PA PD - - - -
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BAd 30
Erase/Progra m Suspend 1 X B0 - - - - - - - - - -
Erase/Program Resume 1 X 30 - - - - - - - - - -
Read CFI Query 1 55 98 - - - - - - - - - -
Blank Check setup 6 555 AA 2AA 55 BAd EB BAd 76 BAd 00 BAd 00
Blank Check confirm and
read 2 BAd 29 BAd
(2) --------
1. X = Don’t care, PA = Program Address, PD = Program Data, BAd = any address in the Block. All values in the table are in
hexadecimal.
2. These cells represent Read cycles. The other cells are Write cycles.
3. The Auto Select addresses and data are given in Table 6: Read electronic signature - auto select mode - programmer
method (16-bit mode), and Table 8: Block protection - auto select mode - programmer method (16-bit mode), except for A9
that is ‘Don’t care’.
4. In Unlock Bypass, the first two unlock cycles are no more needed (see Table 11 and Table 12 Fast Program commands, 8-
bit and 16-bit mode).
Numonyx® Axcell™ M29EW Command Interface
208031-05 37
6.2 Fast Program commands
The M29EW offers a set of Fast Program commands to improve the programming
throughput:
– Double Byte/Word Program (for 32-Mbit and 64-Mbit devices)
– Quadruple Byte/Word Program (f or 32-Mbit and 64-Mbit devices)
– Octuple Byte Program (for 32-Mbit and 64-Mbit devices)
– Write to Buffer Program
– Enhanced Buffer Program (x16 128-Mbit device only)
– Unlock Bypass
The Table 11: Fast Program commands, 8-bit mode on page 46 and the Table 12: Fast
Program commands, 16-bit mode on page 47 show a summary of the Fast Program
commands.
When VPPH is applied to the VPP/WP# pin during Write to Buffer Program and Enhanced
Buffer Program, it will accelerate the programming speed. (see Figure 31: Accelerated
program timing waveforms)
When VPPH is applied to the VPP/WP# pin in read mode, the memory automatically enters
Unlock Bypass mode (see Section 6 .2 .9 : Unlo ck Bypass command ).
Note: For double byte/word program, quadruple byte/word prog ram and octuple byte program,
only VPPL could be applied to the VPP/WP# pin.
After programming has started, Bus Read operations in the memory output the Status
Register conte nt . Write to Buffer Program command can be sus pe nded and then resumed
by issuing a Program Suspend command and a Program Resume command, respectively
(see Section 6.1.9: Program Suspend command and Section 6.1.10: Program Resume
command).
After the fast program operation has completed, the memory will return to the Read mode,
unless an error has occurred. When an error occu rs Bus Read operations to the memory
will continue to output the Status Register. A Read/Reset command must be issued to reset
the error condition and return to Read mode. One of the Erase commands must be used to
set all the bits in a block or in the whole memory from ‘0’ to ‘1’.
Typical program times are given in Table 28: Pr ogramming and Erase Performance.
6.2.1 Double Byte/Word Program command
The Double Byte/Word Program command for 32-Mbit and 64-Mbit devices is used to write
a page of two adjacent bytes/words in parallel. The two bytes/words must differ only for the
address A-1 or A0, respectively. Three bus write cycles are necessary to issue the Double
Byte/Word Program command:
1. The first bus cycle sets up the Double Byte/Word Program command.
2. The second bus cycle latches the Address and the Data of the first byte/word to be
programmed.
3. The third bus cycle latches the Address and the Data of the second byte/word to be
programmed and starts the Program/Erase Controller.
See Table 11: Fast Program commands, 8-bit mode and Table 12: Fast Program
commands , 16-bit mode for command details.
Command Interface Numonyx® Axcell™ M29EW
38 208031-05
6.2.2 Quadruple Byte/Word Program command
The Quadruple Byte/Word Program command for 32-Mbit and 64-Mbit devices is used to
write a page of four adjacent bytes/words in parallel. The four bytes/words m ust differ fo r
addresses A0, DQ15/A-1 in x8 mode or addresses A1, A0 in x16 mode. Five bus write
cycles are necessary to issue the Quadruple Byte/Word Program command:
1. The first bus cycle sets up the Quadruple Byte/Word Program command.
2. The second bus cycle latches the Address and the Data of the first byte/word to be
programmed.
3. The third bus cycle latches the Address and the Data of the second byte/word to be
programmed.
4. The fourth bus cycle latches the Address and the Data of the third byte/word to be
programmed.
5. The fifth bus cycle latches the Address and the Data of the fourth byte/word to be
programmed and starts the Program/Erase Controller.
See Table 11: Fast Program commands, 8-bit mode and Table 12: Fast Program
commands , 16-bit mode for command details.
6.2.3 Octuple Byte Program command
The Octuple Byte Program command for 32-Mbit and 64 -Mbit devices is used to write a
page of eight adjacent bytes in parallel. The eight bytes must differ for addresses A1, A0,
DQ15/A-1 in x8 mode only. Nine bus write cycles are necessary to issue the Octuple Byte
Program command:
1. The first bus cycle sets up the Octuple Byte Program command.
2. The second bus cycle latches the Address and the Data of the first byte to be
programmed.
3. The third bus cycle latches the Address and the Data of the second byte to be
programmed.
4. The fourth bus cycle latches the Address and the Data of the third byte to be
programmed.
5. The fifth bus cycle latches the Address and the Data of the fourth byte to be
programmed.
6. The sixth bus cycle latches the Address and the Data of the fifth byte to be
programmed.
7. The seventh bus cycle latches the Address and the Data of the sixth byte/word to be
programmed.
8. The eighth bus cycle latches the Address and the Data of the seventh byte/word to be
programmed.
9. The ninth bus cycle latches the Address and the Data of the eighth byte/word to be
programmed and starts the Program/Erase Controller.
See Table 11: Fast Program commands, 8-bit mode and Table 12: Fast Program
commands , 16-bit mode for command details.
Numonyx® Axcell™ M29EW Command Interface
208031-05 39
6.2.4 Write to Buffer Program command
The Write to Buffer Program command makes use of the device’s 256-word program buffer
to speed up programming. A maximum of 256 words can be loaded into t he program buffer
in word mode. In byte mode, the maximum buffer size is 256-byte (128-word) due to the
limitation of 8 pins. The Write to Buffer Program command dramatically reduces system
programming time compared to the standard non-buffered Program command.
Note: The maximum number of bytes in write buffer in CFI region (refer to offset 2Ah, Table 39:
Device geometry definition on page 93) is set to 08h (256 bytes) for backward compatible
reasons. No software cha nge is required on the existing applications in both x8 and x16
mode. How e v er, the system performance can be o ptimiz ed by implement the maxim um 256-
word buffer size, contact your sales representatives for questions.
When issuing a Write to Buffer Prog ram command, the VPP/WP# pin can be either held
High, VIH, or raised to VPPH (programming acceleration).
See Table 28 for details on typical Write to Buffer Program times in both cases .
Five successive steps are re qu ir ed to issu e the W rite to Buffer Program command:
1. The Write to Buffer Program command starts with two unlock cycles.
2. The third bus write cycle sets up the Write to Buffer Program command. The set-up
code can be addressed to any location within the tar geted block.
3. The f ourth bus write cycle sets up the number of words/bytes to be programmed. Value
N is written to the same b lock address, where N+1 is the number of w ords/bytes to be
programmed. N+1 must not exceed the size of the p rogram buffer, otherwise the
operatio n will abort. In x8 mode, the maximum N should be no more than 256.
4. The fifth cycle loads the first address and data to be prog rammed.
5. Use N bus write cycles to load the address and data for each word/byte into the
program buffer. Addresses must lie within t he range from the start address+1 to the
start address + N-1. Optimum programming performance and lower power usage are
obtained by aligning the starting address at the beginning of a 256-word boundary
(A[7:0] = 000h). All the ad dr e sse s use d in the Write to Buffer Program operation must
lie within the 256-word boundary. Any crossing boundary buffer progr am will result in a
program abort. See Figure 10 for details of the available program buffer size.
To program the content of the program buffer, this command must be followed by a Write to
Buffer Program Confirm command.
If an address is written several times during a Write to Buffer Program operation, the
address/data counter will be decremented at each data load operation and the data will be
programmed to the last word loaded into the buffer.
Invalid address combinations or failing to fo llow the correct sequence of Bus Write cycles
will abort the Write to Buffer Program.
The Status Register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status
during a Write to Buffer Program operation.
It is possible to detect Program operation fails when changing programmed data from ‘0’ to
‘1’, that is when reprogramming data in a portion of memory already programmed. The
resulting data will be the logical OR between the previous value and the current value.
See Figure 11: Write to Buffer Program fletcher and pseudo code, for a suggested flow
chart on using the Write to Buffer Program command .
Command Interface Numonyx® Axcell™ M29EW
40 208031-05
6.2.5 Enhanced Buffer Program
The Enhanced Buffer Program command, available only on x16 mode 128-Mbit device,
makes use of the de vice’s 256-word write buffer to speed up programming. 256 words can
be loaded into the write buffer. Each write buffer has the same A22-A8 addresses. The
Enhanced Buffer Program command dramatically reduces system programming time .
When issuing a Enhanced Buffer Program command, the VPP/WP# pin can be either held
High, VIH, or raised to VPPH (programming acceleration).
The Enhanced Buffer Program has the same programming speed as a 256-word write to
buffer program speed. See Table 28 for details.
Three successive steps are required to issue the Enhanced Buffer Program command:
– The Enhanced Buffered Program command starts with two unlock cycles.
– The third bus write cycle sets up the Enhanced Buffered Program command. The
setup code can be addressed to any location within the target ed block.
– The fourth bus write cycle loads the first address and data t o be programmed.
There a total of 256 address and data loading cycles.
To progr am the content of the write b u ffer , th e Enhanced Buffer Progra m comma nd m ust be
followed by an Enhanced Buffer Program Confirm command. The command ends with an
internal Enhanced Buffer Program confirm cycle.
Note that address/data cycles must be loaded in an increasing address order (A[7:0] from
00h to FFh) and completely (a ll 256 w ords). Invalid address combinations or failing to follo w
the correct sequence of bus write cycles will result in Enhanced Buffer Program abort.
The status register bits DQ1, DQ5, DQ6, an d DQ7 can be used to monitor the device status
during an Enhanced Buffer Program operation.
An external supply (12 V) can be used to imp rove programming efficiency.
It is possible to detect program operation fails when changing programmed data from “0” to
“1”.
Note: Enhanced Buffered Program commands are available for x 16 mode only.
Numonyx® Axcell™ M29EW Command Interface
208031-05 41
Figure 10. Boundary condition of program buffer size
256 Words
256
Words
program
buffer is
allowed
256
Words
program
buffer is
allowed
Any
buffer
program
attempt
i s not
allowed
255
Words
or less
program
buffer is
allowed
0000h
0100h
0200h
256 Words
Command Interface Numonyx® Axcell™ M29EW
42 208031-05
Figure 11. Write to Buffer Program fletcher and pseudo code
1. n+1 is the number of addresses to be programmed.
2. A Write to Buffer Program Abort and Reset must be issued to return the device in Read mode.
3. When the block address is specified, any address in the selected block address space is acceptable. However when
Write to Buffer
command,
block address
AI08968b
Start
Write Buffer Data,
start address
Abort Write
to Buffer
FAIL OR ABORT
(5)
Write n
(1)
,
block address
X = 0
Write Next Data,
(3)
Program Address Pair
X = X-1
Write to Buffer Program
Confirm, block address
Read Status Register
(DQ1, DQ5, DQ7) at
last loaded address
YES
DQ7 = Data
Check Status Register
(DQ5, DQ7) at
last loaded address
NO
YES
Write to a different
block address
Write to Buffer and
Program Aborted
(2)
DQ5 = 1
DQ1 = 1
DQ7 = Data
(4)
END
First three cycles of the
Write to Buffer and Program command
X=n
YES
YES
YES
YES
NO
NO
NO
NO
NO
Numonyx® Axcell™ M29EW Command Interface
208031-05 43
loading program buffer address with data, all addresses must fall within the selected program buffer page.
4. DQ7 must be checked since DQ5 and DQ7 may change simultaneously.
5. If this flow chart location is reached because DQ5=’1’, then the Write to Buffer Program command failed. If this flow chart
location is reached because DQ1=’1’, then the Write to Buffer Program command aborted. In both cases, the appropriate
reset command must be issued to return the device in Read mode: a Reset command if the operation failed, a Write to
Buffer Program Abort and Reset command if the operation aborted.
6. See Table 9 and Table 10, for details on Write to Buffer Program command sequence.
6.2.6 Buffered Program Abort and Reset command
A Buffered Progr a m Abo rt and Reset command must b e issue d to ab ort the Buffe r Prog r am
operation and reset the device in Read mode.
The buf fer programming sequence can be aborted in the following ways:
– Load a value that is greater than the page buffer size during the number of
locations to program step in the Write to Buffer Program command.
– Write to an address in a block different than the one specified during the write-
buffer-load command.
– Write an address/data pair to a different write-buffer-page than the one selected
by the starting address during the program buffer data loading stage of the
operation.
– Write data other than the Confirm command after the specified number of data
load cycles.
The abort condition is indicated by DQ1 = 1, DQ7 = DQ7 (for the last address location
loaded), DQ6 = togg le, and DQ5 = 0 (all of which are Status Register bits). A Buffered
Program Abort and Reset command sequence must be written to reset the device for the
next operation. Note that the full 3-cycle Buffered Program Abort and Reset command
sequence is required when using Buffer Programming features in Unlock Bypass mode.
Command Interface Numonyx® Axcell™ M29EW
44 208031-05
6.2.7 Write to Buffer Program Confirm command
The Write to Buff er Pr ogram Conf irm command is used to confirm a Write to Buff er Prog ram
command and to program the N+1 words/byte s loaded in the program buffer by this
command.
6.2.8 Enhanced Buffer Program Confirm command
The Enhanced Buffer Program Confirm command is used to confirm an Enhanced Buffer
Program command and to program the 256 words loaded in the buffer.
6.2.9 Unlock Bypass command
The Unloc k Bypass command is used to place the de vice in Unloc k Bypass mode. When the
de vice enter s the Unloc k Bypass mode , t he two init ial unloc k cycles required in the stand ard
progr am command sequence are no more ne eded, and only tw o write cycles are required to
program data, instead of the normal four cycles (see Note 4 below Table 9 and Table 10).
This results in a faster total programming time.
Unloc k Bypa ss command is consequently used in conjunction with the Unlock Bypass
Program command to program the memory faster than with the standard program
commands. When the cycle time to the device is long, considerable time saving can be
made by using these commands. Three Bus Write operations are required to issue the
Unlock Bypass command.
When in Unlock Bypass mode, only the Unlock Bypass Program, Unlock Bypass Block
Erase, Unlock Bypass Chip Erase, and Unlock Bypass Reset commands are valid:
– The Unlock Bypass Program command can be issued to program addresses
within the mem ory.
– The Unlock Bypass Block Erase command can then be issued to erase one or
more memory blocks.
– The Unlock Bypass Chip Erase command can be issued to erase the whole
memory array.
– The Unlock Bypass Write to Buffer Program command can be issued to speed up
programming operation.
– The Unlock Bypass Reset command can be issued to return the memory to Read
mode.
In Unlock Bypass mode the memory can be read as if in Read mode.
6.2.10 Unlock Bypass Program command
The Unloc k Bypass Progr am command can be used to pr ogram on e address in the memory
array at a time. The command requires two Bus Write operations, the final write operation
latches the address and data and starts the Program/Erase controller.
The Program operation usin g the Unlock Bypass Program command behaves identically to
the Program operation using the Program command. The operation cannot be aborted, a
Bus Read oper ation to the memory outputs the Stat us Register. See the progr am comman d
in Table 11.: Fast Program comma nds , 8- bit mode and Table 12.: Fast Program co mma nds,
16-bit mode for more details.
Numonyx® Axcell™ M29EW Command Interface
208031-05 45
6.2.11 Unlock Bypass Block Erase command
The Unlock Bypass Block Erase command can be used to Erase one or more memory
blocks at a time. The command requires two Bus Write operations instead of six using the
standard Block Erase command. The final Bus Write operation latches the address of the
bl ock and starts the Program/Erase controller.
To erase multiple block (after the first two Bus Write operations have selected the first block
in the list), each additional block in the list can be selected by repeating the second Bus
Write operation using the address of the additional block.
The Unloc k Bypass Block Erase command behaves in the same way as the Block Erase
command: th e op eration ca nn ot be aborted, and a Bus Read operation to the mem o ry
outputs the Status Register (see Section 6.1 .5 : Block Erase command for details).
6.2.12 Unlock Bypass Chip Erase command
The Unloc k Bypass Chip Erase comma nd can be used to era se all memory bloc ks at a time .
The command requires two Bus Write operat ions only instead of six using the standard Chip
Erase command. The final Bus Write operation starts the Program/Erase controller.
The Unlock Bypass Chip Erase command behaves in the same way as the Chip Erase
command: th e op eration ca nn ot be aborted, and a Bus Read operation to the mem o ry
outputs the Status Register (see Section 6.1.4: Chip Erase command for details).
6.2.13 Unlock Bypass Write to Buffer Program command
The Unlock Bypass Write to Buffer command can be use d to pro gram the memory in Fast
Program mode. The command requires two Bus Write operations less than the standard
Write to Buffer Program command.
The Unloc k Bypass Write to Buffer Program command behaves in the same way as the
Write t o Buffer Program command: the operation ca nn o t be ab o rte d an d a Bus Read
operation to the memory outputs the Status Register (see Section 6.2.4: Write to Buffer
Progra m command for details).
The Write to Buffer Program Confirm command is used to confirm an Unlock Bypass Write
to Buffer Program comma nd and to program the N+1 words/bytes loaded in the progr am
buffer by this command.
6.2.14 Unlock Bypass Enhanced Buff er Program command
The Unlock Bypass Enhanced Buffer Program command can be used to program the
memory in f ast progr am mode. The command requires two address/data loading cycles less
than the regular Enhanced Buffer Program command (see Table 12: Fast Program
commands , 16-bit mode for the details).
The Unlock Bypass Enhanced Buffer Program command behaves identically to the
Enhanced Buffer Program operation using the Enhanced Buffer Program command. The
operation cannot be aborted and a bus read operation to the memory outputs the status
register (see Chapter 6.2.8: Enhanced Buffer Program Confirm command for the behavior
details).
The Enhanced Buffer Program Confirm command is used to confirm an Unlock Bypass
Enhanced Buffer Program command and to program the 256 words loaded in the buffer.
Command Interface Numonyx® Axcell™ M29EW
46 208031-05
6.2.15 Unlock Bypass Reset command
The Unlock Bypass Reset command can be used to return to Read/Reset mode from
Unloc k Bypass mode. Two Bus Write operations are required to issue the Unlock Bypass
Reset command. Read/Reset command does not exit from Unlock Bypass mode.
Table 11. Fast Program commands, 8-bit mode
Command
Length
Bus Write operations(1)
1st 2nd 3rd 4th 5th
Add Data Add Data Add Data Add Data Add Data
Double Byte
Program 3 AAA 50 PA2(2) PD - - - - - -
Quadruple Byte
Program 5 AAA 56 PA4(3) PD - - - - - -
Octuple byte
Program 9 AAA 8B PA8(4) PD - - - - - -
Write to Buffer
Program N+5 AAA AA 555 55 BAd 25 BAd N(5) PA(6) PD
Write to Buffer
Program Confirm 1 BAd(7) 29 - - - - - - - -
Buff ered Prog ram
Abort and Reset 3 AAA AA 555 55 AAA F0 - - - -
Unlock Bypass
mode entry 3 AAA AA 555 55 AAA 20 - - - -
Unlock Bypass
Program 2XA0PAPD- - - - - -
Unlock Bypass
Block Erase 2+ X 80 BAd 30 - - - - - -
Unlock Bypass
Chip Erase 2X80X10 - - - - - -
Unlock Bypass
Write to Buffer
Program N+3 BAd 25 BAd N(5) PA(6) PD - - - -
Unlock Bypass
Reset 2X90X00 - - - - - -
1. X = Don’t care, PA = Program Address, PD = Program Data, BAd = Any address in the Block. All values in the table are in
hexadecimal.
2. Amax-A0 address pins should remian unchanged. Address A-1 selects between adjacent bytes.
3. Amax-A1 address pin should remain unchanged. A0 and A-1 pins are used to select four adjacent bytes. This address
should be used four times.
4. Amax-A2 address pin should remain unchanged. A1, A0 and A-1 pins are used to select eight adjacent bytes. This address
should be used eight times.
5. The maximum number of cycles in the buffer program command sequence is 261. The maximum number of cycles in the
unlock bypass buffer program command sequence is 259. N+1 is the number of bytes to be programmed during the Write
to Buffer Program operation.
6. Amax-A7 address pins should be consistently unchanged. Addresses A[6:-1] select a byte within the N+1 byte page.
7. BAd must be identical to the address loaded during the Write to Buffer Program 3rd and 4th cycles.
Numonyx® Axcell™ M29EW Command Interface
208031-05 47
Table 12. Fast Program commands, 16-bit mode
Command
Length
Bus Write operations(1)
1st 2nd 3rd 4th 5th
Add Data Add Data Add Data Add Data Add Data
Double Word
Program 3 555 50 PA2(2) PD - - - - - -
Quadruple Word
Program 5 555 56 PA4(3) PD - - - - - -
Write to Buffer
Program N+5 555 AA 2AA 55 BAd 25 BAd N(4) PA(5) PD
Write to Buffer
Program Confirm 1 BAd(6) 29- -------
Enhanced Buffer
Program N+5 555 AA 2AA 55 BAd 33 BAd N(4) PA(5) PD
Enhanced Buffer
Program Confirm 1 BAd(6) 29- -------
Buff ered Prog ram
Abort and Reset 3 555 AA 2AA 55 555 F0 - - - -
Unlock Bypass mode
entry 3 555 AA 2AA 55 555 20 - - - -
Unlock Bypass
Program 2XA0PAPD- - - - - -
Unlock Bypass Block
Erase 2+ X 80 BAd 30 - - - - - -
Unlock Bypass Chip
Erase 2X80X10- - - - - -
Unlock Bypass Write
to Buffer Program N+3 BAd 25 BAd N(4) PA(5) PD - - - -
Unlock Bypass
Enhanced Buffer
Program N+3 BAd 33 BAd N(4) PA(5) PD - - - -
Unlock Bypass Reset 2 X 90 X 00 - - - - - -
1. X = Don’t care, PA = Program Address, PD = Program Data, BAd = Any address in the Block. All values in the table are in
hexadecimal.
2. Amax-A1 address pin should remain unchanged. A0 pin is used to select two adjacent words.
3. Amax-A2 address pin should remian unchanged. A1 and A0 pins are used to select four adjacent words. This address
should be used four times.
4. The maximum number of cycles in the buffer program command sequence is 261. The maximum number of cycles in the
unlock bypass buffer program command sequence is 259. N+1 is the number of bytes to be programmed during the Write
to Buffer Program operation.
5. Amax-A9 address pins should be consistently unchanged. A0-A8 pins are used to select a word within the N+1 word page.
6. BAd must be identical to the address loaded during the Write to Buffer Program 3rd and 4th cycles.
Command Interface Numonyx® Axcell™ M29EW
48 208031-05
6.3 Protection commands
Blocks can be protected individually against accidental program, erase or read operations.
The device b lock protection scheme is sho wn in Figure 9: Software protection scheme. See
either Table 13, or Table 14, depending on the configuration that is being used, for a
summary of the Block Protection commands.
Block protection commands are available both in 8-bit and 16-bit configuration.
The protections of both memory blocks and Extended Memory Block prote ction are
configured thr ough the Lock register (see Section 7.1: Lo ck Register).
6.3.1 Enter Extended Memory Block command
The M29EW has one extra 128-word Extended Memory Block that can only be accessed
using the Enter Extended Memory Block command.
Three Bus Write cycles are required to issue the Enter Extended Memory Block command.
Once the command has been issued the device enters the Extended Memory Block mo de
where all Bus Read or Program operations are conducted on the Extended Memory Block.
Once the device is in the Extended Memory Block mode, the Extended Memory Block is
addressed by using the addresses occupied by block 0 in the other operating modes (see
Figure 8: 64-Mbit and 32-Mbit Boo t Block addresses on page 14).
The de vice remain s in Extended Memory Block mode until the Exit Extended Memory Block
command is issued or power is remove d from the device. After a power-up sequence or
hardware reset, the device will revert to reading from memory blocks in the main array.
The Extended Memory Bloc k cannot be erased, and each bit of t he Extended Memory Block
can only be programmed once.
In Extended Memory Block mode, Erase, Chip Erase, Erase Suspend and Erase Resume
commands ar e no t allowed.
To exit from the Extended Memory Block mode the Exit Extended Memory Block command
must be issued.
The Extended Memory Block is protected from further modificati on by programming Lock
Register bit 0 (see Section 7.1: Lock Register). Once invoked, this protection cannot be
undone.
6.3.2 Exit Extended Memory Block command
The Exit Extended Memory Block comma nd is used to ex it from the Extended Memory
Bloc k mode a nd return the device to Read mode. Four Bus Write oper ations ar e requ ired to
issue the command.
Numonyx® Axcell™ M29EW Command Interface
208031-05 49
6.3.3 Lock Register command set
The M29EW offers a set of commands to access the Lock Register and to configure and
verify its content. See the following sections in conjunction with Section 7.1: Lock Register,
Table 13 and Table 14.
Enter Lock Register Command Set command
Three Bus Write cycles are required to issue the Ente r Lock Register Command Set
command. Once the command has been issued, all Bus Read or Program operations are
issued to the Lock Register.
Lock Register Program and Lock Register Read command
The Lock Register Program command allows to configure the Lock Register. The
programmed data can then be checked by issuing a Lock Register Read command.
An Exit Protection Command Set command must then be issued to return the device to
Read mode (see Section 6.3.8: Exit Protection command set).
6.3.4 Password Protection mode command set
Enter Password Protection Command Set command
Three Bus Write cycles are required to issue the Enter Password Protection Command Set
command. Once the command has been issued, the commands related to the Password
Protection mode can be issued to the device.
Password Program command
The Password Program command is used to program the 64-bit password used in the
Password Protection mode.
To program the 64-bit password, the complete command sequence must be entered eight
times at eight consecutive addresses selected by A1-A0 plus DQ15/A-1 in 8-bit mode, or
four times at four consecutive addresses selected by A1-A0 in 16-bit mode.
The password can be checked by issuing a Password Read command.
Once Password Program operation has completed, an Exit Protection Command Set
command must be issued to return the device to Read mode. The Pass word Protection
mode can then be selected.
By default, all Password bits are set to ‘1’.
Password Read command
The Password Read command is used to verify the Password used in Password Protection
mode.
To verify the 64-bit password, the complete command sequence must be entered eight
times at eight consecutive addresses selected by A1-A0 plus DQ15/A-1 in 8-bit mode, or
four times at four consecutive addresses selected by A1-A0 in 16-bit mode.
If the Password Mode Lock bit is programmed and the user atte mp ts to rea d the pa ssword,
the device will output FFh onto the I/O data bus.
An Exit Protection Command Set command must be issued to return the device to Read
mode.
Command Interface Numonyx® Axcell™ M29EW
50 208031-05
Password Unlock command
The Password Unlock command is used to clear the NVPB Lock bit allowing to modify the
NVPBs.
The Password Unlock command must be issued along with the correct password.
There must b e a 1 µs delay between successive Password Unlock commands in order to
pre v ent hac kers from crac king the pass w ord by t rying all possib le 64-bit comb inations. If this
delay is not respected, the latest command will be ignored.
Approximately 1 µs is required for unlocking the device after the valid 64-bit password has
been provided.
6.3.5 Non-Volatile Protection mode command set
Enter Non-Volatile Protection Command Set command
Three Bus Write cycles are required to issue the Enter Non-Volatile Protection Command
Set command. Once the command has been issued, the commands related to the Non-
Volatile Protection mode can be issued to the device.
Non-Volatile Protection Bit Program command (NVPB Program)
A bl ock can be protected from progr am or erase by issuing a Non-Volatile Protection Bit
command along with the block address. This command sets the NVPB to ‘1’ for a given
block.
Read Non-Volatile Protection Bit Status command (Read NVPB Status)
The status of a NVPB for a given block or group of bloc ks can be read by issuing a Read
Non-Volatile Modify Protection Bit command along with the block address.
Clear all Non-Volatile Protection Bits command (Clear all NVPBs)
The NVPBs are erased simultaneously by issuin g a Clear all Non-Volatile Protection Bits
command. No specific block address is required. If the NVPB Lock bit is set to ‘0’, the
command fails.
Numonyx® Axcell™ M29EW Command Interface
208031-05 51
Figure 12. NVPB Program/Erase algorithm
AI14242
YES
DQ6=
Toggle NO
YES
NO
Ent er NVPB
c omma nd s e t.
Program NVPB
A ddr = BA d
Read By te twi c e
A ddr = BA d
DQ5=1
Read By te twi c e
A ddr = BA d
NO
YES W ait 500 μs
DQ6=
Toggle Read By te tw i c e
A ddr = BA d
Fail
Reset Pass
DQ0=
'1'(Erase)
'0'(Program)
NO
Exit NVPB
c omma nd s e t
YES
Command Interface Numonyx® Axcell™ M29EW
52 208031-05
6.3.6 NVPB Lock Bit command set
Enter NVPB Lock Bit Command Set command
Three bus Write cycles are required to issue the Enter NVPB Lock Bit Command Set
command. Once the command has been issued, the commands allowing to set the NVPB
Lock bit can be issued to the device .
NVPB Lock Bit Program command
This command is used to set the NVPB Lock bit to ‘0’ thus locking the NVPBs , and
preventing them from be in g mo d ified .
Read NVPB Lock Bit Status command
This command is used to read the status of the NVPB Lock bit.
6.3.7 Volatile Protection mode command set
Enter Volatile Protection Command Set command
Three bus Write cycles ar e required to issue the Enter Volatile Protection Command Set
command. Once the command has been issued, the commands related to the Volatile
Protection mode can be issued to the device.
Volatile Protection Bit Program command (VPB Program)
The VPB Program command individually sets a VPB to ‘0’ for a giv en block.
If the NVPB f or the same block is set, the block is locked regardless of the v alue of the VPB
bit. (see Table 16: Block Protection Status).
Read VPB Status command
The status of a VPB for a given block can be read by issuing a Read VPB Status command
along with the block address.
VPB Clear command
The VPB Clear command individually clears (sets to ‘1’) the VPB for a given block.
If the NVPB f or the same block is set, the block is locked regardless of the value of the VPB
bit. (see Table 16: Block Protection Status).
6.3.8 Exit Protection command set
The Exit Protection Command Set command is used to exit from the Lock Register,
Password Protection, Non-Volatile Protection, Volatile Protection, and NVPB Lock Bit
Command Set mode. It return the device to Read mode.
Numonyx® Axcell™ M29EW Command Interface
208031-05 53
Table 13. Block Protection commands, 8-bit mode(1)(2)(3)
Command
Length
Bus operations
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
Ad Data Ad Data Ad Data Ad Data Ad Data Ad Data Ad Data Ad Data Ad Data Ad Data Ad Data
Lock Register
Enter Lock
Register
Command
Set(4) 3AAAAA55555AAA40----------------
Lock
Register
Program 2X A0 X
DATA
(5) - ------------- ----
Lock
Register
Read 1 X DATA
(5) - - - -----------------
Password Protection
Enter
Password
Protection
Command
Set(4)
3AAAAA55555AAA60------------- ---
Password
Program
(6)(7) 2X A0
PWA
nPWD
n- -------------- ---
Password
Read 800 PWD
001 PWD
102 PW
D2 03 PW
D3 04 PW
D4 05 PW
D5 06 PW
D6 07 PW
D7 - - - - - -
Password
Unlock(7) 11 00 25 00 03 00 PW
D0 01 PW
D1 02 PW
D2 03 PW
D3 04 PW
D4 05 PW
D5 06 PW
D6 07 PW
D7 00 29
Non-Volatile Protection
Enter Non-
Volatile
Protection
Command
Set(4)
3AAAAA55555AAAC0------------- ---
NVPB
Program(8) 2XA0BAd00- -------------- ---
Clear all
NVPBs(9) 2X800030- -------------- ---
Read
NVPB
Status (8) 1BAd RD(0)- - - -------------- ---
NVPB Lock bi t
Enter
NVPB Lock
Bit
Command
Set
3AAAAA55555AAA50------------- ---
NVPB Lock
Bit
Program(8) 2XA0X00- -----------------
Read
NVPB Lock
Bit Status
(8) 1 X RD(0)- - - -------------- ---
Volatile Protection
Enter
Volatile
Protection
Command
Set
3AAAAA55555AAAE0------------- ---
VPB
Program(8) 2XA0BAd00- -------------- ---
Read VPB
Status 1BAd RD(0)- - - -----------------
VPB
Clear(8) 2XA0BAd01- -------------- ---
Exit Protection
Command Set
(10) 2X90X00- -----------------
Enter Extended
Memor y Block(4) 3AAAAA55555AAA88------------- ---
Command Interface Numonyx® Axcell™ M29EW
54 208031-05
1. Ad = address; Dat = data; BAd = Any address in the Block; RD = Read data; PWDn = Password byte 0 to 7; PWAn =
Password Address (n = 0 to 7); X = Don’t care. All values in the table are in hexadecimal.
2. Grey cells represent Read cycles. The other cells are Write cycles.
3. DQ15 to DQ8 are ‘Don’t care’ during unlock and command cycles. Amax to A16 are ‘Don’t care’ during unlock and
command cycles unless an address is required.
4. An Enter command sequence must be issued prior to any operation. It disables read and write operations from and to block
0. Read and write operations from any othe r block are allowed.
5. DATA = Lock Register content.
6. Only one portion of password can be programmed or read by each Password Program command.
7. The password portion can be entered or read in any order as long as the entire 64-bit password is entered or read.
8. Protected and unprotected states correspond to 00 and 01, respectively.
9. The Clear all NVPBs command programs all NVPBs before erasure in order to prevent the over-erasure of previously
cleared Non Volatile Modify Protection bits.
10. If an Entry Command Set command is issued, an Exit Protection Command Set command must be issued to return the
device to Read mode.
Numonyx® Axcell™ M29EW Command Interface
208031-05 55
Table 14. Block Protection commands, 16-bit mode(1)(2)(3)
Command
Length
Bus operations
1st 2nd 3rd 4th 5th 6th 7th
Ad Data Ad Data Ad Data Ad Data Ad Data Ad Data Ad Data
Lock register
Enter Lock
Register
Command
Set(4) 3 555 AA 2AA 55 555 40 - - - - - - - -
Lock Register
Program 2X A0 XDATA
(5) ----------
Lock Register
Read 1XDATA
(5) ------------
Password Protection
Enter
Password
Protection
Command
Set(4)
3 555 AA 2AA 55 555 60 - - - - - - - -
Password
Program (6)(7) 2 X A0 PWAn PWDn - - - - - - - - - -
Password
Read 400 PWD0 01 PWD1 02 PWD2 03 PWD3 - - - - - -
Password
Unlock(7) 7 00 25 00 03 00 PWD0 01 PWD1 02 PWD2 03 PWD3 00 29
Non-Volatile Protection
Enter Non-
Volatile
Protection
Command
Set(4)
3 555 AA 2AA 55 555 C0 - - - - - - - -
NVPB
Program(8) 2 X A0 BAd 00 - - - - - - - - - -
Clear all
NVPBs(9) 2 X 80 00 30 - - - - - - - - - -
Read NVPB
Status 1BAd RD(0)------------
NVPB Lock bit
Enter NVPB
Lock Bit
Command Set 3 555 AA 2AA 55 555 50 - - - - - - - -
NVPB Loc k Bit
Program 2X A0 X 00 - - - - - - - - - -
Read NVPB
Lock Bi t Status 1XRD(0)------------
Volatile Protection
Enter Volatile
Protection
Command Set 3 555 AA 2AA 55 555 E0 - - - - - - - -
VPB Progra m 2 X A0 BAd 00 - - - - - - - - - -
Read VPB
Status 1BAd RD(0)------------
VPB Clear 2 X A0 BAd 01 - - - - - - - - - -
Exit Protection
Command Set(10) 2X 90 X 00 - - - - - - - - - -
Enter Extended
Memory Block(4) 3 555 AA 2AA 55 555 88 - - - - - - - -
Exit Extended
Memory Block 4 555 AA 2AA 55 555 90 X 00 - - - - - -
Command Interface Numonyx® Axcell™ M29EW
56 208031-05
1. Ad = address; Dat = data; BAd = Any address in the Block; RD = Read data; PWDn = Password byte 0 to 3; PWAn =
Password Address (n = 0 to 3); X = Don’t care. All values in the table are in hexadecimal.
2. Grey cells represent Read cycles. The other cells are Write cycles.
3. DQ15 to DQ8 are ‘Don’t care’ during unlock and command cycles. Amax to A16 are ‘Don’t care’ during unlock and
command cycles unless an address is required.
4. An Enter command sequence must be issued prior to any operation. It disables read and write operations from and to block
0. Read and write operations from any othe r block are allowed.
5. DATA = Lock Register content.
6. Only one portion of password can be programmed or read by each Password Program command.
7. The password portion can be entered or read in any order as long as the entire 64-bit password is entered or read.
8. Protected and unprotected states correspond to 00 and 01, respectively.
9. The Clear all NVPBs command programs all NVPBs before erasure in order to prevent the over-erasure of previously
cleared Non-volatile Modify Protection bits.
10. If an Entry Command Set command is issued, an Exit Protection Command Set command must be issued to return the
device to Read mode.
Numonyx® Axcell™ M29EW Registers
208031-05 57
7 Registers
The device features two registers:
1. A Lock Register that allows to configure the memory blocks and Extended Memory
Block pr otection (see Table 16: Block Protection Status)
2. A Status Register that provides information on the current or pr evious Program or
Erase operations.
7.1 Lock Register
The Loc k Regi ster is a 16-bit one- time prog r a mmable register. The bits in the Loc k Regist er
are summarized in Table 15: Lock Register bits.
See Section 6.3.3: Loc k Register command set for a descrip tio n of the co mm a nd s allowing
to read and program the Lock Register.
7.1.1 Password Protection Mode Lock bit (DQ2)
The Passwor d Protection Mode Lock bit, DQ0, is one-time programmable. Programming
(setting to ‘0’) this bit permanently places the device in Password Protection mode.
Any attempt to program the Password Protection mode Lock bit when the Non-Volatile
Protection Mode bit is prog rammed causes the oper ation to ab ort and th e de vice to return to
Read mode.
7.1.2 Non-Volatile Protection Mode Lock bit (DQ1)
The Non-Volatile Protection Mode Lock bit, DQ1, is one-time programmable. Programming
(setting to ‘0’) this bit permanently places the device in Non-Volatile Protection mode.
When shipped from Numonyx factory, all parts default to operate in Non-Volatile Protection
mode. The memory blocks are unprotected (NVPBs set to ‘1’).
Any attempt to program the Non-Volatile Protection mode Lock bit when the Password
Protection Mode bit is prog rammed causes the oper ation to ab ort and th e de vice to return to
Read mode.
7.1.3 Extended Memory Block Protection bit (DQ0)
If the device is shipped with the Extended Memory Block unlocked, the block can be
protected b y setting the Extend ed Memory Bloc k Protection bit, DQ0, to ‘0’. Howe v er , this bit
is one-time programmable and once protected the Extended Memory Block cannot be
unprotected any more.
The Extended Memory Block protection status can be read in Auto Select mode by issuing
an Auto Select command (see Table 9 and Table 10).
Registers Numonyx® Axcell™ M29EW
58 208031-05
Table 15. Lock Register bits(1)
DQ15-3(2) DQ2 DQ1 DQ0
Reserved P assword Protection Mode Lock
bit Non-Volatile Protection Mode
Lock bit Extended Memory
Block Protection bit
1. DQ0, DQ1 and DQ2 Lock Register bits are set to ‘1’ when shipped from the Numonyx.
2. DQ15 to DQ3 are reserved and default to ‘1’.
Table 16. Block Protection Status
NVPB Lock bit(1) Block
NVPB(2) Block
VPB(3)
Block
protection
status Block Protection Status
1 1 1 00h Block unprotected (NVPB changeable)
1 1 0 01h Block protected by VPB (NVPB changeable)
1 0 1 01h Block protected by NVPB (NVPB changeable)
10001h
Block protected by NVPB and VPB (NVPB
changeable)
0 1 1 00h Block unprotected (NVPB un changeable)
0 1 0 01h Block protected by VPB (NVPB unchangeable)
00101h
Block protected by NVPB (NVPB
unchangeable)
00001h
Block protected by NVPB and VPB (NVPB
unchangeable)
1. If the NVPB Lock bit is set to ‘0’, all NVPBs are locked. If the NVPB Lock bit is set to ‘1’, all NVPBs are unlocked.
2. If the Block NVPB is set to ‘0’, the block is protected, if set to ‘1’, it is unprotected.
3. If the Block VPB is set to ‘0’, the block is protected, if set to ‘1’, it is unprotected.
Numonyx® Axcell™ M29EW Registers
208031-05 59
Figure 13. Lock Register program flow chart
1. PD is the programmed data (see Table 15: Lock Register bits).
2. Each bit of the Lock Register can only be programmed once.
START
PASS:
Write Lock Register Exit command:
Add Dont' care, Data 90h
Add Dont' care, Data 00h
ai13677
Done
YES
YES
NO
DQ5 = 1 NO
Write Unlock cycles:
Add 555h, Data AAh
Add 2AAh, Data 55h Unlock cycle 1
unlock cycle 2
Write
Enter Lock Register command set:
Add 555h, Data 40h
Program Lock Register Data:
Add Dont' care, Data A0h
Add Dont' care(1), Data PDh
Polling algorithm
Device returned
to Read mode FAIL
Reset to return
the device to Read mode
Registers Numonyx® Axcell™ M29EW
60 208031-05
7.2 Status Register
The M29EW de vice has one Status Registe r . The v arious bits conv ey inf ormation and errors
on the current and previous progr am/erase operation. Bus Read operations from any
address within the memory, always read the Status Register during Program and Erase
operations. It is also read during Erase Suspend when an address within a block being
erased is accessed.
The bits in the Status Register are summarized in Table 17: Status Register bits.
7.2.1 Data Polling bit (DQ7)
The Data Polling bit can be used to identify whether the Program/Erase controller has
successfully completed its operation or if it has responded to an Er ase Suspend. The Data
Polling bit is output on DQ7 when the Status Register is read.
During Program operations the Data Polling bit outputs the complement of the bit being
programmed to DQ7. After successful completion of the Program operation the memory
returns to Read mode and Bus Read oper ations , from the ad dress just progr ammed , output
DQ7, not its complement.
During Erase or Blank Check operations the Data Polling bit outputs ‘0’, the complement of
the erased state of DQ7. When the algorithm is complete, Data Polling produces a '1' on
DQ7. After successful completion of the Erase or Blank Check operation the memory
returns to Read mode.
In Erase Suspend mode the Data Po lling bit will output a ‘1’ during a Bus Read operation
within a block being erased. The Data Polling bit will change from ‘0’ to ‘1’ when the
Program/Erase controller has suspended the Erase operation.
Figure 14: Data polling flow chart, gives an example of how to use the Data Polling bit. A
Valid Addre ss is the address being progra mmed or an address within the b lock being er ased
or blank checked.
7.2.2 Toggle bit (DQ6)
The Toggle bit can be used to identify whether t he Program/Erase controller has
successfully completed its operation or if it has responded to an Er ase Suspend. The Toggle
bit is output on DQ6 when the Status Register is read.
During a Program/Erase operat ion the Toggle bit changes from ‘0’ to ‘1’ to ‘0’, etc., with
successive Bus Read operations at any address . After successful completion of the
operation the memory returns to Read mode.
During Erase Suspend mode the Toggle bit will output when addressing a cell within a block
being erased. The Toggle bit will stop toggling when the Program/Erase controller has
suspended the Erase operation.
Figure 15: Toggle flow chart, gives an example of how to use the Data Toggle bit.
7.2.3 Error bit (DQ5)
The Error bit can be used to ident ify errors detected by the Prog ram/Erase con troller. The
Error bit is set to ‘1’ when a Program, Block Erase or Chip Erase operation fails to write the
correct data to the me m ory, or a Blan k Che ck operation fails. If the Error bit is set a
Numonyx® Axcell™ M29EW Registers
208031-05 61
Read/Reset command must be issued before other commands are issued. The Error bit is
output on DQ5 when the Status Register is read.
Note that the Prog ram command cannot change a bit se t to ‘0 ’ back to ‘1’ and attemptin g to
do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’.
One of the Erase commands must be used to set all the bits in a block or in the whole
memory from ‘0’ to ‘1’.
7.2.4 Erase Timer bit (DQ3)
The Erase Timer bit can be used to identify the start of Program/Erase controller operation
during a Block Er ase command. Once the Pro gram/Erase controller starts erasing the Erase
Timer bit is set to ‘1’. Before the Program/Er ase controlle r starts the Er ase Timer bit is set to
‘0’ and additional blocks to be erased may be written to the command interface. The Erase
Timer bit is output on DQ 3 when the Status Register is read.
7.2.5 Alternative Toggle bit (DQ2)
The Alternative Toggle bit can be used to monitor the Pro gram/Erase contr oller during Er ase
operations. The Alternativ e Toggle bit is output on DQ2 when the Status Register is read.
During Chip Erase and Block Erase operations the Toggle bit changes from ‘0’ to ‘1’ to ‘0’,
etc., with successiv e Bus Read operations from ad dresses within the b locks being er ased. A
protected block is treated the same as a block not being erased. Once the operation
completes the memory returns to Read mode.
During Erase Suspend the Alternative Toggle bit changes from ‘0’ to ‘1’ to ‘0’, etc. with
successive Bus Read ope r at ion s f rom addre sses within the bloc ks bei ng erased. Bus Read
operat ions to addresses within bloc ks not being er ased will output the mem ory arra y data as
if in Read mode.
After an Erase operation that causes the Error bit to be set, the Alternativ e Toggle bit can be
used to identify which block or blocks have caused the error. The Alternative Toggle bit
changes from ‘0’ to ‘1’ to ‘0’, etc. with successive Bus Read Operations from addresses
within blocks that have not erased correctly. The Alternative Toggle bit does not ch ange if
the addressed block has erased correctly.
7.2.6 Buffered Program Abort bit (DQ1)
The Buffered Program Abort bit, DQ1, is set to ‘1’ when a Buffer Program operation aborts.
The Buffered Program Abort and Reset command must be issued to re turn the device to
Read mode (see Write to Buffer Program in Section 6.1: Standard commands).
For the complete polling flow chart, please refer to Figure 16.: Status Register polling flow
chart.
Registers Numonyx® Axcell™ M29EW
62 208031-05
Table 17. Status Register bits(1)
Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 RY/BY#
Program(2) Any address DQ7 Toggle 0 – No
Toggle 00
Program During Erase Suspend Any address DQ7 Toggle 0 – – – 0
Buff ered Prog ram Abort(2) Any address DQ7 Toggle 0 – – 1 0
Program Error Any address DQ7 Toggle 1 – – – Hi-Z
Chip Erase Any address 0 Toggle 0 1 Toggle – 0
Block Erase before timeout Erasing block 0 Toggle 0 0 Toggle – 0
Non-erasing
block 0 Toggle 0 0 No
toggle –0
Block Erase/Blank Check
Erasing/Verifying
block 0 Toggle 0 1 Toggle – 0
Non-
erasing/Verifying
block 0 Toggle 0 1 No
toggle –0
Erase/Blank Check Suspend
Erasing/Verifying
block 1 No Toggle 0 – Toggle – Hi-Z
Non-
erasing/Verifying
block Data read as normal – Hi-Z
Erase/Blank Check Error
Good block
address 0 Toggle 1 1 No
toggle – Hi-Z
Faulty Block
address 0 Toggle 1 1 Toggle – Hi-Z
1. Unspecified data bits should be ignored.
2. DQ7 for Buffer Program is related to the last address location loaded.
Numonyx® Axcell™ M29EW Registers
208031-05 63
Figure 14. Data polling flow chart
READ DQ5 & DQ 7
at V ALID ADDRESS
START
READ DQ7
at V ALID ADDRESS
FAIL PASS
AI07760
DQ7
=
DATA YES
NO
YES
NO
DQ5 = 1
DQ7
=
DATA YES
NO
DQ = 1
YES
NO
Registers Numonyx® Axcell™ M29EW
64 208031-05
Figure 15. Toggle flow chart
READ DQ6 at
Valid Address
START
READ DQ6
TWICE
at Valid Address
FAIL PASS
AI11530
DQ6
=
TOGGLE NO
NO
YES
YES
DQ5
= 1
NO
YES
DQ6
=
TOGGLE
READ
DQ5 & DQ6
at Valid Address
Numonyx® Axcell™ M29EW Registers
208031-05 65
Figure 16. Status Register polling flow chart
Read 1
Read 2
Start
DQ7=Valid
Data?
DQ5=1?
Timeout failure
Device Busy, Re-
Poll
DQ6
toggling?
DQ1=1? Write Buffer
Program Abort
Device Busy, Re-
Poll
Read 3 P rogramming
Operation? Read3 correct
data?
Programming
Operation
Complete
Programming
Operation Failed
DQ6
toggling? DEVICE ERROR
DQ2
toggling?
Read1.DQ6 ≠
Read2.DQ6
Read2.DQ6 ≠
Read3.DQ6
Read2.DQ2 ≠
Read3.DQ2
No
Yes Yes Yes
No
Yes
No
No
Yes
Yes
No
No
Yes
No
Device in Erase/
Suspend Mode
Erase Complete
Yes
No
Invalid state use
RESET comand
Read 2
Read 3
Write Buffer
Programming Yes
No
Maximum Ratings Numonyx® Axcell™ M29EW
66 208031-05
8 Maximum Ratings
Stressing the device above the rating listed in Table 18: Absolute maximum r atings may
cause permanent damage to the device. Exposure t o absolute maximum rating conditions
for extended periods may affect device reliability. These are stress ratings only and
operation of the device at these or any other conditions above those indicated in the
operating sections of this specification is not implied. Refer also to the rele vant quality
documents from Numonyx.
Table 18. Absolute maximum ratings
Symbol Parameter Min Max Unit
TBIAS Temperature under bias −40 85 °C
TSTG Storage temperature −65 125 °C
VIO Input or output voltage(1)(2) −0.6 VCC +0.6 V
VCC Supply voltage(1)(2) −25.6V
VCCQ Input/output supply voltage(1)(2) −25.6V
VPPH(3) Program voltage(1)(2) −214.5V
1. Minimum voltage may undershoot to −2 V during transition and for less than 20ns during transitions.
2. Maximum voltage may overshoot to VCC + 2 V during transition and for less than 20ns during transitions.
3. VPPH must not remain at 12 V for more than a cumulative total of 80hrs.
Numonyx® Axcell™ M29EW DC and AC Parameters
208031-05 67
9 DC and AC Parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 19: Operating and AC measurement con ditions. Designers sho u ld che ck that the
operat ing conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Figure 17. AC measurement load circuit
Figure 18. AC measurement I/O waveform
Table 19. Operating and AC measurement conditions
Parameter Min Max Unit
VCC supply voltage 2.7 3.6 V
VCCQ supply voltage (VCCQ ≤VCC)1.73.6V
VPP supply voltage -0.6 12.5 V
Ambient operating temp erature − 40 85 °C
Load capacitance (CL)30pF
Input rise and fall times - 2.5 ns
Input pulse voltages 0 to VCCQ V
Input and output timing ref. voltages VCCQ/2 V
AI05558b
CL
CL includes JIG capacitance
DEVICE
UNDER
TEST
25 kΩ
VCCQ
25 kΩ
VCC
0.1 µF
VPP
0.1 µF
AI05557b
VCCQ
0 V
VCCQ/2
DC and AC Parameters Numonyx® Axcell™ M29EW
68 208031-05
Figure 19. Power-up wait timings
Table 20. Power-up wait timings
Symbol Alt. Parameter Limit Value Unit
tVCHVCQH -V
CC(1) High to VCCQ(1) High Min 0 µs
tVCHPH(2) tVCS VCC High to rising edge of RST# Min 60 µs
tVCQHPH(2) tVIOS VCCQ High to rising edge of RST# Min 0 µ s
tPHEL tRH RST# High to Chip Enable Low Min 50 ns
tPHWL - RST# High to Write Enable Low Min 150 ns
1. VCC and VCCQ ramps must be synchronized during power-up.
2. If RST# is not stable for tVCHRH or tVCQHRH, the device does not permit any Read and Write operations and a hardware
reset is required.
AI14247
V
CC
RST#
t
VCHPH
t
PHEL
CE#
V
CCQ
t
VCQHPH
WE#
t
VCHVCQH
t
PHWL
Numonyx® Axcell™ M29EW DC and AC Parameters
208031-05 69
Table 21. Device capacitance(1)
Symbol Parameter Test condition Min Max Unit
CIN Input capacitance VIN = 0 V 2 7 pF
COUT Output capacitance VOUT = 0 V 2 5
1. Sampled only, not 100% tested.
Table 22. DC characteristics
Symbol Parameter Test condition Min Typ Max Unit
ILI(1) Input leakage current 0 V ≤ VIN ≤ VCC --±1µA
ILO Output leakage current 0 V ≤ VOUT ≤ VCC --±1µA
ICC1 Read current
Random
Read CE# = VIL, OE# = VIH,
f=5MHz -2025mA
Page
Read CE# = VIL, OE# = VIH,
f=13MHz -1216mA
ICC2 Supply current
(Standby)
128-Mbit CE# = VCCQ ±0.2V
RST# = VCCQ ±0.2V
-50120
µA64-Mbit - 35 120
32-Mbit - 35 120
ICC3(2) Supply current
(Program/Erase/Blank
Check)
Program/Erase
controller activ e
VPP/WP# =
VIL or VIH -3550mA
VPP/WP#=VPPH -2633mA
IPP1
Vpp Current
Read VPP/WP# ≤VCC - 2 15 µA
Standby VPP/WP# ≤VCC -0.25µA
IPP2 Reset RST# = VSS ± 0.2 V - 0.2 5 µA
IPP3
Program
operation
ongoing
VPP/WP#=12V±5% - 5 10 mA
VPP/WP# = VCC -0.050.10mA
IPP4
Erase
operation
ongoing
VPP/WP#=12V±5% - 5 10 mA
VPP/WP# = VCC -0.050.10mA
VIL Input Low voltage VCC ≥2.7 V −0.5 - 0.8 V
VIH Input High voltage VCC ≥2.7 V 2 - VCCQ+0.5 V
VOL Output Low voltage IOL = 100 µA, VCC =V
CC(min),
VCCQ =V
CCQ(min) --0.2V
VOH Output High voltage IOH = -100 µA, VCC =V
CC(min),
VCCQ =V
CCQ(min) VCCQ−0.2 - - V
VPPLK VPP Lock-Out voltage - - - 0.4 V
VPPH Voltage for VPP/WP#
Program acceleration - 11.5 - 12.5 V
VPPL VPP logic level 2.7 - 3.6 V
VLKO(2) Program/Erase lockout
supply voltage -2.3--V
1. The maximum input leakage current is ±5 µA on the VPP/WP# pin.
2. Sampled only, not 100% tested.
DC and AC Parameters Numonyx® Axcell™ M29EW
70 208031-05
Figure 20. Random Read AC waveforms (8-bit mode)
Figure 21. Random Read AC waveforms (16-bit mode)
AI13698
tAVAV
tAVQV tAXQX
tELQX tEHQZ
tGLQV
tGLQX tGHQX
VALID
A0-AMAX/A-1
OE#
DQ0-DQ7
CE#
tELQV tEHQX
tGHQZ
VALID
tELBL tBLQZ
BYTE#
AI08970
tAVAV
tAVQV tAXQX
tELQX tEHQZ
tGLQV
tGLQX tGHQX
VALID
A0-AMAX
OE#
DQ0-DQ15
CE#
tELQV tEHQX
tGHQZ
VALID
tELBH
BYTE#
Numonyx® Axcell™ M29EW DC and AC Parameters
208031-05 71
Figure 22. Byte Transition AC waveform
1. CE# and OE# are VIL.
Figure 23. Page Read AC waveforms (16-bit mode)
tAXQX
tBHQV
A0-AMAX
BYTE#
tAVQV
tBLQX
tBLQZ
VALID
Hi-Z
A–1
DATA OUT
DATA OUT
VALID
DQ0-DQ7
DQ8-DQ15
Byte_Transition_AC-Waveform
AI08971c
VALID
A4-Amax
OE#
DQ0-DQ15
CE#
tELQV
VALID
A0-A3 VALID VALID VALID
VALID VALID
tGLQV
tAVQV
tAVQV1
tEHQZ
tGHQX
tEHQX
tGHQZ
VALID
VALID
VALID
VALID
Table 23. Read AC characteristics (Sheet 1 of 2)
Symbol Alt. Parameter Test
condition Limit BGA TSOP Unit
tAVAV tRC Address Valid to Next Address
Valid CE# = VIL,
OE# = VIL Min 60 70 ns
tAVQV tACC Address Va lid to Output Valid CE# = VIL,
OE# = VIL Max 60 70 ns
tAVQV1 tPAGE Address Valid to Output Valid
(Page) CE# = VIL,
OE# = VIL Max 25 ns
tELQX(1) tLZ Chip Enable Low to Output
Transition OE# = VIL Min 0 ns
tELQV tEChip Enable Low to Output Valid OE# = VIL Max 60 70 ns
tGLQX(1) tOLZ Output Enable Low to Output
Transition CE# = VIL Min 0 ns
DC and AC Parameters Numonyx® Axcell™ M29EW
72 208031-05
Figure 24. Write Enable Controlled Program waveforms (8-bit mode)
1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check
of Status Register Data Polling bit and by a read operation that outputs the data, DOUT, programmed by the previous
Program command.
2. PA is the address of the memory location to be programmed. PD is the data to be programmed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (see Section 7.2.1: Data Polling bit (DQ7)).
4. SeeTable 24: Write AC characteristics, Write Enable C ontrolle d, Table 25: Write AC characteristics, Chip Enable
Controlled and Table 23: Read AC characteristics (Sheet of 2) for details on the timings.
tGLQV tOE Output Enable Low to Output Valid CE# = VIL Max 25 ns
tEHQZ(1) tHZ Chip Enable High to Output Hi-Z OE# = VIL Max 20 ns
tGHQZ(1) tDF Output Enable High to Output Hi-Z CE# = V IL Max 15 ns
tEHQX
tGHQX
tAXQX
tOH
Chip Enable, Output Enable or
Address Transition to Output
Transition -Min 0 ns
tELBL
tELBH
tELFL
tELFH
Chip Enable to BYTE# Low or
High - Max 10 ns
tBLQV tFLQV BYTE# Low to Output Valid - Max 1 µs
tBHQV tFHQV BYTE# High to Output Valid - Max 1 µs
tBLQZ tFLQZ BYTE# Low to Output in high Z - Max 1 µs
1. Sampled only, not 100% tested.
Table 23. Read AC characteristics (Sheet 2 of 2)
Symbol Alt. Parameter Test
condition Limit BGA TSOP Unit
AI13333
OE#
WE#
A0-Amax/A–1
DQ0-DQ7
CE#
AAAh
AOh
PA PA
3rd cycle 4th cycle
PD DQ7 DOUT
DOUT
tAVAV tAVAV
tAVWL tWLAX
D a ta Polling Read cycle
tELWL tWHEH tELQV
tGHWL
tWLWH tWHWL
tWHWH1
tGLQV
tDVWH
tWHDX
tGHQZ tAXQX
Numonyx® Axcell™ M29EW DC and AC Parameters
208031-05 73
Figure 25. Write Enable Controlled Program waveforms (16-bit mode)
1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check
of Status Register Data Polling bit and by a read operation that outputs the data, DOUT, programmed by the previous
Program command.
2. PA is the address of the memory location to be programmed. PD is the data to be programmed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (see Section 7.2.1: Data Polling bit (DQ7)).
4. SeeTable 24: Write AC characteristics, Write Enable C ontrolle d, Table 25: Write AC characteristics, Chip Enable
Controlled and Table 23: Read AC characteristics (Sheet of 2) for details on the timings.
AI13699
OE#
WE#
A0-Amax
DQ0-DQ15
CE#
555h
AOh
PA PA
3rd cycle 4th cycle
PD DQ7 DOUT
DOUT
tAVAV tAVAV
tAVWL tWLAX
Data Polling Read cycle
tELWL tWHEH tELQV
tGHWL
tWLWH tWHWL
tGLQV
tDVWH
tWHDX
tGHQZ tAXQX
DC and AC Parameters Numonyx® Axcell™ M29EW
74 208031-05
M
Table 24. Write AC characteristics, Write Enable Controlled
Symbol Alt Parameter Limit BGA TSOP Unit
tAVAV tWC Address Valid to Next Address Valid Min 60 70 ns
tELWL tCS Chip Enable Low to Write Enable Low Min 0 ns
tWLWH tWP Write Enable Low to Write Enable High Min 35 ns
tDVWH tDS Input Valid to Write Enable High Min 30 ns
tWHDX tDH Write Enab le High to Input Transition Min 0 ns
tWHEH tCH Write Enab le High to Chip Enable High Min 0 ns
tWHWL tWPH Write Enable High to Write Enable Low Min 20 ns
tAVWL tAS Address Valid to Write Enable Low Min 0 ns
tWLAX tAH Write Enabl e Low to Address Transition Min 45 ns
tGHWL - Output Enable High to Write Enable Low Min 0 ns
tWHGL tOEH Write Enable High to Output Enable Low Min 0 ns
tWHRL(1) tBUSY Program/Erase Valid to RY/BY# Low Max 90 ns
tVCHEL tVCS VCC High to Chip Enable Low Min 60 µs
1. Sampled only, not 100% tested.
Numonyx® Axcell™ M29EW DC and AC Parameters
208031-05 75
Figure 26. Chip Enable Controlled Program waveforms (8-bit mode)
1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check
of Status Register Data Polling bit.
2. PA is the address of the memory location to be programmed. PD is the data to be programmed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (see Section 7.2.1: Data Polling bit (DQ7)).
4. See Table 24: Write AC characteristics, Write Enable Controlled, Table 25: Write AC characteristics, Chip Enable
Controlled and Table 23: Read AC characteristics (Sheet of 2) for details on the timings.
AI13334
OE#
CE#
A0-Amax/A–1
DQ0-DQ7
WE#
AAAh
AOh
PA PA
3rd cycle 4th cycle
PD DQ7 DOUT
tAVAV
tAVEL tELAX
D a ta Polling
tWLEL tEHWH
tGHEL
tELEH tEHEL1
tWHWH1
tDVEH
tEHDX
DC and AC Parameters Numonyx® Axcell™ M29EW
76 208031-05
Figure 27. Chip Enable Controlled Program waveforms (16-bit mode)
1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check
of Status Register Data Polling bit.
2. PA is the address of the memory location to be programmed. PD is the data to be programmed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (see Section 7.2.1: Data Polling bit (DQ7)).
4. See Table 24: Write AC characteristics, Write Enable Controlled, Table 25: Write AC characteristics, Chip Enable
Controlled and Table 23: Read AC characteristics (Sheet of 2) for details on the timings.
AI14100
OE#
CE#
A0-Amax
DQ0-DQ15
WE#
555h
AOh
PA PA
3rd cycle 4th cycle
PD DQ7 DOUT
tAVAV
tAVEL tELAX
Data Polling
tWLEL tEHWH
tGHEL
tELEH tEHEL1
tDVEH
tEHDX
Numonyx® Axcell™ M29EW DC and AC Parameters
208031-05 77
Figure 28. Chip/Block Erase wa veforms (8-bit mode)
1. For a Chip Erase command, addresses and data are 555h and 10h, respectively, while they are BAd and 30h for a Block
Erase command.
2. BAd is the block address.
3. See Table 24: Write AC characteristics, Write Enable Controlled, Table 25: Write AC characteristics, Chip Enable
Controlled and Table 23: Read AC characteristics (Sheet of 2) for details on the timings.
AI13335
OE#
WE#
DQ0-DQ7
CE#
555h
AAh
2AAh 555h
55h 80h AAh
tAVAV
tAVWL tWLAX
tELWL tWHEH
tGHWL
tWLWH tWHWL
tDVWH
tWHDX
555h 2AAh 555h/BAd
(1)
55h 10h/
30h
A0-Amax/A-1
Table 25. Write AC characteristics, Chip Enable Controlled
Symbol Alt. Parameter Limit BGA TSOP Unit
tAVAV tWC Address Valid to Next Address Valid Min 60 70 ns
tWLEL tWS Write Enable Low to Chip Enable Low Min 0 ns
tELEH tCP Chip Enable Low to Chip Enable High Min 35 ns
tDVEH tDS Input Valid to Chip Ena ble High Min 30 ns
tEHDX tDH Chip Enable High to Input Transition Min 0 ns
tEHWH tWH Chip Enable High to Write Enable High Min 0 ns
tEHEL tCPH Chip Enable High to Chip Enable Low Min 20 ns
tAVEL tAS Address Valid to Chip Enable Low Min 0 ns
tELAX tAH Chip Enable Low to Address Transition Min 45 ns
tGHEL - Output Enable High Chip Enable Low Min 0 ns
DC and AC Parameters Numonyx® Axcell™ M29EW
78 208031-05
Figure 29. Reset AC waveforms (no program/erase in progress)
Figure 30. Reset AC waveforms (during program/erase operation)
Figure 31. Accelerated program timing waveforms
AI11300b
RY/ BY#
RST# tPLPH
tPHEL,
tPHGL
CE#, OE#
AI11301b
RY/ BY#
RST#
tPLPH
tRHEL, tRH GL
CE#,OE#
tPLRH
Table 26. Reset AC characteristics
Symbol Alt. Parameter Min Max Unit
tPLRH(1) tREADY RST# Low to Read mode, during Program or Erase - 2 5 µs
tPLPH tRP RST# Pulse width 100 - ns
tPHEL, tPHGL(1) tRH RST# High to Chip Enable Low, Output Enable Low 50 - ns
-t
RPD RST# Low to Standby mode, during Read mode 10 - µs
RST# Low to Standby mode, during Program or Erase 50 - µs
tRHWL, tRHEL,
tRHGL(1) tRB RY/BY# High to Write Enable Low, Chip Enable Low,
Output Enable Low 0-ns
1. Sampled only, not 100% tested.
AI05563
VPP/WP#
VPPH
VIL or VIH tVHVPP tVHVPP
Numonyx® Axcell™ M29EW DC and AC Parameters
208031-05 79
Figure 32. Data polling AC waveforms
1. DQ7 returns valid data bit when the ongoing Program or Erase command is completed.
2. See Table 27: Accelerated Program and Data Polling/Data Toggle AC characteristics and Table 23: Read AC
characteristics (Sheet of 2) for details on the timings.
Figure 33. Toggle/Alternat ive Toggle bit polling AC waveforms (8-bit mode)
1. DQ6 stops toggling when the ongoing Program or Erase command is completed. DQ2 stops toggling when the in-progress
Chip Erase or Block Erase command is completed.
2. See Table 27: Accelerated Program and Data Polling/Data Toggle AC characteristics and Table 23: Read AC
characteristics (Sheet of 2) for details on the timings.
AI13336c
OE#
CE#
DQ7
WE#
DQ6-DQ0
DATA
DATA
RY/BY#
tWHEH
tGLQV
tEHQZ
tGHQZ
tWHGL2
tELQV
tWHRL
Output Flag
Valid DQ7 Data
Valid DQ6-DQ0
Data
Output Flag
DQ7
DQ7
AI13337
WE#
CE#
OE#
DQ6/DQ2 Toggle Toggle Toggle Stop
toggling Output
Valid
tGHAX tAXGL
tEHAX tAVEL
tEHEL2
tWHGL2
tGHGL2 tGHGL2
Data
RY/BY#
tWHDX tGLQV tELQV
tWHRL
A0-Amax/A-1
DC and AC Parameters Numonyx® Axcell™ M29EW
80 208031-05
Table 27. Accelerated Program and Data Polling/Data Toggle AC characteristics
Symbol Alt Parameter Min Max Unit
tVHVPP -V
PP/WP# raising or falling time 250 - ns
tVHHWH -Valid V
HH on VPP/WP# to WE# high 50 - ns
tAXGL tASO Address setup time to Output Enable Low during Toggle bi t polling 15 - ns
tGHAX,
tEHAX tAHT Address hold time from Output Enable during Toggle bit polli ng 0 - ns
tEHEL2 tEPH Chip Enable High during Toggle bit polling 20 - ns
tWHGL2,
tGHGL2 tOEH Output Hold time during Data and Toggle bit polling 20 - ns
tWHRL tBUSY Program/Erase Valid to RY/BY# Low - 90 ns
Numonyx® Axcell™ M29EW Programming and Erase Performance
208031-05 81
10 Programming and Erase Performance
Table 28. Programming and Erase Performance
Parameter Buffer
Size Byte Word Min Typ(1)(2) Max(2) Unit
Block Erase - - - - 0.5 4 s
Erase Suspend latency - - - - 20 25 µs
Block Erase time-out - - - 50 - - µs
Byte Program
Single Byte Program - - - - 15 175 µs
Double / Quadruple /
Octuple Byte
Program - - - - 10 200 µs
Byte Write to Buffer
Program
32 32 - - 70 200
µs64 64 - - 85 200
256 256 - - 160 710
Eff ective Write to
Buffer Program per
Byte
32 1 - - 2.19 6.25
µs64 1 - - 1.33 3.125
256 1 - - 0.625 2.77
Wo rd Progr am
Single Word Program - - - - 15 175 µs
Word Write to Buffer
Program
16 - 16 - 70 200
µs
32 - 32 - 85 200
128 - 128 - 160 710
256 - 256 - 284 1280
Full Buffer Program
With VPPH 256 - 256 - 160 800 µs
Eff ective Write to
Buffer Program per
Word
16 - 1 - 4.375 12.5
µs
32 - 1 - 2.66 6.25
128 - 1 - 1.25 5.55
256 - 1 - 1.11 5
Eff ective Full Buffer
Program per Word
With VPPH
256 - 1 - 0.625 3.125 µs
Program Suspend latency - - - - 20 25 µs
Blank Check - - - - 3.2 - ms
Program/Erase cycles (per block) - - - 100,000 - - Cycles
1. Typical values measured at room temperature and nominal voltages.
2. Sampled, but not 100% tested.
Package Mechanical Specifications Numonyx® Axcell™ M29EW
82 208031-05
11 Package Mechanical Specifications
Numonyx offers these devices in both lead-free and leaded packages. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also mark ed on the inner box label.
Figure 34. TSOP56 – 56 lead thi n small-outl ine pac kage,14 x 20 mm, pac kage outli ne
1. Drawing is not to scale.
TSOP-b
D1
E
1 N
CP
B
e
A2
A
N/2
D
DIE
C
LA1 α
Table 29. TSOP56 – 56 lead thin sm all-outline package, 14 x 20 mm, package mechanical data
Symbol Millimeters Inches
Typ Min Max Typ Min Max
A – – 1.20 – – 0.047
A1 – 0.05 – – 0.002 –
A2 0.995 0.965 1.025 0.039 0.038 0.040
B(1) 0.22 0.17 0.27 0.0087 0.0067 0.0106
C 0.125 0.115 0.135 0.0049 0.0045 0.0053
CP – – 0.10 – – 0.004
E 14.00 13.80 14.20 0.551 0.543 0.559
D 20.00 19.80 20.20 0.787 0.780 0.795
D1 18.40 18.20 18.60 0.724 0.717 0.732
e 0.50 – – 0.020 – –
L 0.60 0.50 0.70 0.024 0.020 0.028
α3o0o5o3o0o5o
Ν56
1. For legacy lead width, 0.15mm (Typ), 0.10mm (Min), 0.20mm (Max).
Numonyx® Axcell™ M29EW Package Mechanical Specifications
208031-05 83
Figure 35. TSOP48 – 48 lead thin small-outline packa ge, 12 x 20 mm, package
outline
1. Drawing is not to scale.
Table 30. TSOP48 – 48 lead thin small-outline package, 12 x 20 mm, packa ge
mechanical data
Symbol millimeters
Typ Min Max
A– –1.20
A1 0.10 0.05 0.15
A2 1.00 0.95 1.05
B 0.22 0.17 0.27
C – 0.10 0.21
CP – – 0.10
E 12.00 11.90 12.10
D 20.00 19.80 20.20
D1 18.40 18.30 18.50
e0.50 – –
L 0.60 0.50 0.70
α3o0o5o
Ν48
TSOP-b
D1
E
1 N
CP
B
e
A2
A
N/2
D
DIE
C
LA1 α
Package Mechanical Specifications Numonyx® Axcell™ M29EW
84 208031-05
Figure 36. BGA48 6 x 8 mm - 6 x 8 active ball array, package outline
1. Drawing is not to scale.
2. Drawing is bottom view.
Table 31. BGA48 6 x 8 mm - 6 x 8 active ball array, package mechanical data
Symbol millimeters
Typ Min Max
A– –1.00
A1–0.20–
A2 0.64 – –
b 0.35 0.30 0.40
D 6.00 5.90 6.10
D1 4.00 – –
e0.80 – –
E 8.00 7.90 8.10
E1 5.60 – –
FD 1.00 – –
FE 1.20 – –
SD 0.40 – –
SE 0.40 – –
ddd – – 0.10
Numonyx® Axcell™ M29EW Package Mechanical Specifications
208031-05 85
Figure 37. Fortified BGA64 11 x 13 mm - 8 x 8 active ball array, package outline
1. Drawing is not to scale.
2. Drawing is bottom view.
Table 32. Fortified BGA64 11 x 13 mm - 8 x 8 act ive ball array, package mechanic al
data
Symbol millimeters
Typ Min Max
A– –1.40
A1 0.49 0.40 –
A2 0.80 – –
b 0.60 0.55 0.65
D 11.00 10.90 11.10
D1 7.00 – –
ddd – – 0.10
e1.00 – –
E 13.00 12.90 13.10
E1 7.00 – –
FD 2.00 – –
FE 3.00 – –
SD 0.50 – –
SE 0.50 – –
E1E
D1
D
eb
SD
SE
A2
A1
A
BGA-Z23
ddd
FD
FE
BALL "A1"
Ordering Information Numonyx® Axcell™ M29EW
86 208031-05
12 Ordering Information
Note: This product is also available with the Extended Memory Block Numonyx pre-locked. For
further details and ordering information contact your nearest Numonyx sales office.
De vices are shipped from Numo nyx f actory with the memory content bits era sed to ‘1’. F or a
list of available options (package, High/Low protect, etc.) or for further information on any
aspect of the device, please contact your nearest Numonyx Sales Office.
Table 33. Ordering information scheme
Example: RC 28F 128 M29EW H *****
Package
JS = TSOP56: 14 x 20 mm, lead free, RoHS compliant, halogen free
PC = Fortified BGA64: 11 x 13 mm, lead free, RoHS compliant, halogen free
RC = Fortified BGA64: 11 x 13 mm, leaded
JR = TSOP48: 12 x 20 mm, lead free, RoHS compliant, halogen free
PZ = BGA48: 6 x 8 mm, lead fre e, RoHS compliant, halogen free
Prod uct Lin e
28F= NOR Parallel Interface
Device Density
128=128-Mbit
064=64-Mbit
032=32-Mbit
Device Type
M29EW = 3V core, page flash memory
Device function
H = uniform block, highest block protected by VPP/WP#
L = uniform block, lowest block protected by VPP/WP#
B = bottom boot, bottom two blocks protected by VPP/WP#
T = top boot, top two blocks protected by VPP/WP#
Device features
*= The last digit is randomly assigned to cover packing media and/or features or
other specific configuration.
Numonyx® Axcell™ M29EW Ordering Information
208031-05 87
Table 34. Valid Combinations of SBC M29EW Part Numbers
Note: For further information on ordering products or for product part numbers, go to:
http://www.numonyx.com/en-US/MemoryProducts/Pages/PartNumberLookup.aspx.
128-Mbit 64-Mbit 32-Mbit
JS28F128M29EWH* JS28F064M29EWH* JR28F032M29EWH*
JS28F128M29EWL* JS28F064M29EWL* JR28F032M29EWL*
PC28F128M29EWH* JS28F064M29EWB* JR28F032M29EWB*
PC28F128M29EWL* JS28F064M29EWT* JR28F032M29EWT*
RC28F128M29EWH* JR28F064M29EWH* PZ28F032M29EWH*
RC28F128M29EWL* JR28F064M29EWL* PZ28F032M29EWL*
- JR28F064M29EWB* PZ28F032M29EWB*
- JR28F064M29EWT* PZ28F032M29EWT*
- PC28F064M29EWH* -
- PC28F064M29EWL* -
- PC28F064M29EWB* -
- PC28F064M29EWT* -
- PZ28F064M29EWH* -
- PZ28F064M29EWL* -
- PZ28F064M29EWB* -
- PZ28F064M29EWT* -
128-Mbit Memory Address Table Numonyx® Axcell™ M29EW
88 208031-05
Appendix A 128-Mbit Memory Address Table
Table 35. Block Address Table(1)
Block Number Block Size
(Kbytes / Kwords) x8 Address
(HEX) x16 Address
(HEX)
0 128 / 64 0000000-001FFFF 0000000-000FFFF
1 128 / 64 0020000-003FFFF 0010000-001FFFF
2 128 / 64 0040000-005FFFF 0020000-002FFFF
3 128 / 64 0060000-007FFFF 0030000-003FFFF
4 128 / 64 0080000-009FFFF 0040000-004FFFF
5 128 / 64 00A0000-00BFFFF 0050000-005FFFF
6 128 / 64 00C0000-00DFFFF 0060000-006FFFF
7 128 / 64 00E0000-00FFFFF 0070000-007FFFF
8 128 / 64 0100000-011FFFF 0080000-008FFFF
9 128 / 64 0120000-013FFFF 0090000-009FFFF
10 128 / 64 0140000-015FFFF 00A0000-00AFFFF
11 128 / 64 0160000-017FFFF 00B0000-00BFFFF
12 128 / 64 0180000-019FFFF 00C0000-00CFFFF
13 128 / 64 01A0000-01BFFFF 00D0000-00DFFFF
14 128 / 64 01C0000-01DFFFF 00E0000-00EFFFF
15 128 / 64 01E0000-01FFFFF 00F0000-00FFFFF
16 128 / 64 0200000-021FFFF 0100000-010FFFF
17 128 / 64 0220000-023FFFF 0110000-011FFFF
18 128 / 64 0240000-025FFFF 0120000-012FFFF
19 128 / 64 0260000-027FFFF 0130000-013FFFF
20 128 / 64 0280000-029FFFF 0140000-014FFFF
21 128 / 64 02A0000-02BFFFF 0150000-015FFFF
22 128 / 64 02C0000-02DFFFF 0160000-016FFFF
23 128 / 64 02E0000-02FFFFF 0170000-017FFFF
24 128 / 64 0300000-031FFFF 0180000-018FFFF
25 128 / 64 0320000-033FFFF 0190000-019FFFF
26 128 / 64 0340000-035FFFF 01A0000-01AFFFF
27 128 / 64 0360000-037FFFF 01B0000-01BFFFF
28 128 / 64 0380000-039FFFF 01C0000-01CFFFF
29 128 / 64 03A0000-03BFFFF 01D0000-01DFFFF
30 128 / 64 03C0000-03DFFFF 01E0000-01EFFFF
Numonyx® Axcell™ M29EW 128-Mbit Memory Addres s Table
208031-05 89
31 128 / 64 03E0000-03FFFFF 01F0000-01FFFFF
32 128 / 64 0400000-041FFFF 0200000-020FFFF
33 128 / 64 0420000-043FFFF 0210000-021FFFF
34 128 / 64 0440000-045FFFF 0220000-022FFFF
35 128 / 64 0460000-047FFFF 0230000-023FFFF
36 128 / 64 0480000-049FFFF 0240000-024FFFF
37 128 / 64 04A0000-04BFFFF 0250000-025FFFF
38 128 / 64 04C0000-04DFFFF 0260000-026FFFF
39 128 / 64 04E0000-04FFFFF 0270000-027FFFF
40 128 / 64 0500000-051FFFF 0280000-028FFFF
41 128 / 64 0520000-053FFFF 0290000-029FFFF
42 128 / 64 0540000-055FFFF 02A0000-02AFFFF
43 128 / 64 0560000-057FFFF 02B0000-02BFFFF
44 128 / 64 0580000-059FFFF 02C0000-02CFFFF
45 128 / 64 05A0000-05BFFFF 02D0000-02DFFFF
46 128 / 64 05C0000-05DFFFF 02E0000-02EFFFF
47 128 / 64 05E0000-05FFFFF 02F0000-02FFFFF
48 128 / 64 0600000-061FFFF 0300000-030FFFF
49 128 / 64 0620000-063FFFF 0310000-031FFFF
50 128 / 64 0640000-065FFFF 0320000-032FFFF
51 128 / 64 0660000-067FFFF 0330000-033FFFF
52 128 / 64 0680000-069FFFF 0340000-034FFFF
53 128 / 64 06A0000-06BFFFF 0350000-035FFFF
54 128 / 64 06C0000-06DFFFF 0360000-036FFFF
55 128 / 64 06E0000-06FFFFF 0370000-037FFFF
56 128 / 64 0700000-071FFFF 0380000-038FFFF
57 128 / 64 0720000-073FFFF 0390000-039FFFF
58 128 / 64 0740000-075FFFF 03A0000-03AFFFF
59 128 / 64 0760000-077FFFF 03B0000-03BFFFF
60 128 / 64 0780000-079FFFF 03C0000-03CFFFF
61 128 / 64 07A0000-07BFFFF 03D0000-03DFFFF
62 128 / 64 07C0000-07DFFFF 03E0000-03EFFFF
63 128 / 64 07E0000-07FFFFF 03F0000-03FFFFF
64 128 / 64 0800000-081FFFF 0400000-040FFFF
Table 35. Block Address Table(1)
Block Number Block Size
(Kbytes / Kwords) x8 Address
(HEX) x16 Address
(HEX)
128-Mbit Memory Address Table Numonyx® Axcell™ M29EW
90 208031-05
65 128 / 64 0820000-083FFFF 0410000-041FFFF
66 128 / 64 0840000-085FFFF 0420000-042FFFF
67 128 / 64 0860000-087FFFF 0430000-043FFFF
68 128 / 64 0880000-089FFFF 0440000-044FFFF
69 128 / 64 08A0000-08BFFFF 0450000-045FFFF
70 128 / 64 08C0000-08DFFFF 0460000-046FFFF
71 128 / 64 08E0000-08FFFFF 0470000-047FFFF
72 128 / 64 0900000-091FFFF 0480000-048FFFF
73 128 / 64 0920000-093FFFF 0490000-049FFFF
74 128 / 64 0940000-095FFFF 04A0000-04AFFFF
75 128 / 64 0960000-097FFFF 04B0000-04BFFFF
76 128 / 64 0980000-099FFFF 04C0000-04CFFFF
77 128 / 64 09A0000-09BFFFF 04D0000-04DFFFF
78 128 / 64 09C0000-09DFFFF 04E0000-04EFFFF
79 128 / 64 09E0000-09FFFFF 04F0000-04FFFFF
80 128 / 64 0A00000-0A1FFFF 0500000-050FFFF
81 128 / 64 0A20000-0A3FFFF 0510000-051FFFF
82 128 / 64 0A40000-0A5FFFF 0520000-052FFFF
83 128 / 64 0A60000-0A7FFFF 0530000-053FFFF
84 128 / 64 0A80000-0A9FFFF 0540000-054FFFF
85 128 / 64 0AA0000-0ABFFFF 0550000-055FFFF
86 128 / 64 0AC0000-0ADFFFF 0560000-056FFFF
87 128 / 64 0AE0000-0AFFFFF 0570000-057FFFF
88 128 / 64 0B00000-0B1FFFF 0580000-058FFFF
89 128 / 64 0B20000-0B3FFFF 0590000-059FFFF
90 128 / 64 0B40000-0B5FFFF 05A0000-05AFFFF
91 128 / 64 0B60000-0B7FFFF 05B0000-05BFFFF
92 128 / 64 0B80000-0B9FFFF 05C0000-05CFFFF
93 128 / 64 0BA0000-0BBFFFF 05D0000-05DFFFF
94 128 / 64 0BC0000-0BDFFFF 05E0000-05EFFFF
95 128 / 64 0BE0000-0BFFFFF 05F0000-05FFFFF
96 128 / 64 0C00000-0C1FFFF 0600000-060FFFF
97 128 / 64 0C20000-0C3FFFF 0610000-061FFFF
98 128 / 64 0C40000-0C5FFFF 0620000-062FFFF
Table 35. Block Address Table(1)
Block Number Block Size
(Kbytes / Kwords) x8 Address
(HEX) x16 Address
(HEX)
Numonyx® Axcell™ M29EW 128-Mbit Memory Addres s Table
208031-05 91
99 128 / 64 0C60000-0C7FFFF 0630000-063FFFF
100 128 / 64 0C80000-0C9FFFF 0640000-064FFFF
101 128 / 64 0CA0000-0CBFFFF 0650000-065FFFF
102 128 / 64 0CC0000-0CDFFFF 0660000-066FFFF
103 128 / 64 0CE0000-0CFFFFF 0670000-067FFFF
104 128 / 64 0D00000-0D1FFFF 0680000-068FFFF
105 128 / 64 0D20000-0D3FFFF 0690000-069FFFF
106 128 / 64 0D40000-0D5FFFF 06A0000-06AFFFF
107 128 / 64 0D60000-0D7FFFF 06B0000-06BFFFF
108 128 / 64 0D80000-0D9FFFF 06C0000-06CFFFF
109 128 / 64 0DA0000-0DBFFFF 06D0000-06DFFFF
110 128 / 64 0DC0000-0DDFFFF 06E0000-06EFFFF
111 128 / 64 0DE0000-0DFFFFF 06F0000-06FFFFF
112 128 / 64 0E00000-0E1FFFF 0700000-070FFFF
113 128 / 64 0E20000-0E3FFFF 0710000-071FFFF
114 128 / 64 0E40000-0E5FFFF 0720000-072FFFF
115 128 / 64 0E60000-0E7FFFF 0730000-073FFFF
116 128 / 64 0E80000-0E9FFFF 0740000-074FFFF
117 128 / 64 0EA0000-0EBFFFF 0750000-075FFFF
118 128 / 64 0EC0000-0EDFFFF 0760000-076FFFF
119 128 / 64 0EE0000-0EFFFFF 0770000-077FFFF
120 128 / 64 0F00000-0F1FFFF 0780000-078FFFF
121 128 / 64 0F20000-0F3FFFF 0790000-079FFFF
122 128 / 64 0F40000-0F5FFFF 07A0000-07AFFFF
123 128 / 64 0F60000-0F7FFFF 07B0000-07BFFFF
124 128 / 64 0F80000-0F9FFFF 07C0000-07CFFFF
125 128 / 64 0FA0000-0FBFFFF 07D0000-07DFFFF
126 128 / 64 0FC0000-0FDFFFF 07E0000-07EFFFF
127 128 / 64 0FE0000-0FFFFFF 07F0000-07FFFFF
1. The 128M-bit device consists of 128 blocks, from block 0 to block 127.
Table 35. Block Address Table(1)
Block Number Block Size
(Kbytes / Kwords) x8 Address
(HEX) x16 Address
(HEX)
Common Flash Interface (CFI) Numonyx® Axcell™ M29EW
92 208031-05
Appendix B Common Flash Interface (CFI)
The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from
the Flash memory device. It allo ws a system so ftware to query the de vice to d etermine v a rious elect rical
and timing parameters, density information and functions supported by the memory. The system can
interface easily with the device, enabling the software to upgrade itself when necessary.
When the Read CFI Query command is issued, the memory enters Read CFI Query mode and read
operations output the CFI data. Table 36, Table 37, Table 38, Table 39 an d Table 40 and show the
addresses (A-1, A0-A7) used to retrieve the data.
Table 36. Query structure overview(1)
1. Query data are always presented on the lowest order data outputs.
Address Sub-section name Description
x16 x8
10h 20h CFI query identification string Command set ID and algorithm data offset
1Bh 36h System interface information Device timi ng & voltage information
27h 4Eh Device geometry definition Flash device layout
40h 80h Primary algorithm-specific extended query table Additional information specific to the primar y
algorithm (optional)
Table 37. CFI query identification string(1)
1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
Address Data Description Value
x16 x8
10h 20h 0051h ‘Q’
11h 22h 0052h Query Unique ASCII String ‘QRY’ ‘R’
12h 24h 0059h ‘Y’
13h 26h 0002h Pr imary algorithm command set and control interface ID code 16 bit
ID code defining a specific algorithm AMD
compatible
14h 28h 0000h
15h 2Ah 0040h Address for primary algorithm extended que ry table (see Table 40) P = 40h
16h 2Ch 0000h
17h 2Eh 0000h Alternate vendor command set and control interface ID code second
vendor - specified algorithm supported NA
18h 30h 0000h
19h 32h 0000h Address for alternate algor ithm extended query table NA
1Ah 34h 0000h
Numonyx® Axcell™ M29EW Common Flash Interface (CFI)
208031-05 93
Table 38. CFI query system interface information(1)
Address Data Description Value
x16 x8
1Bh 36h 0027h VCC logic supply minimum Program/Erase voltage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV 2.7 V
1Ch 38h 0036h VCC logic supply maximum Program/Erase voltage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV 3.6 V
1Dh 3Ah 00B5h
VPPH [programming] supply minimum Program/Erase
voltage
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
11.5 V
1Eh 3Ch 00C5h
VPPH [programming] supply m aximum Program/Er ase
voltage
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 10 mV
12.5 V
1Fh 3Eh 0004h Typical time-out for single byte/word program = 2n µs 16 µs
20h 40h 0009h Typical time-out for maximum size buff er program = 2n
µs 512 µs
21h 42h 0009h Typical time-out for individual block erase = 2n ms 0.5 s
22h 44h 000Fh
0010h
0011h Typical time-out for full Chip Erase = 2n ms 32M 33 s
64M 66 s
128M 131 s
23h 46h 0004h Maximum time-out for byte/word program = 2n times
typical time-out 256 µs
24h 48h 0002h Maximum time-out for buffer program = 2n times
typical time-out 2048 µs
25h 4Ah 0003h Maximum time-out per individual bloc k er ase = 2n
times typical time-out 4s
26h 4Ch 0002h Maximum time-out for Chip Erase = 2n times typical
time-out
32M 131 s
64M 262 s
128M 524 s
1. The values given in the above table are valid for all packages.
Table 39. Device geometry definition
Address Data Description Value
x16 x8
27h 4Eh 0016h / 0017h / 0018h Device size = 2n in number of bytes 4 Mbytes
8 Mbyte s
16 Mbytes
28h
29h 50h
52h 0002h
0000h Flash device interface code description x8, x16
Async.
Common Flash Interface (CFI) Numonyx® Axcell™ M29EW
94 208031-05
2Ah
2Bh 54h
56h 0008h(1)
0000h Maximum number of b ytes in multiple-byte
program or page= 2n256
2Ch 58h See below tab le
Number of Erase block regions within device. It
specifies the number of regions containing
contiguous Erase blocks of the same size.
01h = uniform device
02h = boot device
-
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
See below table
Erase block region 1 information
bits 0-15 = y, y+1 = Number of Erase blocks of
identical size.
bits 16-31 = z, Block size in region1 is zx256
bytes.
-
31h
32h
33h
34h
62h
64h
66h
68h
See below table
Erase block region 2 information
bits 0-15 = y, y+1 = Number of Erase blocks of
identical size.
bits 16-31 = z, Block size in region 2 is zx256
bytes.
-
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
Erase block region 3 information 0
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase block region 4 information 0
1. The value at 2Ah in CFI region is purposely set to 08h (256 bytes) due to compatibility reasons. The maximum 256-word
program buffer can be used to optimize system program performance.
Table 39. Device geometry definition
Address Data Description Value
x16 x8
Address 32-Mbit 64-Mbit 128-Mbit
Top Bottom Uniform Top Bottom Uniform Uniform
2Ch 02h 02h 01h 02h 02h 01h 01h
2Dh 07h 07h 3Fh 07h 07h 7Fh 7Fh
2Eh 00h 00h 00h 00h 00h 00h 00h
2Fh 20h 20h 00h 20h 20h 00h 00h
30h 00h 00h 01h 00h 00h 01h 02h
31h 3Eh 3Eh 00h 7Eh 7Eh 00h 00h
32h 00h 00h 00h 00h 00h 00h 00h
33h 00h 00h 00h 00h 00h 00h 00h
34h 01h 01h 00h 01h 01h 00h 00h
Numonyx® Axcell™ M29EW Common Flash Interface (CFI)
208031-05 95
Table 40. Primary algorithm-specific extended query table (1)
Address Data Description Value
x16 x8
40h 80h 0050h
Primary algor ithm extended query table unique ASCII string “PRI”
‘P’
41h 82h 0052h ‘R’
42h 84h 0049h ‘I’
43h 86h 003 1h Major version number, ASCII ‘1’
44h 88h 003 3h Minor version number, ASCII ‘3’
45h 8Ah 0018h Address sensitive unlock (bits 1 to 0)
00 = required, 01= not required
Silicon revision number (bits 7 to 2) Required
46h 8Ch 0002h Erase Suspend
00 = not supported, 01 = Read only, 02 = read and write 2
47h 8Eh 0001h Block protection
00 = not supported, x = number of blocks per group 1
48h 90h 0000h Temporary block unprotect
00 = not supported, 01 = supported Not
supported
49h 92h 0008h Block protect / unprotect
08 = M29EWH/M29EWL 8
4Ah 94h 0000h Simultaneous operations: not supported NA
4Bh 96h 000 0h Burst mode, 00 = not supported, 01 = supported Not
supported
4Ch 98h 0002h Page mode, 00 = not supported, 01 = 8-word page
02 = 8-word page, 03 = 16-word page 8-word
page
4Dh 9Ah 00B5h VPPH supply minimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV 11.5 V
4Eh 9Ch 00C5h VPPH supply maximum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV 12.5 V
4Fh 9Eh 00xxh
To p/bottom boot block flag
xx = 02h: Bottom boot device, HW protection for bottom two blocks
xx = 03h: Top boot device , HW protection f or top tw o blocks
xx = 04h: Uniform device, HW protection for lowest block
xx = 05h: Uniform device, HW protection for highest bloc k
device
type
(bottom
boot, top
boot,
uniform)
50h A0h 0001h Program suspend, 00 = not supported, 01 = supported Supported
1. The values given in the above table are valid for all packages.
Extended Memory Block Numonyx® Axcell™ M29EW
96 208031-05
Appendix C Extended Memory Block
The M29EW has an e xtr a b lo c k, the Extende d Memory Block, that can be accessed u sing a
dedicated command. This Extended Memory Block is 128 wor ds in x16 mode and 256 bytes
in x8 mode. It is used as a secur ity block (to provide a perm a ne n t secu rity identification
number) or to store additional information.
The de vice can be shipped either with the Extended Memory Block pre-loc k ed by Numon yx,
or unlocked.
If the Extended Memory Block is not pre-locked by Numonyx, it can be customer-lockable.
Its status is indicated by bit DQ7 of Extended Memory Block Verify Indicator in Auto Select
mode. This bit is permanently set to either ‘1’ or ‘0’ at the Numonyx factory and cannot be
changed. When set to ‘1’, it indicates that the device is pre-locked by Numonyx and the
Extended Memory Block is protected. When set to ‘0’, it indicates that the device is
customer-lockable. Bit DQ7 being permanently locked to either ‘1’ or ‘0’ is another security
feature wh ich en su re s th at a cu sto m er -lo ckable device cann ot be used inste ad of a
Numonyx pre-locked one.
Bit DQ7 is the most significant bit in the Extended Memory Block Verify Indicator. It can be
read in Auto Select mode using eith er the Programmer (see Table 7 and Table 8) or the In-
system method (see Table 9 and Table 10).
The Extended Memory Block can onl y be accessed when the de vice is in Extended Memory
Block mode. For details of how the Extended Memory Block mode is entered and exited,
refer to the Section 6.3.1: Ent er Extend ed Memory Block command and Section 6.3.2: Exit
Extended Memory Block command, and to Table 13 and Table 9.
C.1 Numonyx pre-locked Extended Memory Block
If devices of which the Extended Memory Block is pre-locked upon customer request, the
128bits security identification number is written to the Extended Memory Block address
space (see Table 41: Extended Memory Block address and data) in Numonyx factory. The
contents in the Exte nd e d Me m ory Block cannot be changed any more.
Numonyx® Axcell™ M29EW Extended Memory Block
208031-05 97
C.2 Customer-lockable Extended Memory Block
A de vice where the Extended Memory Block is customer-loc kab le is deliv ered with the DQ7
bit set to ‘0’ and the Extended Memory Block unprotected. It is up to the customer to
program and protect the Extended Memory Block but care must be taken because the
protection of th e Exte nde d M em o ry Block is not reversible.
If the device has not been shipped with the Extended Memory Block pre-protected, the block
can be protected by setting the Extended Memory Block Protection bit, DQ0, to ‘0’.
How ever, this bit can only be programmed once; and once it is protected the Extended
Memory Block cannot be unprotected.
Once the Extended Memory Block is programmed, the Exit Extended Memory Block
command must be issue d to e xit the Extended Memory Block mode and return the de vice to
Read mode.
Table 41. Extended Memory Block address and data
Address(1) Data
x8 x16 Numonyx pre-locked Customer-lockable
000000h-00000Fh 000000h-000007h Secure identifica tion
number Determined b y
customers
(default)
Secure identification
number
000010h-0000FFh 000008h-00007Fh Protected and
unavailable Determined by
customers
1.
Revision History Numonyx® Axcell™ M29EW
98 208031-05
Appendix D Revision History
Table 42. Document revision history
Date Version Changes
Jun 2009 01 Initial release
Apr 2010 02
Added 48L TSOP and 48B BGA connection information.
Added 64M and 32M memory map.
Added 48L TSOP and 48B BGA package outline information.
Updated program performance and suspend latency.
Order information updated with de vice feature digit.
Updated part number information in valid combination table.
CFI updated to cover 64-Mbit and 32-Mbit device related information.
Read electronic signature information updated to cover 64-Mbit and 32-Mbit
device.
Block protection infor m ation updated to cover 64-Mbit and 32-Mbit device.
Updated the Random Read AC waveform s about BYTE# pin in Section 9:
DC and AC Parameters.
Added a note to state fast program (double program, quadruple program
and octuple program) can only work with VPPL in Section 6.2: Fast
Program commands on page 37.
Updated typical time-out and maximum time-out for buffer program at CFI
table.
Updated the description of VPP/WP# pin in Section 2.8: VPP/Write Protect
(VPP/WP#) on page 16.
Added JESD47E compliant.
Numonyx® Axcell™ M29EW Revision History
208031-05 99
May 2010 03 Updated the Random Read AC wavefor m s about BYTE# pin in Section 9:
DC and AC Parameters.
Put a link for product part numbers in Section 12: Order ing Information.
Jan 2011 04
Aligned with device about the commands for double byte/quadruple
byte/oct uble byte program at Table 11: Fast Program commands, 8-bit
mode on page 46 and double word/quadruple word program at Table 12:
Fast Program commands, 16-bit mode on page 47.
Corrected the CFI value for add ress 2Fh (x16) for 64-Mbit/32-Mbit
Top/Bottom devices.
Corrected the CFI value for add ress 22h (x16) for 32-Mbit devices.
Removed the invalid automatic standby mode from front page and
Section 3: Bus Operations on page 19.
Removed the statement about unlock bypass fast program at note of
Section 6.2: Fast Program commands on page 37 since it’s not valid.
Added JEDEC standard lead width for TSOP56 package at Table 29:
TSOP56 – 56 lead thin small-outline package, 14 x 20 mm, package
mechanical data on page 82
Apr 2011 05
For read ID and read protec tion status, align with device about higher
address pins input status at Table 5, Table 6, Table 7 and Table 8.
Corrected the glitch filter from 5ns to 3ns
Removed the inv alid statement about applying VID to A9 to enter A u to
Select mode at Section 7.1.3: Extended Memory Block Protection bit (DQ0)
Add Blank Check related information
Date Version Changes
Numonyx® Axcell™ M29EW
100
Please Read Carefully:
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX® PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN NUMONYX'S TER M S AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY
WHATSOEVER, AND NUMONYX DIS CLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF
NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR I NFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility
applications.
Numonyx may make changes to specificati ons and product descri ptions at any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any s uch patents, trademarks, copyrights, or other intellectual property righ ts.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves
these for future definition and shall have no resp onsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product orde r.
Copies of doc uments which have an orde r number and are referenced in this document, or other Numonyx literat ure may be obtained by
visiting Numonyx's website at http://www.numonyx.com.
Numonyx Axc ell is a trademark or re gistered trademark of Numonyx or its subsidiaries in the United States and other countri es.
*Other names and brands may be claimed as the property of others.
Copyright © 2009, Numonyx, B.V., All Rights Reserved.
