EL2126 - Intersil Corporation - Datasheet.Directory

®EL2126

Ultra-Low Noise, Low Power, Wideband

Amplifier

The EL2126 is an ultra-low noise, wideband amplifier that

runs on half the supply current of competitive parts. It is

intended for use in systems such as ultrasound imaging

where a very small signal needs to be amplified by a large

amount without adding significant noise. Its low power

dissipation enables it to be packaged in the tiny SOT-23

package, which further helps systems where many input

channels create both space and power dissipation problems.

The EL2126 is stable for gains of 10 and greater and uses

traditional voltage feedback. This allows the use of reactive

elements in the feedback loop, a common requirement for

many filter topologies. It operates from ±2.5V to ±15V

supplies and is available in the 5 Ld SOT-23 and 8 Ld SO

packages.

The EL2126 is fabricated in Elantec’s proprietary

complementary bipolar process, and is specified for

operation over the full -40°C to +85°C temper ature range.

Pinouts EL2126

(5 LD SOT-23)

TOP VIEW

EL2126

(8 LD SO)

TOP VIEW

Features

• Voltage noise of only 1.3nV/÷Hz

• Current noise of only 1.2pA/÷Hz

• 200µV offset voltage

• 100MHz -3dB BW for AV = 10

• Very low supply current - 4.7mA

• SOT-23 package

• ±2.5V to ±15V operation

• Pb-free plus anneal available (RoHS compliant)

Applications

• Ultrasound input amplifiers

• Wideband instrumentation

• Communication equipment

• AGC & PLL active filters

• Wideband sensors

VS+

IN-IN+

VS-

OUT

IN-

IN+

VS-

VS+

OUT

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

FN7046.3Data Sheet April 16, 2007

2FN7046.3

April 16, 2007

Ordering Information

Part

Number PART

MARKING TEMP RANGE

(°c) Tape & Reel Package pkg. dWG. #

EL2126CW-T7 G -40 to +85 7” (3K pcs) 5 Ld SOT-23 MDP0038

EL2126CW-T7A G -40 to +85 7” (250 pcs) 5 Ld SOT-23 MDP0038

EL2126CS 2126CS -40 to +85 - 8 Ld SOIC MDP0027

EL2126CS-T7 2126CS -40 to +85 7” 8 Ld SOIC MDP0027

EL2126CS-T13 2126CS -40 to +85 13” 8 Ld SOIC MDP0027

EL2126CSZ

( Note) 2126CSZ -40 to +85 - 8 Ld SOIC

(Pb-free) MDP0027

EL2126CSZ-T7

( Note) 2126CSZ -40 to +85 7” 8 Ld SOIC

(Pb-free) MDP0027

EL2126CSZ-T13 ( Note) 2126CSZ -40 to +85 13” 8 Ld SOIC

(Pb-free) MDP0027

EL2126CWZ-T7

(Note) BAAH -40 to +85 7” 5 Ld SOT-23 P5.064

EL2126CWZ-T7A

(Note) BAAH -40 to +85 7” 5 Ld SOT-23 P5.064

NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate terminat ion

finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at

Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

EL2126

3FN7046.3

April 16, 2007

Absolute Maximum Ratings Thermal Information

VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33V

Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA

Any Input . . . . . . . . . . . . . . . . . . . . . . . . . . VS+ - 0.3V to VS- + 0.3V

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-60°C to +150°C

Maximum Die Junction Temperature. . . . . . . . . . . . . . . . . . .+150°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests

are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA

Electrical Specifications VS+ = +5V, VS- = -5V, TA = +25°C, RF = 180Ω, RG = 20Ω, RL = 500Ω unless otherwise specified.

Parameter Description Conditions Min Typ Max Unit

DC PERFORMANCE

VOS Input Offset Voltage (SO8) 0.2 2 mV

Input Offset Voltage (SOT23-5) 3mV

TCVOS Offset Voltage Temperature

Coefficient 17 µV/°C

IBInput Bias Current -10 -7 µA

IOS Input Bias Current Offset 0.06 0.6 µA

TCIB Input Bias Current Temperature

Coefficient 0.013 µA/°C

CIN Input Capacitance 2.2 pF

AVOL Open Loop Gain VO = -2.5V to +2.5V 80 87 dB

PSRR Power Supply Rejection Ratio

(Note 1) 80 100 dB

CMRR Common Mode Rejection Ratio at CMIR 75 106 dB

CMIR Common Mode Input Range -4.6 3.8 V

VOUTH Positive Output Voltage Swing No load, RF = 1kΩ3.8 3.8 V

VOUTL Negative Output Voltage Swing No load, RF = 1kΩ-4 -3.9 V

VOUTH2 Positive Output Voltage Swing RL = 100Ω3.2 3.45 V

VOUTL2 Negative Output Voltage Swing RL = 100Ω-3.5 -3.2 V

IOUT Output Short Circuit Current

(Note 2) 80 100 mA

ISY Supply Current 4.7 5.5 mA

AC PERFORMANCE - RG = 20Ω, CL = 3pF

BW -3dB Bandwidth, RL = 500Ω100 MHz

BW ±0.1dB ±0.1dB Bandwidth, RL = 500Ω17 MHz

BW ±1dB ±1dB Bandwidth, RL = 500Ω80 MHz

Peaking Peaking, RL = 500Ω0.6 dB

SR Slew Rate VOUT = 2VP-P, measured at 20% to 80% 80 110 V/µs

OS Overshoot, 4VP-P Output Square

Wave Positive 2.8 %

Negative -7 %

tSSettling Time to 0.1% of ±1V Pulse 51 ns

EL2126

4FN7046.3

April 16, 2007

VNVoltage Noise Spectral Density 1.3 nV/√Hz

INCurrent Noise Spectral Density 1.2 pA/√Hz

HD2 2nd Harmonic Distortion (Note 3) -70 dBc

HD3 3rd Harmonic Distortion (Note 3) -70 dBc

NOTES:

1. Measured by moving the supplies from ±4V to ±6V

2. Pulse test only and using a 10Ω load

3. Frequency = 1MHz, VOUT = 2VP-P, into 500Ω and 5pF load

Electrical Specifications VS+ = +5V, VS- = -5V, T A = +25°C, RF = 180Ω, RG = 20Ω, RL = 500Ω unless otherwise specified. (Continued)

Parameter Description Conditions Min Typ Max Unit

Electrical Specifications VS+ = +15V, VS- = -15V, TA = 25°C, RF = 180Ω, RG = 20Ω, RL = 500Ω unless otherwise specified.

Parameter Description Conditions Min Typ Max Unit

DC PERFORMANCE

VOS Input Offset Voltage (SO8) 0.5 3 mV

Input Offset Voltage (SOT23-5) 3mV

TCVOS Offset Voltage Temperature

Coefficient 4.5 µV/°C

IBInput Bias Current -10 -7 µA

IOS Input Bias Current Offset 0.12 0.7 µA

TCIB Input Bias Current Temperature

Coefficient 0.016 µA/°C

CIN Input Capacitance 2.2 pF

AVOL Open Loop Gain 80 90 dB

PSRR Power Supply Rejection Ratio

(Note 4) 65 80 dB

CMRR Common Mode Rejection Ratio at CMIR 70 85 dB

CMIR Common Mode Input Range -14.6 13.8 V

VOUTH Positive Output Voltage Swing No load, RF = 1kΩ13.6 13.7 V

VOUTL Negative Output Voltage Swing No load, RF = 1kΩ-13.8 -13.7 V

VOUTH2 Positive Output Voltage Swing RL = 100Ω, RF = 1kΩ10.2 11.2 V

VOUTL2 Negative Output Voltage Swing RL = 100Ω, RF = 1kΩ-10.3 -9.5 V

IOUT Output Short Circuit Current

(Note 5) 140 220 mA

ISY Supply Current 56mA

AC PERFORMANCE - RG = 20Ω, CL = 3pF

BW -3dB Bandwidth, RL = 500Ω135 MHz

BW ±0.1dB ±0.1dB Bandwidth, RL = 500Ω26 MHz

BW ±1dB ±1dB Bandwidth, RL = 500Ω60 MHz

Peaking Peaking, RL = 500Ω2.1 dB

SR Slew Rate (±2.5V Square Wave,

Measured 25%-75%) 130 150 V/µS

OS Overshoot, 4VP-P Output Square

Wave Positive 1.6 %

Negative -4.4 %

TSSettling Time to 0.1% of ±1V Pulse 48 ns

EL2126

5FN7046.3

April 16, 2007

NOTES:

4. Measured by moving the supplies from ±13.5V to ±16.5V

5. Pulse test only and using a 10Ω load

6. Frequency = 1MHz, VOUT = 2VP-P, into 500Ω and 5pF load

VNVoltage Noise Spectral Density 1.4 nV/√Hz

INCurrent Noise Spectral Density 1.1 pA/√Hz

HD2 2nd Harmonic Distortion (Note 6) -72 dBc

HD3 3rd Harmonic Distortion (Note 6) -73 dBc

Electrical Specifications VS+ = +15V, VS- = -15V, TA = 25°C, RF = 180Ω, RG = 20Ω, RL = 500Ω unless otherwise specified. (Continued)

Parameter Description Conditions Min Typ Max Unit

EL2126

6FN7046.3

April 16, 2007

Typical Performance Curves

Non-Inverting Frequency Response for Va rious RF

-2

-6

-101M 10M 100M

Frequency (Hz)

Normalized Gain (dB)

RF=1kΩ

RF=500Ω

RF=180Ω

RF=100Ω

VS=±5V

AV=10

CL=5pF

RL=500Ω

Non-Inverting Frequency Response for Various RF

-2

-6

-101M 10M 100M

Frequency (Hz)

Normalized Gain (dB)

RF=1kΩ

RF=500Ω

RF=180Ω

RF=100Ω

Inverting Frequency Response for Va rious RF

-4

-8

-121M 10M 100M

Frequency (Hz)

Normalized Gain (dB)

VS=±15V

AV=-10

CL=5pF

RL=500Ω

Inverting Frequency Response for Various RF

-4

-8

-121M 10M 100M

Frequency (Hz)

Normalized Gain (dB)

VS=±5V

AV=-10

CL=5pF

RL=500Ω

Non-Inverting Frequency Response for Various Gain

-2

-6

-101M 10M 100M

Frequency (Hz)

Normali zed Gain (d B)

AV=10

VS=±5V

RG=20Ω

RL=500Ω

CL=5pF

Non-Inverting Frequency Response for Various Gain

-2

-6

-101M 10M 100M

Frequency (Hz)

Normali zed Gain (d B)

RF=1kΩ

RF=350Ω

RF=100Ω

RF=200Ω

RF=500ΩRF=1kΩ

RF=500Ω

RF=200Ω

RF=100Ω

RF=350Ω

AV=20

AV=50

VS=±15V

RG=20Ω

RL=500Ω

CL=5pF AV=10

AV=20

AV=50

VS=±15V

AV=10

CL=5pF

RL=500Ω

EL2126

7FN7046.3

April 16, 2007

Typical Performance Curves (Continued)

Inverting Frequency Response for Various Gain

-4

-8

-121M 10M 100M

Frequency (Hz)

Normalized Gain (dB)

Inverting Frequency Response for Va rious RF

-4

-8

-121M 10M 100M

Frequency (Hz)

Normalized Gain (dB)

Non-Inverting Frequency Response for Various

Output Signal Levels

-2

-6

-101M 10M 100M

Frequency (Hz)

Normali zed Gain (d B)

Non-Inverting Frequency Response for Various

Output Signal Levels

-4

-8

-121M 10M 100M

Frequency (Hz)

Normali zed Gain (d B)

Inverting Frequency Response for Various Output

Signal Levels

-4

-8

-121M 10M 100M

Frequency (Hz)

Normali zed Gain (d B)

Inverting Frequency Response for Va rious Output

Signal Levels

-4

-8

-121M 10M 100M

Frequency (Hz)

Normali zed Gain (d B)

VS=±5V

CL=5pF

RG=35Ω

AV=-10

AV=-20

AV=-50

VS=±15V

CL=5pF

RG=20Ω

AV=-10

AV=-20

AV=-50

VS=±5V

CL=5pF

RL=500Ω

RF=180Ω

AV=10

VO=2.5VPP

VO=5VPP

VO=1VPP

VO=30mVPP

VO=500mVPP

VS=±15V

CL=5pF

RL=500Ω

RF=180Ω

AV=10

VO=5VPP

VO=1VPP

VO=2.5VPP

VO=30mVPP

VO=500mVPP

VO=10VPP

VS=±5V

CL=5pF

RL=500Ω

RF=350Ω

AV=10

VO=3.4VPP

VO=1VPP

VO=2.5VPP

VO=30mVPP

VO=500mVPP VS=±15V

CL=5pF

RL=500Ω

RF=200Ω

AV=10

VO=3.4VPP

VO=1VPP

VO=2.5VP

VO=30mVPP

VO=500mVPP

VO=2.5VPP

EL2126

8FN7046.3

April 16, 2007

Typical Performance Curves (Continued)

Non-Inverting Frequency Response for Various CL

-2

-6

-10

1M 10M 100M

Frequency (Hz)

Normalized Gain (dB)

Non-Inverting Frequency Response for Various CL

-2

-6

-101M 10M 100M

Frequency (Hz)

Normalized Gain (dB)

Inverting Frequency Response for Various CL

-4

-8

-121M 10M 100M

Frequency (Hz)

Normalized Gain (dB)

Inverting Frequency Response for Various CL

-4

-8

-121M 10M 100M

Frequency (Hz)

Normalized Gain (dB)

Open Loop Gain/Phase

100

10k 10M 1G

Frequency (Hz)

Open Loop Gain (dB)

Supply Current vs Supply Voltage

0.6/div

1.5/div

Supply Voltage (V)

Supply Current (mA)

CL=28pF

CL=16pFCL=11pF

CL=5pF

CL=1pF

VS=±15V

RF=180Ω

AV=10

RL=500Ω

CL=28pF

CL=16pF

CL=11pF

CL=5pF

CL=1.2pF

VS=±5V

RF=350Ω

RL=500Ω

AV=-10

CL=28pF

CL=16pF

CL=11pF

CL=5pF

CL=1.2pF

CL=28pF

CL=16pF

CL=11p

CL=5pF

CL=1.2pF

VS=±15V

RF=200Ω

RL=500Ω

AV=-10

100k 100M1M

250

150

-50

-150

-250

Open Loop Phase (°)

VS=±5V

RF=150Ω

AV=10

RL=500Ω

Gain

Phase

VS=±5V

CL=11pF

EL2126

9FN7046.3

April 16, 2007

Typical Performance Curves (Continued)

Peaking vs Vs

3.0

2.5

2.0

1.0

0.5

00246810 1416

±Supply Voltage (V)

Peaking (dB)

1.5

Bandwidth vs Vs

160

140

100

00246810 1416

±VS (V)

-3dB Bandwidth

120

1MHz Harmonic Distortion vs Output Swing

-40

-50

-60

-80

-90

-100012345 78

VOUT (VP-P)

Harmonic Distortion (dBc)

-70

1MHz Harmonic Distortion vs Output Swing

-30

-40

-60

-80

-90

-1000 5 10 15 20 25

VOUT (VP-P)

Harmonic Distortion (dBc)

-70

-50

VS=±5V

RG=20Ω

RL=500Ω

CL=5pF

AV=10

AV=-10

2nd HD

3rd HD

2nd HD

VS=±5V

RG=20Ω

RL=500Ω

CL=5pF

VS=±5V

VO=2VP-P

RF=180Ω

AV=10

RL=500Ω

AV=-10

AV=10

AV=-20

AV=50

AV=-50

VS=±5V

VO=2VP-P

RF=180Ω

AV=10

RL=500Ω

3rd HD

Large Signal Step Response

0.5V/div

10ns/div

Small Signal Step Response

20mV/div

10ns/div

VS=±5V

VO=100mV

RF=180Ω

RG=20Ω

VS=±5V

VO=2VPP

RF=180Ω

RG=20Ω

EL2126

10 FN7046.3

April 16, 2007

Typical Performance Curves (Continued)

Group Delay vs Frequency

-4

1M 10M 100M 400M

Frequency (Hz)

Group Delay (ns)

VS=±5V

RL=500Ω

AV=10

AV=-10

Noise vs Frequency

110 100 10k 100k

Frequency (Hz)

IN (pA/√Hz), VN (nV/√Hz)

CMRR vs Frequency

-10

-50

-90

-11010 1M 10M 100M

Frequency (Hz)

CMRR (dB)

-70

-30

1k 100k100 10k

Settling Time vs Accuracy

0.1 1.0 10.0

Accuracy (%)

Settling Time (ns)

=±5V, V

=5V

P-P

=±15V, V

=5V

P-P

=±15V, V

=2V

P-P

=±5V, V

=2V

P-P

Total Harmonic Distortion vs Frequency

-20

-50

-80

-901k 10k 100M

Frequency (Hz)

THD (dBc)

VS=±5V

VO=2VP-P

100k 1M 10M

-30

-40

-70

-60

PSRR vs Frequency

110

10k 100k 1M 10M 200M

Frequency (Hz)

PSRR (dB)

VS=±5V

PSRR+

PSRR-

IN, VS=±5V

VN, VS=±15V

IN, VS=±15V

VN, VS=±5V

EL2126

11 FN7046.3

April 16, 2007

Typical Performance Curves (Continued)

Closed Loop Output Impedance vs Frequency

100

0.1

0.01

10k 1M 100M

Frequency (Hz)

Closed Loop Output Impedance (Ω)

Bandwidth and Peaking vs Temperature

120

100

0-40 40 160

Temperature

Bandwidth (MHz)

100k 10M

VS=±5V VS=±5V

800120

3.5

2.5

1.5

0.5

-0.5

Peaking (dB)

Slew Rate vs Swing

220

180

140

100

60-1

VOUT Swing (VPP)

Slew Rate (V/µs)

371115

5VSR+

5VSR-

15VSR+

15VSR-

15913

200

160

120

Bandwidth

Peaking

-2

-1

4.8

5.2

5.1

4.9

Supply Current vs Temperature

-50 0 100 15050

Die Temperature (°C)

IS (mA)

VS=±5V

VS=±15V

Offset Voltage vs Temperatur e

-50 0 100 15050

Die Temperature (°C)

VS=±5V

VS=±15V

VOS (mV)

CMRR vs Temperature

-50 0 100 15050

Die Temperature (°C)

CMRR (dB)

120

110

100

VS=±5V

EL2126

12 FN7046.3

April 16, 2007

Typical Performance Curves (Continued)

110

102

106

PSRR vs Temperature

-50 0 100 15050

Die Temperature (°C)

PSRR (dB)

VS=±5V

VS=±15V

Positive Output Swing vs Temperature

-50 0 100 15050

Die Temperature (°C)

VOUTH (V)

VS=±5V

Positive Output Swing vs Temperature

-50 0 100 15050

Die Temperature (°C)

VOUTH (V)

VS=±15V

4.05

3.95

3.9

3.85

3.8

13.85

13.8

13.75

13.7

13.65

13.6

-3.9

-3.95

-4.05

-4.25

-4.15

-13.76

-13.78

-13.8

-13.82

Negative Output Swing vs Temperature

-50 0 100 15050

Die Temperature (°C)

VOUTL (V)

VS=±5V

Negative Output Swing vs Temperature

-50 0 100 15050

Die Temperature (°C)

VS=±15V

VOUTL (V)

-4

-4.1

-4.2

Slew Rate vs Temperature

-50 0 100 15050

Die Temperature (°C)

Slew Rate (V/µs)

102

100

VS=±5V

EL2126

13 FN7046.3

April 16, 2007

Typical Performance Curves (Continued)

155

150

140

135

3.52

3.5

3.46

3.44

Slew Rate vs Te mperature

-50 0 100 15050

Die Temperature (°C)

SR (V/µs)

VO=2VPP

VS=±15V

Positive Loaded Output Swing vs Temperature

-50 0 100 15050

Die Temperature (°C)

VOUTH2 (V)

VS=±5V

11.8

11.6

11.2

10.8

10.6

Positive Loaded Output Swing vs Temperature

-50 0 100 15050

Die Temperature (°C)

SR (V/µs)

VS=±15V

145 3.48

11.4

-3.35

-3.4

-3.45

-3.6

-3.5

3.55

-9.4

-9.8

-10.2

-10.6

Negative Loaded Output Swing vs Temperature

-50 0 100 15050

Die Temperature (°C)

VOUTL2 (V)

VS=±5V

Negative Loaded Output Swing vs Temperature

-50 0 100 15050

Die Temperature (°C)

VS=±15V

VOUTL2 (V)

-9.6

-10

-10.4

1.2

0.6

Package Power Dissipation vs Ambient Temperature

JEDEC JESD51-3 Low Effective Thermal Conductivity

Test Board

Ambient Temperature (°C)

Power Dissipation (W )

25 125 15075

0.4

0.8

0.2

10050 85

488mW

781mW

=+160°C/W

SO8

=+256°C/W

SOT23-5

1.8

0.8

1.6

0.4

1.2

0.2

0.6

1.4

Package Power Dissipation vs Ambient Temperature

JEDEC JESD51-7 High Effective Thermal Conductivity

Test Board

Ambient Temperature (°C)

Power Dissipation (W)

25 125 15075 10050 85

543mW

=+110°C/W

SO8

1.136W

θJA=+230°C/W

SOT23-5

EL2126

14 FN7046.3

April 16, 2007

Pin Descriptions

EL2126CW

(5 ld SOT-23) EL2126CS

(8 ld SO) Pin Name Pin Function Equivalent Circuit

1 6 VOUT Output

Circuit 1

2 4 VS- Supply

3 3 VINA+ Input

Circuit 2

4 2 VINA- Input Reference Circuit 2

5 7 VS+ Supply

VOUT

VS+

VIN-VIN+

VS+

VS-

EL2126

15 FN7046.3

April 16, 2007

Applications Information

Product Descr iption

The EL2126 is an ultra-low noise, wideband monolithic

operational amplifier built on Elantec's proprietary high

speed complementary bipolar process. It features 1.3nV/√Hz

input voltage noise, 200µV typical offset voltage, and 73dB

THD. It is intended for use in systems such as ultrasound

imaging where very small signals are needed to be

amplified. The EL2126 also has excellent DC specifications:

200µV VOS, 22µA IB, 0.4µA IOS, and 106dB CMRR. These

specifications allow the EL2126 to be used in DC-sensitive

applications such as difference amplifiers.

Gain-Bandwidth Product

The EL2126 has a gain-bandwidth product of 650MHz at

±5V. For gains less th an 20, higher-order poles in the

amplifier's transfer function contribute to even higher closed-

loop bandwidths. For example, the EL2126 has a -3dB

bandwidth of 100MHz at a gain of 10 and decreases to

33MHz at gain of 20. It is import ant to note that the extra

bandwidth at lower gain does not come at the expenses of

stability. Even though the EL2126 is designed for gain ≥ 10.

With external compensation, the device can also operate at

lower gain setti n g s . Th e R C ne t wo rk sh ow n in Fig u re 1

reduces the feedback gain at high frequency and thus

maintains the amplifier stability. R values must be less than

RF divided by 9 and 1 divided by 2πRC must be less than

200MHz.

Choice of Feedback Resistor, RF

The feedback resistor forms a pole with the input

capacita nce. As this pole becomes larger, phase margin is

reduced. This increases ringin g in the time domain and

peaking in the frequency domain. Therefore, RF has some

maximum value which should not be exceeded for optimum

performance. If a large value of RF must be used, a small

capacitor in the few pF range in parallel with RF can help to

reduce this ringing and peaking at th e ex pense of reducing

the bandwidth. Frequency response curves for various RF

values are shown in the typical performance curves section

of this data sheet.

Noise Calculations

The primary application for the EL2126 is to amplify very

small signals. To maintain the proper signal-to-noise ratio, it

is essential to minimize noise contribution from the amplifier .

Figure 2 below shows all the noise source s for all the

components around the amplifier .

VN is the amplifier input voltage noise

IN+ is the amplifier positive input current noise

IN- is the amplifier negative input current noise

VRX is the thermal noise associated with each resistor:

where:

k is Boltzmann's constant = 1.380658 x 10-23

T is temperature in degrees Kelvin (273+ °C)

The total noise due to the amplifier seen at the output of the

amplifier can be calculated by using the Equation 2.

As the equation shows, to keep noise at a minimum, small

resistor values should be used. At higher amplifier gain

configuration where R2 is reduced, the noise due to IN-, R2,

and R1 decreases and the noise caused by IN+, VN, and R3

starts to dominate. Because noise is summed in a root-

mean-squares method, noise sources sma ller than 25% of

the largest noise source can be ignored. T his can greatly

simplify the formula and make noise calculation much easier

to calculate.

VIN

VOUT

FIGURE 1.

+VON

VIN

IN+

IN-

VR3

VR2

VR1

FIGURE 2.

VRX 4kTRx=(EQ. 1)

VON BW=VN21R1

-------

⎝⎠

⎜⎟

⎛⎞

×IN-2R12IN+2R321R1

-------

⎝⎠

⎜⎟

⎛⎞

××+×4KTR

14KTR

2R1

-------

⎝⎠

⎜⎟

⎛⎞

××××+××× 4KTR

31R1

-------

⎝⎠

⎜⎟

⎛⎞

××××++ +

⎝ ⎠

⎜ ⎟

⎛ ⎞

(EQ. 2)

EL2126

16 FN7046.3

April 16, 2007

Output Drive Capability

The EL2126 is designed to drive low impedance load. It can

easily drive 6VP-P signal in to a 100Ω load. This high output

drive capability makes the EL2126 an ideal choice for RF, IF,

and video applications. Furthermore, the EL2126 is

current-limited at the output, allowing it to with stand

momentary short to ground. However, the power dissipation

with output-shorted cannot exceed the power dissipation

capability of the package.

Driving Cables and Capacitive Loads

Although the EL2126 is designed to drive low impedance

load, capacitive loads will decreases the amplifier's phase

margin. As shown in the performance curves, capacitive

load can result in peaking, overshoo t and possible

oscillation. For optimum AC performance, capacitive loads

should be reduced as much as possible or isolated with a

series resistor between 5Ω to 20Ω. When driving coaxial

cables, double termination is alwa ys recommended for

reflection-free performance. When pro perly terminated, the

capacitance of the coaxial cable will not add to the capacitive

load seen by the amplifier.

Power Supply Bypassing And Printed Circuit

Board Layout

As with any high frequency devices, good printed circuit

board layout is essential for optimum performance. Ground

plane construction is highly recommended. Lead lengths

should be kept as short as possible. The power supply pins

must be closely bypassed to reduce the risk of oscillation.

The combination of a 4.7µF tantalum capacitor in parallel

with 0.1µF ceramic capacitor has been proven to work well

when placed at each supply pin. For single supply operation,

where pin 4 (VS-) is connected to the ground plane, a single

4.7µF tantalum capacitor in parallel with a 0.1µF ceramic

capacitor acros s pins 7 (VS+) and pin 4 (VS-) will suffice.

For good AC performance, parasitic capacitance should be

kept to a minimum. Ground plane construction again should

be used. Small chip resistors are recommended to minimize

series inductance. Use of sockets should be avoided since

they add parasitic inductance and capacitance which will

result in additional peaking and overshoot.

Supply Voltage Range and Single Supply

Operation

The EL2126 has been designed to operate with supply

voltage range of ±2.5V to ±15V. With a single supply, the

EL2126 will operate from +5V to +30V. Pins 4 and 7 are the

power supply pins. The positive power supply is connected

to pin 7. When used in single supply mode, pin 4 is

connected to ground. Wh en used in dual supply mode, the

negative power supply is connected to pin 4.

As the power supp l y vol tage decreases from +30V to +5V, it

becomes necessary to pay special attention to the input

voltage range. The EL2126 has an input voltage range of

0.4V from the negative supply to 1.2V from the positive

supply. So, for example, on a single +5V supply, the EL2126

has an input voltage range which spans from 0.4V to 3.8V.

The output range of the EL2126 is also quite large, on a +5V

supply, it swings from 0.4V to 3.8V.

EL2126

17 FN7046.3

April 16, 2007

EL2126

Small Outline Package Family (SO)

GAUGE

PLANE

A1 L

DETAIL X 4° ±4°

SEATING

PLANE

0.010 BMCA

0.004 C

0.010 BMCA

(N/2)

NN (N/2)+1

PIN #1

I.D. MARK

h X 45°

SEE DETAIL “X”

0.010

MDP0027

SMALL OUTLINE PACKAGE FAMILY (SO)

SYMBOL

INCHES

TOLERANCE NOTESSO-8 SO-14 SO16

(0.150”) SO16 (0.300”)

(SOL-16) SO20

(SOL-20) SO24

(SOL-24) SO28

(SOL-28)

A0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -

A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -

A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -

b0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -

c0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -

D0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3

E0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -

E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3

e0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -

L0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -

L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -

h0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -

N 8 14 16 16 20 24 28 Reference -

Rev. M 2/07

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994

18 FN7046.3

April 16, 2007

EL2126

Small Outline Transistor Plastic Packages (SOT23-5)

AA1

0.20 (0.008) M

0.10 (0.004) C

-C-

SEATING

PLANE

123

VIEW C

4X θ1

GAUGE PLANE

SEATING

αL2

PLANE

BASE METAL

WITH

PLATING

P5.064

5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A0.036 0.057 0.90 1.45 -

A1 0.000 0.0059 0.00 0.15 -

A2 0.036 0.051 0.90 1.30 -

b0.012 0.020 0.30 0.50 -

b1 0.012 0.018 0.30 0.45

c0.003 0.009 0.08 0.22 6

c1 0.003 0.008 0.08 0.20 6

D0.111 0.118 2.80 3.00 3

E0.103 0.118 2.60 3.00 -

E1 0.060 0.067 1.50 1.70 3

e 0.0374 Ref 0.95 Ref -

e1 0.0748 Ref 1.90 Ref -

L0.014 0.022 0.35 0.55 4

L1 0.024 Ref. 0.60 Ref.

L2 0.010 Ref. 0.25 Ref.

N5 55

R0.004 -0.10 -

R1 0.004 0.010 0.10 0.25

α0o8o0o8o-

Rev. 2 9/03

NOTES:

1. Dimensioning and tolerance per ASME Y14.5M-1994.

2. Package conforms to EIAJ SC-74 and JEDEC MO178AA.

3. Dimensions D and E1 are exclusive of mold flash, protrusions,

or gate burrs.

4. Footlength L measured at reference to gauge plane.

5. “N” is the number of terminal positions.

6. These Dimensions apply to the flat section of the lead between

0.08mm and 0.15mm from the lead tip.

7. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are for reference only.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Intersi l or i t s sub sidi ari es.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7046.3

April 16, 2007

EL2126

SOT-23 Package Family

321

0.15 DC

2X 0.20 C

B0.20 MDC A-B

2 3

SEATING

PLANE

0.10 C

1 3

0.15 A-BC

(L1)

0.25

0° +3°

-0°

GAUGE

PLANE

MDP0038

SOT-23 PACKAGE FAMILY

SYMBOL

MILLIMETERS

TOLERANCESOT23-5 SOT23-6

A 1.45 1.45 MAX

A1 0.10 0.10 ±0.05

A2 1.14 1.14 ±0.15

b 0.40 0.40 ±0.05

c 0.14 0.14 ±0.06

D 2.90 2.90 Basic

E 2.80 2.80 Basic

E1 1.60 1.60 Basic

e 0.95 0.95 Basic

e1 1.90 1.90 Basic

L 0.45 0.45 ±0.10

L1 0.60 0.60 Reference

N 5 6 Reference

Rev. F 2/07

NOTES:

1. Plastic or metal protrusions of 0.25mm maximum per side are not

included.

2. Plastic interlead protrusions of 0.25mm maximum per side are not

included.

3. This dimension is measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

5. Index area - Pin #1 I.D. will be located within the indicated zone

(SOT23-6 only).

6. SOT23-5 version has no center lead (shown as a dashed line).