ADC0808, ADC0809 CMOS ANALOG-TO-DIGITAL CONVERTERS WITH 8-CHANNEL MULTIPLEXERS SLAS036 - JUNE 1981 - REVISED MAY 1988 D D D D D D D D D D D D Total Unadjusted Error . . . 0.75 LSB Max for ADC0808 and 1.25 LSB Max for ADC0809 Resolution of 8 Bits 100-s Conversion Time Ratiometric Conversion Monotonicity Over the Entire A/D Conversion Range No Missing Codes Easy interface with Microprocessors Latched 3-State Outputs Latched Address inputs Single 5-V Supply Low Power Consumption Designed to Be Interchangeable With National Semiconductor ADC0808, ADC0809 N PACKAGE (TOP VIEW) 3 4 5 INPUTS 6 7 START EOC 2-5 OE CLK VCC REF+ GND 2-7 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 2 1 INPUTS 0 A B ADDRESS C ALE 2-1 (MSB) 2-2 2-3 2-4 2-8 (LSB) REF- 2 -6 FN PACKAGE description INPUT 6 INPUT 5 INPUT 4 INPUT 3 INPUT 2 INPUT 1 INPUT 0 (TOP VIEW) The ADC0808 and ADC0809 are monolithic CMOS devices with an 8-channel multiplexer, an 8-bit analog-to-digital (A/D) converter, and microprocessor-compatible control logic. The 8-channel multiplexer can be controlled by a microprocessor through a 3-bit address decoder with address load to select any one of eight single-ended analog switches connected directly to the comparator. The 8-bit A/D converter uses the successive-approximation conversion technique featuring a high-impedance threshold detector, a switched-capacitor array, a sampleand-hold, and a successive-approximation register (SAR). Detailed information on interfacing to most popular microprocessors is readily available from the factory. 4 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 A B ADDRESS C ALE 2 -1(MSB) 2 -2 2 -3 REF+ GND 2 -7 2 -6 REF- 2-8(LSB) 2 -4 INPUT START EOC 2 -5 OE CLK VCC The comparison and converting methods used eliminate the possibility of missing codes, nonmonotonicity, and the need for zero or full-scale adjustment. Also featured are latched 3-state outputs from the SAR and latched inputs to the multiplexer address decoder. The single 5-V supply and low power requirements make the ADC0808 and ADC0809 especially useful for a wide variety of applications. Ratiometric conversion is made possible by access to the reference voltage input terminals. The ADC0808 and ADC0809 are characterized for operation from - 40C to 85C. Copyright 1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 1 ADC0808, ADC0809 CMOS ANALOG-TO-DIGITAL CONVERTERS WITH 8-CHANNEL MULTIPLEXERS SLAS036 - JUNE 1981 - REVISED MAY 1988 functional block diagram (positive logic) Sample-and-Hold Binary-Weighted Capacitors REF+ REF- 0 1 2 INPUTS 3 4 5 6 7 CLOCK START OE ADDRESS A ADDRESS B ADDRESS C ALE 12 16 Switch Matrix Threshold Detector 26 27 28 1 2 Output Latches Analog Multiplexer 3 Timing and Control 4 5 EN 7 10 6 9 25 24 23 Address Decoder 22 FUNCTION TABLE INPUTS ALE SELECTED ANALOG CHANNEL 0 1 2 3 4 5 6 7 ADDRESS C B A L L L L H H H H L L H H L L H H L H L H L H L H H = high level, L = low level = low-to-high transition 2 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 17 14 15 8 18 19 20 21 2-8 (LSB) 2-7 2-6 2-5 2-4 2-3 2-2 2-1 (MSB) (EOC) ADC0808, ADC0809 CMOS ANALOG-TO-DIGITAL CONVERTERS WITH 8-CHANNEL MULTIPLEXERS SLAS036 - JUNE 1981 - REVISED MAY 1988 operating sequence 1/f CLK START 50% 50% tw(S) ALE 50% 50% tw(ALC) Address Stable ADDRESS 50% tsu INPUT 50% th Analog Value Input Stable Multiplex Output Internal EOC Analog Value 50% 50% td(EOC) tconv 50% OE 50% ten Hi-Z State 90% 10% Latch Outputs * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * tdis 90% 10% 3 ADC0808, ADC0809 CMOS ANALOG-TO-DIGITAL CONVERTERS WITH 8-CHANNEL MULTIPLEXERS SLAS036 - JUNE 1981 - REVISED MAY 1988 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V Input voltage range: Control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 15 V All other inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VCC + 0.3 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . . . . . . . . . . . . . . . . . . . . . 260C NOTE 1: All voltage values are with respect to network ground terminal. recommended operating conditions Supply voltage, VCC MIN NOM MAX 4.5 5 6 V VCC 0 VCC + 0.1 - 0.1 V Positive reference voltage, Vref+ (see Note 2) Negative reference voltage, Vref- Differential reference voltage, Vref+ - Vref- UNIT V 5 High-level input voltage, VIH V VCC - 1.5 V Low-level input voltage, VIL Operating free-air temperature, TA NOTE 2: Care must be taken that this rating is observed even during power-up. - 40 1.5 V 85 C electrical characteristics over recommended operating free-air temperature range. VCC = 4.75 V to 5.25 V (unless otherwise noted) PARAMETER TEST CONDITIONS VOH High-level output voltage VOL Low level output voltage Low-level IOZ Off state (high-impedance-state) Off-state (high impedance state) output current II IIL Control input current at maximum input voltage ICC Ci Supply current CO Output capacitance, data outputs IO = - 360 A IO = 1.6 mA Data outputs End of conversion TYP Low-level control input current Input capacitance, control inputs UNIT V 0.45 0.45 3 V A VO = 0 VI = 15 V -3 1 A VI = 0 fclock = 640 kHz -1 A 0.3 3 mA 10 15 pF 10 15 TA = 25C TA = 25C 1000 Typical values are at VCC = 5 V and TA = 25C. * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * MAX VCC- 0.4 IO = 1.2 mA VO = VCC Resistance from REF+ to REF- 4 MIN pF k ADC0808, ADC0809 CMOS ANALOG-TO-DIGITAL CONVERTERS WITH 8-CHANNEL MULTIPLEXERS SLAS036 - JUNE 1981 - REVISED MAY 1988 analog multiplexer PARAMETER lon TEST CONDITIONS on state current (see Note 3) Channel on-state loff ff Channel off-state off state current VI = VCC, VI = 0.1 V, fclock = 640 kHz fclock = 640 kHz VCC = 5 V,, TA = 25C VI = 5 V VI = 0 VCC = 5 V VI = 5 V VI = 0 MIN TYP MAX 2 -2 10 200 - 10 - 200 1 -1 UNIT A nA A Typical values are at VCC = 5 V and TA = 25C. NOTE 3: Channel on-state current is primarily due to the bias current into or out of the threshold detector, and it varies directly with clock frequency. timing requirements, VCC = Vref+ = 5 V, Vref - = 0 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 10 640 1280 kHz 90 100 116 fclock tconv Clock frequency tw(s) tw(ALE) Pulse duration, START 200 ns Pulse duration ALE 200 ns tsu th Setup time, ADDRESS 50 ns Hold time, ADDRESS 50 td Delay time, EOC Conversion time See Note 4 See Notes 4 and 5 s ns 0 14.5 s operating characteristics, TA = 25C, VCC = Vref+ = 5 V, Vref - = 0 V, fclock = 640 kHz (unless otherwise noted) ADC0808 PARAMETER kSVS Supply voltage sensitivity TEST CONDITIONS VCC = Vref+ = 4.75 V to 5.25 V, TA = - 40C to 85C, See Note 6 MIN TYP ADC0809 MAX 0.05 MIN TYP MAX UNIT 0.05 %/V Linearity error (see Note 7) 0.25 0.5 LSB Zero error (see Note 8) 0.25 0.25 LSB Total unadjusted error (see Note 9) 0.25 TA = 25C TA = - 40C to 85C 0.5 0.75 0.5 1.25 LSB 1 TA = 0C to 70C CL = 50 pF, ten Output enable time RL = 10 k 80 250 80 250 ns tdis Output disable time CL = 10 pF, RL = 10 k 105 250 105 250 ns Typical values for all except supply voltage sensitivity are at VCC = 5 V, and all are at TA = 25C. NOTES: 4. Refer to the operating sequence diagram. 5. For clock frequencies other than 640 kHz, td(EOC) maximum is 8 clock periods plus 2 s. 6. Supply voltage sensitivity relates to the ability of an analog-to-digital converter to maintain accuracy as the supply voltage varies. The supply and Vref+ are varied together and the change in accuracy is measured with respect to full-scale. 7. Linearity error is the maximum deviation from a straight line through the end points of the A/D transfer characteristic. 8. Zero error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference between 11111111 and the converted output for full-scale input voltage. 9. Total unadjusted error is the maximum sum of linearity error, zero error, and full-scale error. * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 5 ADC0808, ADC0809 CMOS ANALOG-TO-DIGITAL CONVERTERS WITH 8-CHANNEL MULTIPLEXERS SLAS036 - JUNE 1981 - REVISED MAY 1988 PRINCIPLES OF OPERATION The ADC0808 and ADC0809 each consists of an analog signal multiplexer, an 8-bit successive-approximation converter, and related control and output circuitry. multiplexer The analog multiplexer selects 1 of 8 single-ended input channels as determined by the address decoder. Address load control loads the address code into the decoder on a low-to-high transition. The output latch is reset by the positive-going edge of the start pulse. Sampling also starts with the positive-going edge of the start pulse and lasts for 32 clock periods. The conversion process may be interrupted by a new start pulse before the end of 64 clock periods. The previous data will be lost if a new start of conversion occurs before the 64th clock pulse. Continuous conversion may be accomplished by connecting the end-of-conversion output to the start input. If used in this mode, an external pulse should be applied after power up to assure start up. converter The CMOS threshold detector in the successive-approximation conversion system determines each bit by examining the charge on a series of binary-weighted capacitors (Figure 1). In the first phase of the conversion process , the analog input is sampled by closing switch SC and all ST switches, and by simultaneously charging all the capacitors to the input voltage. In the next phase of the conversion process, all ST and SC switches are opened and the threshold detector begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference voltage. In the switching sequence, all eight capacitors are examined separately until all 8 bits are identified, and then the charge-convert sequence is repeated. in the first step of the conversion phase, the threshold detector looks at the first capacitor (weight = 128). Node 128 of this capacitor is switched to the reference voltage, and the equivalent nodes of all the other capacitors on the ladder are switched to REF-. If the voltage at the summing node is greater than the trip-point of the threshold detector (approximately one-half the VCC voltage), a bit is placed in the output register, and the 128-weight capacitor is switched to REF-. If the voltage at the summing node is less than the trip point of the threshold detector, this 128-weight capacitor remains connected to REF+ through the remainder of the capacitor-sampling (bit-counting) process. The process is repeated for the 64-weight capacitor, the 32-weight capacitor, and so forth down the line, until all bits are counted. With each step of the capacitor-sampling process, the initial charge is redistributed among the capacitors. The conversion process is successive approximation, but relies on charge redistribution rather than a successive-approximation register (and reference DAC) to count and weigh the bits from MSB to LSB. SC Threshold Detector 128 64 32 REF+ Node 128 REF- REF+ REF- ST 16 REF+ REF- ST 8 REF+ REF- ST 4 REF+ REF- ST 2 REF+ REF- ST 1 REF+ REF- ST REF+ REF- ST To Output Latches 1 REF- ST ST VI Figure 1. Simplified Model of the Successive-Approximation System 6 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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