ADC0808, ADC0809
CMOS ANALOG-TO-DIGITAL CONVERTERS
WITH 8-CHANNEL MULTIPLEXERS
SLAS036 – JUNE 1981 – REVISED MAY 1988
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
D
Total Unadjusted Error... ±0.75 LSB Max
for ADC0808 and ±1.25 LSB Max for
ADC0809
D
Resolution of 8 Bits
D
100-µs Conversion Time
D
Ratiometric Conversion
D
Monotonicity Over the Entire A/D
Conversion Range
D
No Missing Codes
D
Easy interface with Microprocessors
D
Latched 3-State Outputs
D
Latched Address inputs
D
Single 5-V Supply
D
Low Power Consumption
D
Designed to Be Interchangeable With
National Semiconductor ADC0808,
ADC0809
description
The ADC0808 and ADC0809 are monolithic
CMOS devices with an 8-channel multiplexer, an
8-bit analog-to-digital (A/D) converter, and
microprocessor-compatible control logic. The
8-channel multiplexer can be controlled by a
microprocessor through a 3-bit address decoder
with address load to select any one of eight
single-ended analog switches connected directly
to the comparator. The 8-bit A/D converter uses
the successive-approximation conversion tech-
nique featuring a high-impedance threshold
detector, a switched-capacitor array, a sample-
and-hold, and a successive-approximation regis-
ter (SAR). Detailed information on interfacing to
most popular microprocessors is readily available
from the factory.
The comparison and converting methods used eliminate the possibility of missing codes, nonmonotonicity , and
the need for zero or full-scale adjustment. Also featured are latched 3-state outputs from the SAR and latched
inputs to the multiplexer address decoder. The single 5-V supply and low power requirements make the
ADC0808 and ADC0809 especially useful for a wide variety of applications. Ratiometric conversion is made
possible by access to the reference voltage input terminals.
The ADC0808 and ADC0809 are characterized for operation from –40°C to 85°C.
Copyright 1988, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
3
4
5
6
7
START
EOC
2–5
OE
CLK
VCC
REF+
GND
2–7
2
1
0
A
B
C
ALE
2–1 (MSB)
2–2
2–3
2–4
2–8 (LSB)
REF–
2–6
N PACKAGE
(TOP VIEW)
INPUTS INPUTS
ADDRESS
3212827
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
A
B
C
ALE
2–1(MSB)
2–2
2–3
INPUT
START
EOC
2–5
OE
CLK
VCC
426
14 15 16 1718
REF+
GND
2
2
REF–
2 (LSB)
2
INPUT 6
INPUT 5
INPUT 4
INPUT 3
INPUT 2
INPUT 1
INPUT 0
FN PACKAGE
(TOP VIEW)
ADDRESS
–7
–6
–8 –4
ADC0808, ADC0809
CMOS ANALOG-TO-DIGITAL CONVERTERS
WITH 8-CHANNEL MULTIPLEXERS
SLAS036 – JUNE 1981 – REVISED MAY 1988
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
functional block diagram (positive logic)
REF–
REF+
7
EN
(EOC)
2–1 (MSB)
2–2
2–3
2–4
2–5
2–6
2–7 (LSB)
–8
2
8
21
20
19
18
15
14
17
ALE
ADDRESS C
ADDRESS B
ADDRESS A
OE
START
22
23
24
25
CLOCK
9
6
10
INPUTS
7
6
5
4
3
2
1
0
Address
Decoder
Output
Latches
5
4
3
2
1
28
27
26
Analog
Multiplexer
Timing
and
Control
Threshold
Detector
Switch
Matrix
Binary-Weighted
Capacitors
16
12
Sample-and-Hold
L
H
L
H
L
H
L
H
H = high level, L = low level
↑ = low-to-high transition
SELECTED
ANALOG
CHANNEL
INPUTS
ADDRESS ALE
CBA
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
↑
↑
↑
↑
↑
↑
↑
↑
0
1
2
3
4
5
6
7
FUNCTION TABLE
ADC0808, ADC0809
CMOS ANALOG-TO-DIGITAL CONVERTERS
WITH 8-CHANNEL MULTIPLEXERS
SLAS036 – JUNE 1981 – REVISED MAY 1988
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
operating sequence
Latch Outputs
OE
EOC
Multiplex Output
Internal
INPUT
ADDRESS
ALE
START
CLK
Analog Value
Hi–Z State
10%
90% 10%
90%
50%50%
tdis
ten
tconv
50% 50%
Analog Value
tsu th
50%50%
Address Stable
tw(ALC)
50%50%
tw(S)
50%50%
1/f
td(EOC)
Input Stable
ADC0808, ADC0809
CMOS ANALOG-TO-DIGITAL CONVERTERS
WITH 8-CHANNEL MULTIPLEXERS
SLAS036 – JUNE 1981 – REVISED MAY 1988
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range: Control inputs –0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
All other inputs –0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 10 seconds: FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package 260°C. . . . . . . . . . . . . . . . . . . . .
NOTE 1: All voltage values are with respect to network ground terminal.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC 4.5 5 6 V
Positive reference voltage, V ref+ (see Note 2) VCC VCC+0.1 V
Negative reference voltage, V ref– 0–0.1 V
Differential reference voltage, Vref+ – Vref– 5 V
High-level input voltage, VIH VCC–1.5 V
Low-level input voltage, VIL 1.5 V
Operating free-air temperature, TA–40 85 °C
NOTE 2: Care must be taken that this rating is observed even during power-up.
electrical characteristics over recommended operating free-air temperature range. VCC = 4.75 V
to 5.25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VOH High-level output voltage IO = –360 µA VCC–0.4 V
VOL
Low level out
p
ut voltage
Data outputs IO = 1.6 mA 0.45
V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
End of conversion IO = 1.2 mA 0.45
V
IOZ
Off state (high im
p
edance state) out
p
ut current
VO = VCC 3
µA
I
OZ
Off
-
state
(high
-
impedance
-
state)
o
u
tp
u
t
c
u
rrent
VO = 0 –3 µ
A
IIControl input current at maximum input voltage VI = 15 V 1 µA
IIL Low-level control input current VI = 0 –1 µA
ICC Supply current fclock = 640 kHz 0.3 3 mA
CiInput capacitance, control inputs TA = 25°C 10 15 pF
COOutput capacitance, data outputs TA = 25°C 10 15 pF
Resistance from REF+ to REF– 1000 kΩ
†Typical values are at VCC = 5 V and TA = 25°C.
ADC0808, ADC0809
CMOS ANALOG-TO-DIGITAL CONVERTERS
WITH 8-CHANNEL MULTIPLEXERS
SLAS036 – JUNE 1981 – REVISED MAY 1988
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
analog multiplexer
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
l
Channel on state current (see Note 3)
VI = VCC, fclock = 640 kHz 2
µA
l
on
Channel
on
-
state
c
u
rrent
(see
Note
3)
VI = 0.1 V,fclock = 640 kHz –2 µ
A
V
CC
= 5 V, VI = 5 V 10 200
nA
lff
Channel off state current
CC ,
TA = 25°CVI = 0 –10 –200
nA
l
off
Channel
off
-
state
c
u
rrent
VCC =5V
VI = 5 V 1
µA
V
CC =
5
V
VI = 0 –1 µ
A
†Typical values are at VCC = 5 V and TA = 25°C.
NOTE 3: Channel on-state current is primarily due to the bias current into or out of the threshold detector, and it varies directly with clock frequency.
timing requirements, VCC = Vref+ = 5 V, Vref– = 0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
fclock Clock frequency 10 640 1280 kHz
tconv Conversion time See Note 4 90 100 116 µs
tw(s) Pulse duration, START 200 ns
tw(ALE) Pulse duration ALE 200 ns
tsu Setup time, ADDRESS 50 ns
thHold time, ADDRESS 50 ns
tdDelay time, EOC See Notes 4 and 5 0 14.5 µs
operating characteristics, TA = 25°C, VCC = Vref+ = 5 V, Vref– = 0 V, fclock = 640 kHz (unless otherwise
noted)
PARAMETER
ADC0808 ADC0809
UNIT
PARAMETER
MIN TYP†MAX MIN TYP†MAX
UNIT
kSVS Supply voltage sensitivity VCC = Vref+ = 4.75 V to 5.25 V,
TA = –40°C to 85°C, See Note 6 ±0.05 ±0.05 %/V
Linearity error (see Note 7) ±0.25 ±0.5 LSB
Zero error (see Note 8) ±0.25 ±0.25 LSB
TA = 25°C±0.25 ±0.5 ±0.5
Total unadjusted error (see Note 9) TA = –40°C to 85°C±0.75 ±1.25 LSB
TA = 0°C to 70°C±1
ten Output enable time CL = 50 pF, RL = 10 kΩ80 250 80 250 ns
tdis Output disable time CL = 10 pF, RL = 10 kΩ105 250 105 250 ns
†Typical values for all except supply voltage sensitivity are at VCC = 5 V, and all are at TA = 25°C.
NOTES: 4. Refer to the operating sequence diagram.
5. For clock frequencies other than 640 kHz, td(EOC) maximum is 8 clock periods plus 2 µs.
6. Supply voltage sensitivity relates to the ability of an analog-to-digital converter to maintain accuracy as the supply voltage varies.
The supply and Vref+ are varied together and the change in accuracy is measured with respect to full-scale.
7. Linearity error is the maximum deviation from a straight line through the end points of the A/D transfer characteristic.
8. Zero error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
9. Total unadjusted error is the maximum sum of linearity error, zero error, and full-scale error.
ADC0808, ADC0809
CMOS ANALOG-TO-DIGITAL CONVERTERS
WITH 8-CHANNEL MULTIPLEXERS
SLAS036 – JUNE 1981 – REVISED MAY 1988
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PRINCIPLES OF OPERATION
The ADC0808 and ADC0809 each consists of an analog signal multiplexer , an 8-bit successive-approximation
converter, and related control and output circuitry.
multiplexer
The analog multiplexer selects 1 of 8 single-ended input channels as determined by the address decoder.
Address load control loads the address code into the decoder on a low-to-high transition. The output latch is
reset by the positive-going edge of the start pulse. Sampling also starts with the positive-going edge of the start
pulse and lasts for 32 clock periods. The conversion process may be interrupted by a new start pulse before
the end of 64 clock periods. The previous data will be lost if a new start of conversion occurs before the 64th
clock pulse. Continuous conversion may be accomplished by connecting the end-of-conversion output to the
start input. If used in this mode, an external pulse should be applied after power up to assure start up.
converter
The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capacitors (Figure 1). In the first phase of the conversion
process , the analog input is sampled by closing switch SC and all ST switches, and by simultaneously charging
all the capacitors to the input voltage.
In the next phase of the conversion process, all ST and SC switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference voltage.
In the switching sequence, all eight capacitors are examined separately until all 8 bits are identified, and then
the charge-convert sequence is repeated. in the first step of the conversion phase, the threshold detector looks
at the first capacitor (weight = 128). Node 128 of this capacitor is switched to the reference voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF–. If the voltage at the summing
node is greater than the trip-point of the threshold detector (approximately one-half the VCC voltage), a bit is
placed in the output register, and the 128-weight capacitor is switched to REF–. If the voltage at the summing
node is less than the trip point of the threshold detector , this 128-weight capacitor remains connected to REF+
through the remainder of the capacitor-sampling (bit-counting) process. The process is repeated for the
64-weight capacitor, the 32-weight capacitor, and so forth down the line, until all bits are counted.
With each step of the capacitor-sampling process, the initial charge is redistributed among the capacitors. The
conversion process is successive approximation, but relies on charge redistribution rather than a
successive-approximation register (and reference DAC) to count and weigh the bits from MSB to LSB.
Node 128
VI
To Output
Latches
Threshold
Detector
SC
REF+
REF–
128
ST
REF+
REF–
64
ST
REF+
REF–
32
ST
REF+
REF–
16
ST
REF+
REF–
8
ST
REF+
REF–
4
ST
REF+
REF–
2
STST
1
REF– ST
REF–
REF+
1
Figure 1. Simplified Model of the Successive-Approximation System
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Copyright 1998, Texas Instruments Incorporated