SLLS163E − J ULY 1993 − REVISED APRIL 2006
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DMeets or Exceeds EIA Standard RS-485
DDesigned for High-Speed Multipoint
Transmission on Long Bus Lines in Noisy
Environments
DSupport Data Rates up to and Exceeding
Ten Million Transfers Per Second
DCommon-Mode Output Voltage Range of
−7 V to 12 V
DPositive- and Negative-Current Limiting
DLow Power Consumption...1.5 mA Max
(Output Disabled)
DFunctionally Interchangeable With SN75172
description
The SN65LBC172 and SN75LBC172 are
monolithic quadruple differential line drivers with
3-state outputs. Both devices are designed to
meet the requirements of EIA Standard RS-485.
These devices are optimized for balanced
multipoint bus transmission at data rates up to and
exceeding 10 million bits per second. Each driver
features wide positive and negative common-
mode output voltage ranges, current limiting, and
thermal-shutdown circuitry making it suitable for
party-line applications in noisy environments.
Both devices are designed using LinBiCMOS,
facilitating ultra-low power consumption and
inherent robustness.
Both the SN65LBC172 and SN75LBC172 provide
positive- and negative-current limiting and
thermal shutdown for protection from line fault
conditions on the transmission bus line. These
devices offer optimum performance when
used with the SN75LBC173 or SN75LBC175
quadruple line receivers. The SN65LBC172 and
SN75LBC172 are available in the 16-pin DIP
package (N) and the 20-pin wide-body small-
outline inline-circuit (SOIC) package (DW).
The SN75LBC172 is characterized for operation
over the commercial temperature range of 0°C to
70°C. The SN65LBC172 is characterized over the
industrial temperature range of −40°C to 85°C.
LinBiCMOS is a trademark of Texas Instruments Incorporated.
Copyright 2001−2006, Texas Instruments Incorporated
!" # $%&" !# '%()$!" *!"&+
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1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1A
1Y
1Z
G
2Z
2Y
2A
GND
VCC
4A
4Y
4Z
G
3Z
3Y
3A
N PACKAGE
(TOP VIEW)
NC − No internal connection
FUNCTION TABLE
(each driver)
INPUT ENABLES OUTPUTS
AGG
YZ
H
L
H
L
X
H = high level, L = low level,
X = irrelevant, Z = high impedance (off)
H
H
X
X
L
X
X
L
L
H
HL
LH
HL
LH
ZZ
1A
1Y
NC
1Z
G
2Z
NC
2Y
2A
GND
VCC
4A
4Y
NC
4Z
G
3Z
NC
3Y
3A
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DW PACKAGE
(TOP VIEW)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SLLS163E − JULY 1993 − REVISED APRIL 2006
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol†
4A
3A
2A
1A
G
G
4Z
4Y
3Z
3Y
2Z
2Y
1Z
1Y
13
14
11
10
5
6
3
2
15
9
7
1
12
4≥1EN
†This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Pin numbers shown are for the N package.
logic diagram (positive logic)
4A
3A
2A
1A
G
G
15
9
7
1
12
4
4Z
4Y
3Z
3Y
2Z
2Y
1Z
1Y
13
14
11
10
5
6
3
2
schematic diagrams of inputs and outputs
Input
50 µA
VCC
Driver Output
VCC
200 Ω
ALL INPUTS Y OR Z OUTPUT
SLLS163E − J ULY 1993 − REVISED APRIL 2006
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings†
Supply voltage range, VCC (see Note 1) −0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO −10 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at A, G, G −0.3 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous power dissipation Internally limited‡
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡The maximum operating junction temperature is internally limited. Use the dissipation rating table to operate below this temperature.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
High-level input voltage, VIH 2 V
Low-level input voltage, VIL 0.8 V
Voltage at any bus terminal (separately or common mode), VO
Y or Z
12
V
Voltage at any bus terminal (separately or common mode), VOY or Z −7 V
High-level output current, IOH Y or Z −60 mA
Low-level output current, IOL Y or Z 60 mA
Continuous total power dissipation See Dissipation Rating Table
Junction temperature, TJ140 °C
Operating free-air temperature, TA
SN65LBC172 −40 85
°C
Operating free-air temperature, T
ASN75LBC172 0 70 °
C
DISSIPATION RATING TABLE
PACKAGE THERMAL
MODEL TA < 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING
DW
Low K†1094 mW 10.4 mW/°C625 mW 469 mW
DW High K‡1669 mW 15.9 mW/°C 954 mW 715 mW
N1150 mW 9.2 mW/°C736 mW 598 mW
†In accordance with the low effective thermal conductivity metric definitions of EIA/JESD 51−3.
‡In accordance with the high effective thermal conductivity metric definitions of EIA/JESD 51−7.
SLLS163E − JULY 1993 − REVISED APRIL 2006
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK Input clamp voltage II = −18 mA −1.5 V
RL = 54
Ω
,
SN65LBC172 1.1 1.8 5
|VOD|
Differential output voltage‡
RL = 54 Ω,
See Figure 1 SN75LBC172 1.5 1.8 5
V
|VOD|
Differential output voltage‡
RL = 60
Ω
,
SN65LBC172 1.1 1.7 5 V
RL = 60 Ω,
See Figure 2 SN75LBC172 1.5 1.7 5
∆|VOD|Change in magnitude of common-mode output voltage§±0.2 V
VOC
Common-mode output voltage
RL = 54 Ω,
See Figure 1
3
V
VOC Common-mode output voltage RL = 54 Ω,See Figure 1
3
−1 V
∆|VOC|Change in magnitude of common-mode output voltage§±0.2 V
IOOutput current with power off VCC = 0, VO = − 7 V to 12 V ±100 µA
IOZ High-impedance-state output current VO = − 7 V to 12 V ±100 µA
IIH High-level input current VI = 2.4 V −100 µA
IIL Low-level input current VI = 0.4 V −100 µA
IOS Short-circuit output current VO = −7 V to 12 V ±250 mA
ICC
Supply current (all drivers)
No load
Outputs enabled 7
mA
I
CC
Supply current (all drivers)
No load
Outputs disabled 1.5
mA
†All typical values are at VCC = 5 V and TA = 25°C.
‡The minimum VOD specification does not fully comply with EIA-485 at operating temperatures below 0°C. The lower output signal should be used
to determine the maximum signal-transmission distance.
§∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input changes from a high level to a low
level.
switching characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(OD) Differential output delay time
RL = 54 Ω,
See Figure 3
211 20
ns
tt(OD) Differential output transition time RL = 54 Ω,See Figure 3 10 15 25 ns
tPZH Output enable time to high level RL = 110 Ω,See Figure 4 20 30 ns
tPZL Output enable time to low level RL = 110 Ω,See Figure 5 21 30 ns
tPHZ Output disable time from high level RL = 110 Ω,See Figure 4 48 70 ns
tPLZ Output disable time from low level RL = 110 Ω,See Figure 5 21 30 ns
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOC
2
RL
2
RL
VOD2
Figure 1. Differential and Common-Mode Output Voltages
R2 = 375 Ω
VOD
RL = 60 Ω
Vtest
Vtest
0 V or 3 V A
R1 = 375 Ω
Y
Z
−7 V < Vtest < 12 V
G at 5 V
or
G at 0 V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, duty cycle = 50%, tr ≤ 5 ns,
tf ≤ 5 ns, ZO = 50 Ω.
B. CL includes probe and stray capacitance.
Figure 2. Driver VOD Test Circuit
VOLTAGE WAVEFORMS
50%
tt(OD)
td(OD)
10%
tt(OD)
≈ 2.5 V
≈− 2.5 V
90%
50%
Output
td(OD)
0 V
3 V
Input
TEST CIRCUIT
Output
CL = 50 pF
(see Note B)
RL = 54 Ω
50 Ω
1.5 V 1.5 V
3 V
Input
Generator
(see Note A)
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, duty cycle = 50%, tr ≤ 5 ns,
tf ≤ 5 ns, ZO = 50 Ω.
B. CL includes probe and stray capacitance.
Figure 3. Driver Differential-Output Test Circuit and Delay and Transition-Time Waveforms
SLLS163E − JULY 1993 − REVISED APRIL 2006
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
RL = 110 Ω
VOLTAGE WAVEFORMSTEST CIRCUIT
Output
Input
tPZH
1.5 V
2.3 V
0.5 V
tPHZ
1.5 V
VOH
Voff ≈ 0 V
0 V
3 V
Output
Generator
(see Note A)
0 V or 3 V
50 Ω
S1
CL = 50 pF
(see Note B)
Input
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, duty cycle = 50%, tr ≤ 5 ns,
tf ≤ 5 ns, ZO = 50 Ω.
B. CL includes probe and stray capacitance.
Figure 4. tPZH and tPHZ Test Circuit and Voltage Waveforms
VOLTAGE WAVEFORMSTEST CIRCUIT
Output
RL = 110 Ω
CL = 50 pF
(see Note B)
50 Ω
5 V
5 V
VOL
0.5 V
tPZL
3 V
tPLZ
1.5 V
2.3 V
1.5 V
Output
Input
0 V
3 V
(see Note C)
0 V or 3 V
S1
Input
Generator
(see Note A)
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, duty cycle = 50%, tr ≤ 5 ns,
tf ≤ 5 ns, ZO = 50 Ω.
B. CL includes probe and stray capacitance
C. To test the active-low enable G, ground G and apply an inverted waveform to G..
Figure 5. tPZL and tPLZ Test Circuit and Waveforms
SLLS163E − J ULY 1993 − REVISED APRIL 2006
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 6
IO − Output Current − A
VO − Output Voltage − V
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
Output Disabled
TA = 25°C
40
30
20
10
0
−10
−20
−30
−40
20151050−5−10−15−20
−50 25
50
−25
ÁÁ
ÁÁ
ÁÁ
IO
VCC = 5 V
VCC = 0 V
µ
Figure 7
IOL − Low-Level Output Current − mA
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
− Low-Level Output Voltage − V
OL
V
3.5
3
2.5
2
1.5
1
0.5
80604020
0
4
0100
VCC = 5 V
TA = 25°C
4.5
5
12
0
−20
Figure 8
3
2.5
2
1.5
1
0.5
4020
0−20−40
060
TA − Free-Air Temperature − °C
− Differential Output Voltage − V
−60
DIFFERENTIAL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
ÁÁ
ÁÁ
VOD
80 100
RL = 54 Ω
VCC = 5 V
Figure 9
IOH − High-Level Output Current − mA
− High-Level Output Voltage − V
4.5
4
3.5
3
2.5
2
1.5
5
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
−40−20 −600
VOH
−80 −100
VCC = 5 V
TA = 25°C
−120
20
SLLS163E − JULY 1993 − REVISED APRIL 2006
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 10
IO − Output Current − mA
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3
2.5
2
1.5
1
0.5
90807060
5040302010
0
− Differential Output Voltage − V
0
OD
V
100
VCC = 5 V
TA = 25°C
Figure 11
tpd(DO)
TA − Free-Air Temperature − °C
PROPAGATION DELAY TIME,
DIFFERENTIAL OUTPUT
vs
FREE-AIR TEMPERATURE
11
10
9
8
7
6
5
1008060
40200−20−40
4
12
Propagation Delay Time, Differential Output − ns
−60
13
14 RL = 54 Ω
CL = 50 pF
VCC = 5 V
−
THERMAL CHARACTERISTICS − DW PACKAGE
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Junction−to−ambient thermal reisistance, θJA†
Low-K board, no air flow 96
Junction−to−ambient thermal reisistance, θJA
†
High-K board, no air flow 62.9
°C/W
Junction−to−board thermal reisistance, θJB High-K board, no air flow 39.6 °C/W
Junction−to−case thermal reisistance, θJC 29.1
Average power dissipation, P(AVG)
All four channels maximum loading,
maximum signaling rate, RL = 54 Ω, input to
D is 10 Mbps 50% duty cycle square wave,
VCC = 5.25 V, TJ = 130 °C.
1100 mW
Ambient free−air temperature, TA
JEDEC high-K board model −40 85
Ambient free−air temperature, TAJEDEC high-K board model −40 64 °C
Thermal shutdown junction temperature, TSD 165
C
†See TI application note literature number SZZA003, Package Thermal Characterization Methodologies, for an explanation of this parameter.
SLLS163E − J ULY 1993 − REVISED APRIL 2006
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THERMAL CHARACTERISTICS OF IC PACKAGES
ΘJA (Junction-to-Ambient Thermal Resistance) i s defined as the dif ference in junction temperature to ambient temperature
divided by the operating power
ΘJA is NOT a constant and is a strong function of
Dthe PCB design (50% variation)
Daltitude (20% variation)
Ddevice power (5% variation)
ΘJA can be used to compare the thermal performance of packages if the specific test conditions are defined and used.
Standardized testing includes specification of PCB construction, test chamber volume, sensor locations, and the thermal
characteristics of holding fixtures. ΘJA is often misused when it is used to calculate junction temperatures for other
installations.
TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition thermal
performance and consists of a single trace layer 25 mm long and 2-oz thick copper. The high-k board gives best case in−use
condition and consists of two 1-oz buried power planes with a single trace layer 25 mm long with 2-oz thick copper. A 4%
to 50% difference in ΘJA can be measured between these two test cards
ΘJC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by the
operating power. It is measured by putting the mounted package up against a copper block cold plate to force heat to flow
from die, through the mold compound into the copper block.
ΘJC is a useful thermal characteristic when a heatsink is applied to package. It is NOT a useful characteristic to predict
junction temperature as it provides pessimistic numbers if the case temperature is measured in a non-standard system and
junction temperatures are backed out. It can be used with ΘJB in 1-dimensional thermal simulation of a package system.
ΘJB (Junction-to-Board Thermal Resistance) is defined to be the difference in the junction temperature and the PCB
temperature at the center of the package (closest to the die) when the PCB is clamped in a cold−plate structure. ΘJB is only
defined for the high-k test card.
ΘJB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal resistance
(especially for BGA’s with thermal balls) and can be used for simple 1-dimensional network analysis of package system
(see Figure 12).
Surface Node
qJC Calculated/Measured
Junction
qJB Calculated/Measured
PC Board
qCA Calculated
Ambient Node
Figure 12. Thermal Resistance
PACKAGE OPTION ADDENDUM
www.ti.com 20-Jul-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN65LBC172DW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC172DWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC172N ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPD N / A for Pkg Type
SN65LBC172NE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPD N / A for Pkg Type
SN75LBC172DW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC172DWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC172DWR ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC172DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC172N ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPD N / A for Pkg Type
SN75LBC172NE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPD N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 20-Jul-2011
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN75LBC172 :
•Military: SN55LBC172
NOTE: Qualified Version Definitions:
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN75LBC172DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN75LBC172DWR SOIC DW 20 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
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