SLLS163E - JULY 1993 - REVISED APRIL 2006 D Meets or Exceeds EIA Standard RS-485 D Designed for High-Speed Multipoint D D D D D N PACKAGE (TOP VIEW) Transmission on Long Bus Lines in Noisy Environments Support Data Rates up to and Exceeding Ten Million Transfers Per Second Common-Mode Output Voltage Range of -7 V to 12 V Positive- and Negative-Current Limiting Low Power Consumption . . . 1.5 mA Max (Output Disabled) Functionally Interchangeable With SN75172 description The SN65LBC172 and SN75LBC172 are monolithic quadruple differential line drivers with 3-state outputs. Both devices are designed to meet the requirements of EIA Standard RS-485. These devices are optimized for balanced multipoint bus transmission at data rates up to and exceeding 10 million bits per second. Each driver features wide positive and negative commonmode output voltage ranges, current limiting, and thermal-shutdown circuitry making it suitable for party-line applications in noisy environments. Both devices are designed using LinBiCMOS, facilitating ultra-low power consumption and inherent robustness. Both the SN65LBC172 and SN75LBC172 provide positive- and negative-current limiting and thermal shutdown for protection from line fault conditions on the transmission bus line. These devices offer optimum performance when used with the SN75LBC173 or SN75LBC175 quadruple line receivers. The SN65LBC172 and SN75LBC172 are available in the 16-pin DIP package (N) and the 20-pin wide-body smalloutline inline-circuit (SOIC) package (DW). 1A 1Y 1Z G 2Z 2Y 2A GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 4A 4Y 4Z G 3Z 3Y 3A DW PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 1A 1Y NC 1Z G 2Z NC 2Y 2A GND 20 19 18 17 16 15 14 13 12 11 VCC 4A 4Y NC 4Z G 3Z NC 3Y 3A NC - No internal connection FUNCTION TABLE (each driver) INPUT A ENABLES G G OUTPUTS Y Z H X H L H H X L H L X L H L H X L L H L L H Z Z X H = high level, L = low level, X = irrelevant, Z = high impedance (off) The SN75LBC172 is characterized for operation over the commercial temperature range of 0C to 70C. The SN65LBC172 is characterized over the industrial temperature range of - 40C to 85C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinBiCMOS is a trademark of Texas Instruments Incorporated. Copyright 2001-2006, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SLLS163E - JULY 1993 - REVISED APRIL 2006 logic symbol G G 1A 2A 3A 4A 4 12 logic diagram (positive logic) G 1 G EN 2 1 3 6 7 5 10 9 11 14 15 13 1A 1Y 4 12 2 1 3 1Z 2Y 2A 2Z 6 7 5 3Y 3Z 3A 4Y 10 9 11 4Z This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the N package. 4A 14 15 13 1Y 1Z 2Y 2Z 3Y 3Z 4Y 4Z schematic diagrams of inputs and outputs ALL INPUTS Y OR Z OUTPUT VCC VCC 50 A 200 Output Input Driver 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLLS163E - JULY 1993 - REVISED APRIL 2006 absolute maximum ratings Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10 V to 15 V Voltage range at A, G, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC + 0.5 V Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The maximum operating junction temperature is internally limited. Use the dissipation rating table to operate below this temperature. NOTE 1: All voltage values are with respect to GND. recommended operating conditions Supply voltage, VCC MIN NOM MAX UNIT 4.75 5 5.25 V High-level input voltage, VIH 2 V Low-level input voltage, VIL 0.8 V 12 Voltage at any bus terminal (separately or common mode), VO Y or Z High-level output current, IOH Y or Z -60 mA Low-level output current, IOL Y or Z 60 mA -7 Continuous total power dissipation V See Dissipation Rating Table Junction temperature, TJ 140 Operating free-air temperature, TA SN65LBC172 -40 85 SN75LBC172 0 70 C C DISSIPATION RATING TABLE PACKAGE THERMAL MODEL TA < 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 70C POWER RATING TA = 85C POWER RATING Low K High K 1094 mW 10.4 mW/C 625 mW 469 mW DW 1669 mW 15.9 mW/C 954 mW 715 mW 1150 mW 9.2 mW/C 736 mW 598 mW N In accordance with the low effective thermal conductivity metric definitions of EIA/JESD 51-3. In accordance with the high effective thermal conductivity metric definitions of EIA/JESD 51-7. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SLLS163E - JULY 1993 - REVISED APRIL 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VIK TEST CONDITIONS Input clamp voltage MIN TYP II = - 18 mA |VOD| Differential output voltage |VOD| Change in magnitude of common-mode output voltage VOC Common-mode output voltage |VOC| Change in magnitude of common-mode output voltage IO IOZ Output current with power off IIH IIL High-level input current IOS Short-circuit output current ICC Supply current (all drivers) Low-level input current UNIT -1.5 V RL = 54 , See Figure 1 SN65LBC172 1.1 1.8 5 SN75LBC172 1.5 1.8 5 RL = 60 , See Figure 2 SN65LBC172 1.1 1.7 5 SN75LBC172 1.5 1.7 V 5 0.2 V 3 -1 V 0.2 V VCC = 0, VO = - 7 V to 12 V VO = - 7 V to 12 V 100 A 100 A VI = 2.4 V VI = 0.4 V -100 A -100 A VO = - 7 V to 12 V Outputs enabled No load Outputs disabled 250 mA RL = 54 , High-impedance-state output current MAX See Figure 1 7 1.5 mA All typical values are at VCC = 5 V and TA = 25C. The minimum VOD specification does not fully comply with EIA-485 at operating temperatures below 0C. The lower output signal should be used to determine the maximum signal-transmission distance. |VOD| and |VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input changes from a high level to a low level. switching characteristics, VCC = 5 V, TA = 25C PARAMETER TEST CONDITIONS MIN TYP MAX 2 11 20 10 15 25 UNIT td(OD) tt(OD) Differential output delay time Differential output transition time RL = 54 , See Figure 3 tPZH tPZL Output enable time to high level RL = 110 , See Figure 4 20 30 ns Output enable time to low level RL = 110 , See Figure 5 21 30 ns tPHZ tPLZ Output disable time from high level RL = 110 , See Figure 4 48 70 ns Output disable time from low level RL = 110 , See Figure 5 21 30 ns 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 ns SLLS163E - JULY 1993 - REVISED APRIL 2006 PARAMETER MEASUREMENT INFORMATION RL 2 VOD2 RL 2 VOC Figure 1. Differential and Common-Mode Output Voltages Vtest R1 = 375 Y 0 V or 3 V A RL = 60 VOD Z G at 5 V or G at 0 V R2 = 375 Vtest -7 V < Vtest < 12 V NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, duty cycle = 50%, tr 5 ns, tf 5 ns, ZO = 50 . B. CL includes probe and stray capacitance. Figure 2. Driver VOD Test Circuit 3V Input Input Generator (see Note A) RL = 54 CL = 50 pF (see Note B) 50 1.5 V 1.5 V 0V Output td(OD) Output td(OD) 50% 90% 2.5 V 50% 10% 3V tt(OD) - 2.5 V tt(OD) VOLTAGE WAVEFORMS TEST CIRCUIT NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, duty cycle = 50%, tr 5 ns, tf 5 ns, ZO = 50 . B. CL includes probe and stray capacitance. Figure 3. Driver Differential-Output Test Circuit and Delay and Transition-Time Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SLLS163E - JULY 1993 - REVISED APRIL 2006 PARAMETER MEASUREMENT INFORMATION 3V Input 1.5 V S1 1.5 V Output 0 V or 3 V 0V Input Generator (see Note A) 0.5 V CL = 50 pF (see Note B) 50 tPZH RL = 110 VOH Output 2.3 V Voff 0 V tPHZ TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, duty cycle = 50%, tr 5 ns, tf 5 ns, ZO = 50 . B. CL includes probe and stray capacitance. Figure 4. tPZH and tPHZ Test Circuit and Voltage Waveforms 5V RL = 110 S1 Output 3V Input 1.5 V 1.5 V 0V 0 V or 3 V Generator (see Note A) 50 tPZL CL = 50 pF (see Note B) Input tPLZ 2.3 V Output 5V 0.5 V VOL 3V (see Note C) TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, duty cycle = 50%, tr 5 ns, tf 5 ns, ZO = 50 . B. CL includes probe and stray capacitance C. To test the active-low enable G, ground G and apply an inverted waveform to G.. Figure 5. tPZL and tPLZ Test Circuit and Waveforms 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLLS163E - JULY 1993 - REVISED APRIL 2006 TYPICAL CHARACTERISTICS OUTPUT CURRENT vs OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 50 5 Output Disabled TA = 25C 4.5 VOL - Low-Level Output Voltage - V 40 IIO O - Output Current - A 30 20 10 0 AA AA AA -10 VCC = 0 V -20 -30 VCC = 5 V -40 VCC = 5 V TA = 25C 4 3.5 3 2.5 2 1.5 1 0.5 -50 -25 -20 -15 -10 -5 0 5 10 15 20 0 -20 25 0 20 40 60 80 100 IOL - Low-Level Output Current - mA VO - Output Voltage - V Figure 6 Figure 7 DIFFERENTIAL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 5 RL = 54 VCC = 5 V VOH - High-Level Output Voltage - V VOD - Differential Output Voltage - V 3 2.5 2 1.5 1 AA AA 0.5 0 -60 120 VCC = 5 V TA = 25C 4.5 4 3.5 3 2.5 2 1.5 -40 -20 0 20 40 60 80 100 TA - Free-Air Temperature - C 20 0 -20 -40 -60 -80 -100 -120 IOH - High-Level Output Current - mA Figure 8 Figure 9 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SLLS163E - JULY 1993 - REVISED APRIL 2006 TYPICAL CHARACTERISTICS PROPAGATION DELAY TIME, DIFFERENTIAL OUTPUT vs FREE-AIR TEMPERATURE V OD - Differential Output Voltage - V 3 VCC = 5 V TA = 25C 2.5 2 1.5 1 0.5 0 0 10 20 30 40 50 60 70 80 90 100 IO - Output Current - mA t pd(DO)- Propagation Delay Time, Differential Output - ns DIFFERENTIAL OUTPUT VOLTAGE vs OUTPUT CURRENT 14 RL = 54 CL = 50 pF VCC = 5 V 13 12 11 10 9 8 7 6 5 4 -60 -40 -20 0 20 40 60 80 100 TA - Free-Air Temperature - C Figure 11 Figure 10 THERMAL CHARACTERISTICS - DW PACKAGE TEST CONDITIONS PARAMETER Junction-to-ambient thermal reisistance, JA Junction-to-board thermal reisistance, JB MIN 96 High-K board, no air flow 62.9 High-K board, no air flow 39.6 Junction-to-case thermal reisistance, JC Average power dissipation, P(AVG) Ambient free-air temperature, TA TYP Low-K board, no air flow MAX UNIT C/W 29.1 All four channels maximum loading, maximum signaling rate, RL = 54 , input to D is 10 Mbps 50% duty cycle square wave, VCC = 5.25 V, TJ = 130 C. 1100 JEDEC high-K board model -40 85 JEDEC high-K board model -40 64 mW C C Thermal shutdown junction temperature, TSD 165 See TI application note literature number SZZA003, Package Thermal Characterization Methodologies, for an explanation of this parameter. 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLLS163E - JULY 1993 - REVISED APRIL 2006 THERMAL CHARACTERISTICS OF IC PACKAGES JA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient temperature divided by the operating power JA is NOT a constant and is a strong function of D D D the PCB design (50% variation) altitude (20% variation) device power (5% variation) JA can be used to compare the thermal performance of packages if the specific test conditions are defined and used. Standardized testing includes specification of PCB construction, test chamber volume, sensor locations, and the thermal characteristics of holding fixtures. JA is often misused when it is used to calculate junction temperatures for other installations. TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition thermal performance and consists of a single trace layer 25 mm long and 2-oz thick copper. The high-k board gives best case in-use condition and consists of two 1-oz buried power planes with a single trace layer 25 mm long with 2-oz thick copper. A 4% to 50% difference in JA can be measured between these two test cards JC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by the operating power. It is measured by putting the mounted package up against a copper block cold plate to force heat to flow from die, through the mold compound into the copper block. JC is a useful thermal characteristic when a heatsink is applied to package. It is NOT a useful characteristic to predict junction temperature as it provides pessimistic numbers if the case temperature is measured in a non-standard system and junction temperatures are backed out. It can be used with JB in 1-dimensional thermal simulation of a package system. JB (Junction-to-Board Thermal Resistance) is defined to be the difference in the junction temperature and the PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold-plate structure. JB is only defined for the high-k test card. JB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal resistance (especially for BGA's with thermal balls) and can be used for simple 1-dimensional network analysis of package system (see Figure 12). Ambient Node qCA Calculated Surface Node qJC Calculated/Measured Junction qJB Calculated/Measured PC Board Figure 12. Thermal Resistance POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 PACKAGE OPTION ADDENDUM www.ti.com 20-Jul-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) SN65LBC172DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC172DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC172N ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPD N / A for Pkg Type SN65LBC172NE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPD N / A for Pkg Type SN75LBC172DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC172DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC172DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC172DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC172N ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPD N / A for Pkg Type SN75LBC172NE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPD N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 20-Jul-2011 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN75LBC172 : * Military: SN55LBC172 NOTE: Qualified Version Definitions: * Military - QML certified for Military and Defense Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN75LBC172DWR Package Package Pins Type Drawing SOIC DW 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.8 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 2.7 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75LBC172DWR SOIC DW 20 2000 367.0 367.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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