EVAL1201/AA - STMicroelectronics - Datasheet.Directory

1/20

■0.5Msps to 50Msps sampling frequency

■40mW @5Msps,150mW @ 50Msps

■2.5V supply voltage with 2.5V/3.3V compati-

bility fordigital I/O

■Input range: 2Vpp differential

■SFDR up to 77dB @ 50Msps, Fin=15MHz

■ENOB up to10.5 bits @ 50Msps, Fin=15MHz

■Built-in reference voltage with external bias

capability

■Pinout compatibility with TSA0801, TSA1001

and TSA1002

DESCRIPTION

The TSA1201 is a 12-bit, 50MHz maximum

sampling frequency Analog to Digital converter

using a CMOS technology combining high

performances and very low power consumption.

The TSA1201 is based on apipeline structure and

digital error correction to provide excellent static

linearity and achieve 10.5 effective bits at

Fs=50Msps, and Fin=15MHz, with a global power

consumption of 150mW.

The TSA1201 features adaptative behaviour to

the application. Its architecture allows to sample

from 0.5Msps up to 50Msps, witha programmable

power consumption which makes the application

board even more optimized.

It integrates a proprietary track-and-hold structure

to ensure an high analog bandwidth of 1GHz and

enable IF-sampling.

Several features are available on the device. A

voltage reference is integrated in the circuit.

Differential or single-ended analog inputs can be

applied. The output data can be coded into two

differential formats. A Data Ready signal is raised

as the data is valid on the outputand can be used

for synchronization purposes.

The TSA1201 is available in extended (-40°Cto

+85°C) temperature range, in small 48 pins TQFP

package.

APPLICATIONS

■High speed data acquisition

■Medical imaging and ultrasound

■Portable instrumentation

■High speed DSP interface

■Digital communication - IF sampling

ORDER CODE

PIN CONNECTIONS (top view)

PACKAGE

Part Number Temperature

Range Package Conditioning Marking

TSA1201IF -40°C to +85°C TQFP48 Tray SA1201I

TSA1201IFT -40°C to +85°C TQFP48 Tape & Reel SA1201I

EVAL1201/AA Evaluation board

7 x 7 mm TQFP48

VREFM

VREFP

VINB

AGND

index

corner

13 14 15 16 17 18 19 20 21 22

23 24

48 44 43 42 41 40 39 38 37

46 45

AGND

VIN

D10

AVCC

AGND

IPOL

INCM

D0 (LSB)

AVCC

SRC

OEB

AGND

AVCC

DFSB

VCCBI

GNDBE

VCCBE

GNDBE

GNDBI

DGND

DVCC

CLK

DGND

VCCBE

DGND

DVCC

D11 (MSB)

TSA1201

12-BIT, 50MSPS, 150mW A/D CONVERTER

March 2001

TSA1201

2/20

ABSOLUTE MAXIMUM RATINGS

OPERATING CONDITIONS

BLOCK DIAGRAM

Symbol Parameter Values Unit

AVCC Analog Supply voltage 1) 0 to 3.3 V

DVCC Digital Supply voltage 1) 0 to 3.3 V

VCCBI Digital buffer Supply voltage 1) 0 to 3.3 V

VCCBE Digital buffer Supply voltage 1) 0 to 3.6 V

Tstg Storage temperature +150 °C

ESD Electrical Static Discharge

- HBM

- CDM-JEDEC Standard 2

1.5 KV

1. All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages

must never exceed -0.3V or VCC+0V

Symbol Parameter Test conditions Min Typ Max Unit

AVCC Analog Supply voltage 2.25 2.5 2.7 V

DVCC Digital Supply voltage 2.25 2.5 2.7 V

VCCBI Internal (quiet) buffer Supply voltage 2.25 2.5 2.7 V

VCCBE External (noisy) buffer Supply voltage 2.25 2.5 3.5 V

VREFP Forced top voltage reference 0.8 - AVCC V

VREFM Bottom internal reference voltage input 0 1 V

stage stage stage

12n

Reference

Timing

circuit

Sequencer-phaseshifting

Digital data correction

Buffers

IPOL

VREFM

VREFP

CLK

+2.5V

VIN

VINB

DFSB

OEB

D11

INCM

GND

GNDA

+2.5V/3.3V

SRC

TSA1201

3/20

PIN CONNECTIONS (top view)

PIN DESCRIPTION

VREFM

VREFP

VINB

AGND

index

corner

13 14 15 16 17 18 19 20 21 22

23 24

48 44 43 42 41 40 39 38 37

46 45

AGND

VIN

D10

AVCC

AGND

IPOL

INCM

D0 (LSB)

AVCC

SRC

OEB

AGND

AVCC

DFSB

VCCBI

GNDBE

VCCBE

GNDBE

GNDBI

DGND

DVCC

CLK

DGND

VCCBE

DGND

DVCC

D11 (MSB)

TSA1201

Pin No Name Description Observation Pin No Name Description Observation

1 IPOL Analog bias currentinput 25 D10 Digital output CMOS output (2.5V/3.3V)

2 VREFP Top voltage reference 1V 26 D9 Digital output CMOS output (2.5V/3.3V)

3 VREFM Bottom voltage reference 0V 27 D8 Digital output CMOS output (2.5V/3.3V)

4 AGND Analog ground 0V 28 D7 Digitaloutput CMOS output (2.5V/3.3V)

5 VIN Analog input 1Vpp 29 D6 Digital output CMOS output (2.5V/3.3V)

6 AGND Analog ground 0V 30 D5 Digitaloutput CMOS output (2.5V/3.3V)

7 VINB Inverted analog input 1Vpp 31 D4 Digital output CMOS output (2.5V/3.3V)

8 AGND Analog ground 0V 32 D3 Digitaloutput CMOS output (2.5V/3.3V)

9 INCM Input common mode 0.5V 33 D2 Digital output CMOS output (2.5V/3.3V)

10 AGND Analog ground 0V 34 D1 Digital output CMOS output (2.5V/3.3V)

11 AVCC Analog power supply 2.5V 35 D0(LSB) Least Significant Bit output CMOS output (2.5V/3.3V)

12 AVCC Analog power supply 2.5V 36 NC Non connected

13 DVCC Digital power supply 2.5V 37 NC Non connected

14 DVCC Digital power supply 2.5V 38 DR Data Ready output CMOS output (2.5V/3.3V)

15 DGND Digital groun d 0V 39 VCCBE Digital Buffer power supply 2.5V/3.3V

16 CLK Clock input 2.5V compatible CMOS input 40 GNDBE Digital Buffer ground 0V

17 DGND Digital groun d 0V 41 VCCBI Digital Buffer power supply 2.5V

18 NC Non connected 42 NC Non connected

19 DGND Digital groun d 0V 43 SRC Slew rate control input 2.5V/3.3V CMOS input

20 GNDBI Digital buffer ground 0V 44 OEB OutputEnable input 2.5V/3.3V CMOS input

21 GNDBE Digital buffer ground 0V 45 DFSB Data Format Select input 2.5V/3.3V CMOS input

22 VCCBE Digital buffer power supply 2.5V/3.3V 46 AVCC Analog power supply 2.5V

23 OR Out Of Range output CMOS output (2.5V/3.3V) 47 AVCC Analog powersupply 2.5V

24 D11(MSB) Most Significant Bit output CMOS output (2.5V/3.3V) 48 AGND Analog ground 0V

TSA1201

4/20

ELECTRICAL CHARACTERISTICS

AVCC = DVCC= VCCBE = VCCBI = 2.5V,Fs= 50Msps,Fin=2MHz, Vin@ -1dBFS, VREFM=0V

Tamb = 25°C (unless otherwise specified)

TIMING CHARACTERISTICS

TIMING DIAGRAM

Symbol Parameter Test conditions Min Typ Max Unit

FS Sampling Frequency 0.5 50 MHz

DC Clock Duty Cycle 45 50 55 %

TC1 Clock pulse width (high) 9 10 ns

TC2 Clock pulse width (low) 9 10 ns

Tod Data Output Delay (Fall of Clock

to Data Valid) 6pF load capacitance 8ns

Tpd Data Pipeline delay 5.5 cycles

Ton Falling edge of OEB to digital

output valid data 1ns

Toff Rising edge of OEB to digital

output tri-state 1ns

N-3 N-2 N-1

N+4

N+5

N+3

N+1

N+2

N+6

N-3 N-1N-4N-5N-6N-7N-8N-9

CLK

OEB

Tod Ton

Toff

Tpd + Tod

HZ state

DATA

OUT

TSA1201

5/20

CONDITIONS

AVCC = DVCC = VCCBE = VCCBI = 2.5V,Fs= 50Msps,Fin=2MHz, Vin@ -1dBFS, VREFM=0V

Tamb = 25°C (unless otherwise specified)

ANALOG INPUTS

REFERENCE VOLTAGE

Symbol Parameter Test conditions Min Typ Max Unit

VIN-VINB Full scale reference voltage 2.0 Vpp

Cin Input capacitance 7.0 pF

Rin Differential input resistance 5 MΩ

BW Analog Input Bandwitdh Vin@Full Scale, Fs=50Msps 1000 MHz

ERB Effective Resolution Bandwidth1) 90 MHz

1. See parameters definition for more information.

Symbol Parameter Test conditions Min Typ Max Unit

VREFP Top internal reference voltage 0.79 1.0 1.16 V

Tmin= -40°C to Tmax= 85°C1) 0.79 1.16 V

Vpol Analog bias voltage 1.08 1.15 1.22 V

Tmin= -40°C to Tmax= 85°C1) 1.07 1.23 V

VINCM Input common mode voltage 0.40 0.55 0.65 V

Tmin= -40°C to Tmax= 85°C1) 0.4 0.65 V

1. Not fully tested over the temperature range. Guaranted by sampling.

TSA1201

6/20

CONDITIONS

AVCC = DVCC = VCCBE = VCCBI = 2.5V,Fs= 50Msps,Fin=2MHz, Vin@ -1dBFS, VREFP=1V,

VREFM=0V

Tamb = 25°C (unless otherwise specified)

POWER CONSUMPTION

DIGITALINPUTS AND OUTPUTS

Symbol Parameter Test conditions Min Typ Max Unit

Pd Power consumption in normal

operation mode

1) 150 158 mW

Tmin= -40°C to Tmax= 85°C2) 165 mW

ICCA Analog Supply current 1) 46 51 mA

Tmin= -40°C to Tmax= 85°C2) 55 mA

ICCD Digital Supply Current 1) 1.9 2.2 mA

Tmin= -40°C to Tmax= 85°C2) 2.2 mA

ICCBI Digital Buffer Supply Current 1) 0.3 0.4 mA

Tmin= -40°C to Tmax= 85°C2) 0.4 mA

ICCBE Digital Buffer Supply Current 1) 9.8 10.8 mA

Tmin= -40°C to Tmax= 85°C2) 10.8 mA

ICCBEZ Digital Buffer Supply Current in

High Impedance Mode 45mA

Rthja Junction-ambient thermal resis-

tance (TQFP48) 80 °C/W

1. Equivalent load: Rload= 470Ωand Cload= 6pF

2. Not fully tested over the temperature range. Guaranted by sampling.

Symbol Parameter Test conditions Min Typ Max Unit

Clock input

VIL Logic ”0” voltage 0 0.8 V

VIH Logic ”1” voltage 2.0 2.5 V

Digital inputs

VIL Logic ”0” voltage 0 0.25 x

VCCBE V

VIH Logic ”1” voltage 0.75 x

VCCBE VCCBE V

Digital Outputs

VOL Logic ”0” voltage Iol=10µA00.1 x

VCCBE V

VOH Logic ”1” voltage Ioh=10µA 0.9 x

VCCBE VCCBE V

IOZ High Impedance leakage current OEB set to VIH -2.5 2.5 µA

CLOutput Load Capacitance 15 pF

TSA1201

7/20

CONDITIONS

AVCC = DVCC = VCCBE = VCCBI = 2.5V,Fs= 50Msps, Vin@ -1dBFS, VREFP=1V, VREFM=0V

Tamb = 25°C (unless otherwise specified)

ACCURACY

DYNAMIC CHARACTERISTICS

Symbol Parameter Test conditions Min Typ Max Unit

OE Offset Error Fin= 2MHz, VIN@+1dBFS 2.45 mV

DNL Differential Non Linearity Fin= 2MHz, VIN@+1dBFS ±0.6 LSB

INL Integral Non Linearity Fin= 2MHz, VIN@+1dBFS ±1.7 LSB

-Monotonicity and no missing

codes Guaranted

Symbol Parameter Test conditions Min Typ Max Unit

SFDR Spurious Free Dynamic Range Fin= 15MHz1) -77.2 -68 dBc

Fin= 15MHz2) -67 dBc

SNR Signal to Noise Ratio Fin= 15MHz1) 61.6 64.9 dB

Fin= 15MHz2) 60.7 dB

THD Total Harmonics Distorsion Fin= 15MHz1) -74.3 -68 dB

Fin= 15MHz2) -64 dB

SINAD Signal to Noise and Distorsion-

Ratio Fin= 15MHz1) 61 64.4 dB

Fin= 15MHz2) 60 dB

ENOB Effective Number of Bits Fin= 15MHz1) 10 10.5 bits

Fin= 15MHz2) 9.9 bits

1. Equivalent load: Rload= 470Ωand Cload= 6pF

2. Tmin= -40°C to Tmax= 85°C. Not fully tested over the temperature range. Guaranted by sampling.

TSA1201

8/20

DEFINITIONS OF SPECIFIED PARAMETERS

STATIC PARAMETERS

Static measurements are performed through

method of histograms on a 2MHz input signal,

sampled at 50Msps, which is high enough to fully

characterize the test frequency response. The

input level is +1dBFS to saturate the signal.

Differential Non Linearity (DNL)

The average deviation of any output code width

from the ideal code width of 1LSB.

Integral Non linearity (INL)

An ideal converter presents a transfer function as

being the straight line fromthe starting code to the

ending code. The INL is the deviation for each

transition from this ideal curve.

DYNAMIC PARAMETERS

Dynamic measurements are performed by

spectral analysis, applied to an input sinewave of

various frequencies and sampled at 50Msps.

Spurious Free Dynamic Range (SFDR)

The ratio between the power of the worst spurious

signal (not always an harmonic) and the amplitude

of fundamental tone (signal power) over the full

Nyquist band. It is expressed in dBc.

Total Harmonic Distortion (THD)

The ratio of the rms sum of the first five harmonic

distortion components to the rms value of the

fundamental line. It is expressed in dB.

Signal to Noise Ratio (SNR)

The ratio of the rms value of the fundamental

component to the rms sum of all other spectral

components in the Nyquist band (fs/2) excluding

DC, fundamental and the first five harmonics.

SNR is reported in dB.

Signal to Noise and Distorsion Ratio (SINAD)

Similar ratioas for SNR but including the harmonic

distortion components in the noise figure (not DC

signal). It is expressed in dB.

From the SINAD, the Effective Number of Bits

(ENOB) can easily be deduced using the formula:

SINAD= 6.02 ×ENOB + 1.76 dB.

When the applied signal is notFull Scale (FS), but

has an A0amplitude, the SINAD expression

becomes:

SINAD= 6.02×ENOB+ 1.76 dB + 20log (2A0/FS)

The ENOB is expressed in bits.

Analog Input Bandwidth

The maximum analog input frequency at which the

spectral response of a full power signal is reduced

by 3dB. Higher values can be achieved with

smaller input levels.

Effective Resolution Bandwidth (ERB)

The band of input signal frequencies that the ADC

is intended to convert without loosing linearity i.e.

the maximum analog input frequency at which the

SINAD is decreased by 3dB or the ENOB by 1/2

bit.

Pipeline delay

Delay between the initial sample of the analog

input and the availability of the corresponding

digital data output,on the output bus. Also called

data latency. It is expressed as a number of clock

cycles.

TSA1201

9/20

Static parameter: Integral Non Linearity

Fs=50MSPS; Fin=1MHz; Icca=45mA; N=131072pts

Static parameter: Differential Non Linearity

Fs=50MSPS; Fin=1MHz; Icca=45mA; N=131072pts

Linearity vs. VCCA

Fs=50MSPS; Icca=45mA; Fin=10MHz Distortion vs. VCCA

Fs=50MSPS; Icca=45mA; Fin=10MHz

-3

-2

-1

0 500 1000 1500 2000 2500 3000 3500 4000

Output Code

INL (LSBs)

-2

-1.5

-1

-0.5

0.5

1.5

0 500 1000 1500 2000 2500 3000 3500 4000

Output Code

DNL (LSBs)

62.5

63.5

64.5

65.5

66.5

2.25 2.35 2.45 2.55 2.65

VCCA(V)

Dynamic parameters

(dB)

10.2

10.4

10.6

10.8

11.2

11.4

11.6

11.8

ENOB (bits)

SINAD

ENOB

SNR

-82

-81

-80

-79

-78

-77

-76

-75

-74

-73

-72

2.25 2.35 2.45 2.55 2.65

VCCA (V)

Dynamic Parameters (dB)

SFDR

THD

TSA1201

10/20

Linearity vs. VCCD

Fs=50MSPS; Icca=45mA; Fin=10MHz

Linearity vs. VCCBE

Fs=50MSPS; Icca=45mA; Fin=10MHz

Linearity vs. Fs

Icca=45mA; Fin=10MHz

Distortion vs. VCCD

Fs=50MSPS; Icca=45mA; Fin=10MHz

Distortion vs. VCCBE

Fs=50MSPS; Icca=45mA; Fin=10MHz

Distortion vs. Fs

Icca=45mA; Fin=10MHz

61.5

62.5

63.5

64.5

65.5

2.25 2.35 2.45 2.55 2.65

VCCD(V)

Dynamic parameters

(dB)

10.2

10.4

10.6

10.8

11.2

11.4

11.6

11.8

ENOB (bits)

SINAD

ENOB

SNR

2.25 2.35 2.45 2.55 2.65

VCCBE(V)

Dynamic parameters

(dB)

10.2

10.4

10.6

10.8

11.2

11.4

11.6

11.8

ENOB (bits)

SINAD

ENOB

SNR

15 25 35 45 55 65 75

Fs (MHz)

Dynamic parameters (dB)

9.5

10.5

11.5

ENOB (bits)

ENOB

SNR

SINAD

-85

-83

-81

-79

-77

-75

-73

-71

2.25 2.35 2.45 2.55 2.65

VCCD(V)

Dynamic parameters (dB)

THD

SFDR

-82

-81

-80

-79

-78

-77

-76

-75

-74

-73

-72

2.25 2.35 2.45 2.55 2.65

VCCBE(V)

Dynamic Parameters (dB)

SFDR

THD

-90

-85

-80

-75

-70

-65

-60

-55

-50

15 25 35 45 55 65 75

Fs (MHz)

Dynamic parameters (dB)

THD

SFDR

TSA1201

11/20

Linearity vs. Fin

Fs=50MHz; Icca=45mA

Linearity vs.Temperature

Fs=49.7MSPS; Icca=45mA; Fin=15MHz

Distortion vs. Fin

Fs=50MHz; Icca=45mA

Distortion vs. Temperature

Fs=49.7MSPS; Icca=45mA; Fin=15MHz

Single-tone 16K FFT at 50Msps

Fin=94.5MHz; Icca=45mA, Vin@-0.5dBFS

020406080

Fin (MHz)

Dynamic parameters (dB)

7.5

8.5

9.5

10.5

11.5

ENOB

SNR

SINAD

-40 10 60 110

Temperature (°C)

Dynamic Parameters (dB)

9.5

10.5

11.5

SINAD

ENOB

SNR

-90

-85

-80

-75

-70

-65

-60

0 20406080

Fin (MHz)

Dynamic parameters (dB)

THD

SFDR

-40 10 60 110

Temperature (°C)

Dynamic Parameters (dB)

SFDR

THD

-140

-20

-40

-60

-80

-100

-120

151050

PowerSpectrum(dB)

Frequency (MHz)

12/20

TSA1201 APPLICATION NOTE

DETAILED INFORMATION

The TSA1201 is a High Speed analog to digital

converter basedon apipeline architecture and the

latest deep submicron CMOS process to achieve

the best performances in terms of linearity and

power consumption.

The pipeline structure consists of 11 internal

conversion stages in which the analog signal is

fed and sequencially converted into digital data.

Each 10 first stages consists of an Analog to

Digital converter, a Digital to Analog converter, a

Sample and Hold and a gain of 2 amplifier. A

1.5-bit conversion resolution is achieved in each

stage. The latest stage simply is a comparator.

Each resulting LSB-MSB couple is then time

shifted to recover from the delay caused by

conversion. Digital data correction completes the

processing by recovering from the redundancy of

the (LSB-MSB) couple for each stage. The

corrected data are outputed through the digital

buffers.

Signal input is sampled on the rising edge of the

clock while digital outputs are delivered on the

falling edge of the clock.

The advantages of such a converter reside in the

combination of pipeline architecture and the most

advanced technologies. The highest dynamic

performances are achieved while consumption

remains at the lowest level.

Some functionalites have been added in order to

simplify as much as possible the application

board. These operational modes are described in

the following table.

The TSA1201 is pin to pin compatible with the

8bits/40Msps TSA0801, the 10bits/25Msps

TSA1001 and the 10bits/50Msps TSA1002. This

ensures a conformity with the product family and

above all, an easy upgrade of the application

OPERATIONAL MODES DESCRIPTION

Data Format Select (DFSB)

When set to low level (VIL), the digital inputDFSB

provides a two’s complement digital output MSB.

This can be of interest when performing some

further signal processing.

When set to high level (VIH), DFSB provides a

standard binary output coding.

Output Enable (OEB)

When set to low level (VIL), all digital outputs

remain active and are in low impedance state.

When set to high level (VIH), all digital outputs

buffers are in high impedance state while the

converter goes onsampling. When OEB is set to a

low level again, the data are then present on the

output with a very short Ton delay.

Therefore, thisallows the chip select of the device.

The timing diagram summarizes this functionality.

Inputs Outputs

Analog input differential level DFSB OEB SRC OR DR Most Significant Bit (MSB)

(VIN-VINB) > RANGE H L X H CLK D11

-RANGE > (VIN-VINB) H L X H CLK D11

RANGE> (VIN-VINB) >-RANGE H L X L CLK D11

(VIN-VINB) > RANGE L L X H CLK D11 Complemented

-RANGE > (VIN-VINB) L L X H CLK D11 Complemented

RANGE> (VIN-VINB) >-RANGE L L X L CLK D11 Complemented

X X H X HZ HZ HZ

X X X H X CLK 25Msps compliant slew rate

X X X L X CLK 50Msps compliant slew rate

TSA1201

13/20

Slew Rate Control (SRC)

When set to high level (VIH), all digital outputs

currents arelimited toa clamp value so that digital

noise power is reduced to its minimum. Rise and

fall times just match 25MHz sampling rate

assuming the load capacitance on each digital

output remains below 10pF.

When set to low level (VIL), the maximum digital

output current increases so that rise and fall times

just match the 50MHz sampling rate assuming the

load capacitance on each digital output remains

below 10pF.

Out of Range (OR)

This function is implemented on the output stage

in order to set up an ”Out of Range” flag whenever

the digital data is over the full scale range.

Typically, there is a detection of all the data being

at ’0’ or all the data beingat ’1’. This ends up with

an output signal OR which is in low level state

(VOL) when the data stay within in the range, or in

high level state (VOH)when the data are out of the

range.

Data Ready (DR)

The Data Ready output is an image of the clock

being synchronized on the output data (D0 to

D11). This is a very helpful signal that simplifes

the synchronization of the measurement

equipment or the controling DSP.

As digital output, DR goes into high impedance

state when OEB is asserted to high level as

described in the timing diagram.

DRIVING THE ANALOG INPUT

Differential inputs

The TSA1201 has been designed to obtain

optimum performances when being differentially

driven. An RF transformer is a good way to

achieve such performances.

Figure 1 describes the schematics. The input

signal is fed to the primary of the transformer,

while the secondary drives both ADC inputs. The

common mode voltage of the ADC (INCM) is

connected to the center-tap of the secondary of

the transformer in order to bias the input signal

around this common voltage, internally set to

0.56V. It determines the DC component of the

analog signal. As being an high impedance input,

it acts as an I/O and can be externally driven to

adjust this DC component. The INCM is

decoupled to maintain a low noise level on this

node. Our evaluation board is mounted with a 1:1

ADT1-1 transformer from Minicircuits. You might

also use a higher impedance ratio (1:2 or 1:4) to

reduce the driving requirement on the analog

signal source.

Each analog input can drive a 1Vpp amplitude

input signal, so the resultant differential amplitude

is 2Vpp.

Figure 1 : Differential input configuration

Single-ended input configuration

Some applications may require a single-ended

input. This is easily achieved with the

configuration reported on Figure 2 for an

AC-coupled input or on Figure 3 and 4 for a

DC-coupled input..

In the case of AC-coupled analog input, it is

recommended to connectthe other analoginput to

the common mode voltage of the circuit (INCM) so

as to properly bias the ADC. The INCM may

remain at the same internal level (0.56V) thus

driving only a 1Vpp input amplitude, or it must be

increased to 1V to drive a 2Vpp input amplitude.

Figure 2 : AC-coupled Single-ended input

In the case of DC-coupled analog input, Figure 3

shows the configuration for a 2Vpp input signal.

The DC component is driven by VREFP which is

connected to INCM and VINB and therefore

imposes its voltage. VREFM being connected to

ground, a dynamic of 2Vpp is achievable.

Figure 4 describes the configuration for a 1Vpp

analog signal. In this case, VREFM is connected

TSA1201

VIN

VINB INCM

50Ω100pF

330pF 470nF10nF

Analog source 1:1

ADT1-1

TSA1201

VIN

VINB INCM

50Ω

100nF

330pF 470nF

10nF

Signal source

TSA1201

14/20

to VINB and INCM. The latest imposes its voltage.

VREFP being internally set to 1V, the dynamic is

then 1Vpp.

Figure 3 : DC-coupled 2Vpp analog input

Figure 4 : DC-coupled 1Vpp analog input

IF-sampling

Software radio has become a common mode for

receiving data through RF receivers. Its main

advantage being to digitally implement what was

originally done with analog functions such as

discriminators, demodulation and filtering.

Originally, bipolar process was mainly used

because they provided high transistor transit

frequency, while pure CMOS technology showed

a lower one. With new CMOS process and circuit

topology, higher frequencies are now achieved.

The TSA1201 has been specifically designed to

meet the requirement of sampling at Intermediate

Frequency. For this purpose, the Track-and-Hold

of the first pipeline stage has been built to ensure

the global linearity of the overall ADC to perform

the right characteristics.

Our proprietary Track-and-Hold has a patented

switch control system to enable the performances

not to be degraded as input signal frequency

increases.

As a result, an analog bandwidth of 1GHz is

achieved.

REFERENCE CONNECTION

Internal reference

In the standard configuration, the ADC is biased

with the internal reference voltage. VREFM pin is

connected to Analog Ground while VREFP is

internally set to a voltage of 1.0V. It is

recommended to decouple the VREFP in order to

minimize low and high frequency noise. Refer to

Figure 5 for the schematics.

Figure 5 : Internal reference setting

External reference

It is possible to use an external reference voltage

instead of the internal one for specificapplications

requiring even better linearity or enhanced

temperature behaviour. In this case, the amplitude

of the external voltage must be at least equal to

the internal one (1.0V). Using the

STMicroelectronics Vref TS821 leads to optimum

performances when configured as shown on

Figure 6.

Figure 6 : External reference setting

This can be very helpful for example for

multichannel application to keep a good matching

over the sampling frequency range.

TSA1201

VIN

VINB INCM

330pF 470nF

10nF

Analog

Analog+DC VREFP

VREFM

TSA1201

VIN

VINB INCM

330pF 470nF

10nF

Analog

Analog+DC

VREFM

TSA1201

VIN

VINB VREFM

1.0V

VREFP 330pF 470nF

10nF

1kΩ

TSA1201

VIN

VINB VREFM

VREFP

external

reference

TS821

VCCA 330pF 470nF

10nF

TSA1201

15/20

Clock input

The quality of your converter isvery dependant on

your clock input accuracy, in terms of aperture

jitter; the use of low jitter crystal controlled

oscillator is recommended.

The duty cycle must be between 45% and 55%.

The clock power supplies must be separated from

the ADC output ones to avoid digital noise

modulation at the output.

It is recommended to always keep the circuit

clocked, even at the lowest specified sampling

frequency of 0.5Msps, before applying the supply

voltages.

Power consumption optimization

The internal architecture of the TSA1201 enables

to optimize the power consumption according to

the sampling frequency of. For this purpose, a

resistor is placed between IPOL and the analog

Ground pins. Therefore, the total dissipation is

adjustable from 0.5Msps up to 50Msps. This

feature is of highest importance when power

saving conditions the application.

The TSA1201 will combine highest performances

and lowest consumption at 50Msps when Rpol is

equal to 12kΩ.

At lower sampling frequency range, this value of

resistor may be adjusted in order to decrease the

analog current without any degradation of

dynamic performances.

As an example, 40mW total power consumption is

achieved at 5 Msps with Rpol equal to 190k

Ω

and

35mW is dissipated at 1Msps with Rpol equal to

350kΩ.

The table below sums up the relevant data.

Figure 7 describes the behaviour of the converter

as sampling frequency increases and shows the

optimum in terms of analog current and

polarization resistor.

Total power consumption optimization

depending on Rpol value

Figure 7 : Optimized power consumption

Fin=1MHz

Layout precautions

To use the ADC circuits inthe best mannerat high

frequencies, some precautions have to be taken

for power supplies:

- First of all, the implementation of 4 separate

proper supplies and ground planes (analog,

digital, internal and external buffer ones) on the

PCB is mandatory for high speed circuit

applications to provide low inductance and low

resistance common return.

The separation of the analog signal from the

digital part is essential to prevent noise from

coupling onto the input signal.

- Power supply bypass capacitors must be placed

as close as possible to the IC pins in order to

improve high frequency bypassing and reduce

harmonic distortion.

- Proper termination of all inputs and outputs must

be incorporated with output termination resistors;

then the amplifier load will be only resistive and

the stability of the amplifier will be improved. All

leads must be wide and as short as possible

especially for the analog input inorder to decrease

parasitic capacitance and inductance.

- To keep the capacitive loading as low as

possible at digital outputs, short lead lengths of

routing are essential to minimize currents when

the output changes. To minimize this output

capacitance, buffers or latches close to the output

pins will relax this constraint.

- Choose component sizes as small as possible

(SMD).

Fs (Msps) 5 35 50

Rpol (kΩ) 190 29 12

Optimized

power (mW) 40 100 150

100

120

140

160

180

200

5 25456585

Fs(MHz)

Rpol(kOhms)

Icca(mA)

RPOL

ICCA

TSA1201

16/20

EVAL1201 evaluation board

The characterization of the board has been made

with a fully ADC devoted test bench as shown on

Figure 8. The analog signal must be filtered to be

very pure.

The dataready signal is the acquisitionclock of the

logic analyzer.

The ADC digital outputs are latched by the octal

buffers 74LCX573.

All characterization measurements have been

made with:

- SFSR=+0.5dB for static parameters.

- SFSR=-0.5dB for dynamic parameters.

Figure 8 : Analog to Digital Converter characterization bench

Sinewave

Generator

Power

SineWave

Generator

ADC

evaluation

board Logic

Analyzer

Pulse

Generator

dataready

data

Vin

HP8644B

HP8133A

TLA704

TSA1201

17/20

Figure 9 : TSA1201 Evaluation board schematic

100pF

330pF

470nF

10nF

330pF

10nF

470nF

330pF

10nF

C10

470nF

C11

330pF

C12

10nF

C13

470nF

C14

330pF

C15

10nF

C16

470nF

Raj1

47K

C17

330pF

C18

10nF

C19

470nF

CLJ/SMB

C24

10µ

OEB

GND

10 LE 11

Q0 19

Q1 18

Q2 17

Q3 16

Q4 15

Q5 14

Q6 13

Q7 12

VCC 20

74LCX573

OEB

GND

10 LE 11

Q0 19

Q1 18

Q2 17

Q3 16

Q4 15

Q5 14

Q6 13

Q7 12

VCC 20

74LCX573

R10

47K

R11

47K

R12

47K

R14

47K R15

47K

C25

330pF

C27

10nF

C28

470nF

C29

10µF

D10

D11

D12

R13

47K

C30

330pF

C31

10nF

C32

470nF

VCC

J17

VDDBUFF3V

J18

VccB1

C34

47µ

C35

47µ

refP

refM

egl commode

es comMode

AVCC

VCCB1

DFSB

J10

OEB

J11

J13

C26

330pF

C39

10nF

C37

470nF

VCCB2

C33

330pF

C40

10nF

C38

470nF

D13

GND

ndB2

ndB1

C41

10µF

+C42

47µF

Ipol

VrefP

VrefM

AGND

Vin

AGND

VINB

AGND

INCM

AGND

AVCC

DVCC

DGN D

CLK

DGN D

GND BUF F

2.5VCCBUFF

D13

D12 25

D11 26

D10 27

D9 28

D8 29

D7 30

D6 31

D5 32

D4 33

D3 34

D2 35

D1 36

D0 37

DR 38

2.5VCCBUFF 39

GNDB UFF 40

2.5VCCBUFF 41

NC 42

NC 43

OEB 44

DFSB 45

AVCC 46

AVCC 47

AGN D 48

8-14bitsADC

TSA1002

R16

47K R17

47K R18

47K R19

47K

DR 1

32PIN

J16

CON2

C20

330pF

C21

10nF

C22

470nF

C23

10µ

J15

DVCC

C36

47µ

T2-AT1-1WT

TSA1201

100pF

330pF

470nF

10nF

330pF

10nF

470nF

330pF

10nF

C10

470nF

C11

330pF

C12

10nF

C13

470nF

C14

330pF

C15

10nF

C16

470nF

Raj1

47K

C17

330pF

C18

10nF

C19

470nF

CLJ/SMB

C24

10µ

OEB

GND

10 LE 11

Q0 19

Q1 18

Q2 17

Q3 16

Q4 15

Q5 14

Q6 13

Q7 12

VCC 20

74LCX573

OEB

GND

10 LE 11

Q0 19

Q1 18

Q2 17

Q3 16

Q4 15

Q5 14

Q6 13

Q7 12

VCC 20

74LCX573

R10

47K

R11

47K

R12

47K

R14

47K R15

47K

C25

330pF

C27

10nF

C28

470nF

C29

10µF

D10

D11

D12

R13

47K

C30

330pF

C31

10nF

C32

470nF

VCC

J17

VDDBUFF3V

J18

VccB1

C34

47µ

C35

47µ

refP

refM

egl commode

es comMode

AVCC

VCCB1

DFSB

J10

OEB

J11

J13

C26

330pF

C39

10nF

C37

470nF

VCCB2

C33

330pF

C40

10nF

C38

470nF

D13

GND

ndB2

ndB1

C41

10µF

+C42

47µF

Ipol

VrefP

VrefM

AGND

Vin

AGND

VINB

AGND

INCM

AGND

AVCC

DVCC

DGN D

CLK

DGN D

GND BUF F

2.5VCCBUFF

D13

D12 25

D11 26

D10 27

D9 28

D8 29

D7 30

D6 31

D5 32

D4 33

D3 34

D2 35

D1 36

D0 37

DR 38

2.5VCCBUFF 39

GNDB UFF 40

2.5VCCBUFF 41

NC 42

NC 43

OEB 44

DFSB 45

AVCC 46

AVCC 47

AGN D 48

8-14bitsADC

TSA1002

R16

47K R17

47K R18

47K R19

47K

DR 1

32PIN

J16

CON2

C20

330pF

C21

10nF

C22

470nF

C23

10µ

J15

DVCC

C36

47µ

T2-AT1-1WT

TSA1201

18/20

Figure 10 : Printed circuit of evaluationboard.

Printed circuit board - List of components

Part Design Footprint Part Design Footprint Part Design Footprint Part Design Footprint

Type ator Type ator Type ator Type ator

10uF C2 4 1210 330pF C33 603 470nF C7 805 AVCC J12 FICHE2MM

10uF C2 3 1210 330pF C20 603 470nF C16 805 CLJ/SMB J4 SMB /H

10uF C4 1 1210 330pF C8 603 470nF C19 805 AGND J19 FICHE2MM

10uF C2 9 1210 330pF C2 603 470nF C3 805 DFSB J9 FICHE2MM

100pF C1 60 3 330pF C5 603 47KΩR12 603 DGND J20 FICHE2MM

10nF C12 60 3 33 0pF C 11 6 03 47KΩR14 603 DVCC J15 FICHE2MM

10nF C3 9 60 3 330pF C30 603 47KΩR11 603 GndB 1 J22 FICHE2MM

10nF C15 60 3 33 0pF C 17 6 03 47KΩR a j1 VR5 GndB 2 J2 1 F ICH E2 MM

10nF C4 0 60 3 33 0pF C 14 6 03 47KΩR10 603 Mes com mo de J8 FICHE2MM

10nF C2 7 60 3 47uF C36 CAP 47KΩR19 603 OEB J10 FICHE2MM

10nF C4 60 3 47uF C34 CAP 47KΩR13 6 03 R e gl c o m mo de J7 F ICH E2 MM

10nF C2 1 60 3 47uF C35 CAP 47KΩR15 603 T2-AT1-1WT T2 ADT

10nF C3 1 60 3 47uF C42 CAP 47KΩR16 603 T2-AT1-1WT T1 ADT

10nF C6 60 3 470nF C22 805 47KΩR17 603 Vc cB1 J18 FICHE2MM

10nF C9 60 3 470nF C32 805 47KΩR18 603 VDDBUFF3V J17 FICHE2MM

10nF C18 60 3 470nF C37 805 50ΩR3 603 Vin J1 SMB/H

1KΩR2 603 470nF C38 805 50ΩR1 603 VrefM J5 FICHE2MM

32PIN J6 IDC32 470nF C13 805 74LCX573 U3 TSSOP20 VrefP J2 FICHE2MM

330pF C2 5 603 470nF C28 805 74LCX573 U2 TSS OP20 TS A1002 U1 TQFP 48

330pF C2 6 603 47 0nF C 10 8 05 CON 2 J16 S IP 2

TSA1201

Part Design Footprint Part Design Footprint Part Design Footprint Part Design Footprint

Type ator Type ator Type ator Type ator

10uF C2 4 1210 330pF C33 603 470nF C7 805 AVCC J12 FICHE2MM

10uF C2 3 1210 330pF C20 603 470nF C16 805 CLJ/SMB J4 SMB /H

10uF C4 1 1210 330pF C8 603 470nF C19 805 AGND J19 FICHE2MM

10uF C2 9 1210 330pF C2 603 470nF C3 805 DFSB J9 FICHE2MM

100pF C1 60 3 330pF C5 603 47KΩR12 603 DGND J20 FICHE2MM

10nF C12 60 3 33 0pF C 11 6 03 47KΩR14 603 DVCC J15 FICHE2MM

10nF C3 9 60 3 330pF C30 603 47KΩR11 603 GndB 1 J22 FICHE2MM

10nF C15 60 3 33 0pF C 17 6 03 47KΩR a j1 VR5 GndB 2 J2 1 F ICH E2 MM

10nF C4 0 60 3 33 0pF C 14 6 03 47KΩR10 603 Mes com mo de J8 FICHE2MM

10nF C2 7 60 3 47uF C36 CAP 47KΩR19 603 OEB J10 FICHE2MM

10nF C4 60 3 47uF C34 CAP 47KΩR13 6 03 R e gl c o m mo de J7 F ICH E2 MM

10nF C2 1 60 3 47uF C35 CAP 47KΩR15 603 T2-AT1-1WT T2 ADT

10nF C3 1 60 3 47uF C42 CAP 47KΩR16 603 T2-AT1-1WT T1 ADT

10nF C6 60 3 470nF C22 805 47KΩR17 603 Vc cB1 J18 FICHE2MM

10nF C9 60 3 470nF C32 805 47KΩR18 603 VDDBUFF3V J17 FICHE2MM

10nF C18 60 3 470nF C37 805 50ΩR3 603 Vin J1 SMB/H

1KΩR2 603 470nF C38 805 50ΩR1 603 VrefM J5 FICHE2MM

32PIN J6 IDC32 470nF C13 805 74LCX573 U3 TSSOP20 VrefP J2 FICHE2MM

330pF C2 5 603 470nF C28 805 74LCX573 U2 TSS OP20 TS A1002 U1 TQFP 48

330pF C2 6 603 47 0nF C 10 8 05 CON 2 J16 S IP 2

TSA1201

19/20

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the

consequences of use of such information nor for any infringement of patents or other rights ofthird parties which may resultfrom

its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications

mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information

previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or

systems without express written approval of STMicroelectronics.

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PACKAGE MECHANICAL DATA

48 PINS - PLASTIC PACKAGE

Dim. Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 1.60 0.063

A1 0.05 0.15 0.002 0.006

A2 1.35 1.40 1.45 0.053 0.055 0.057

B 0.17 0.22 0.27 0.007 0.009 0.011

C 0.09 0.20 0.004 0.008

D 9.00 0.354

D1 7.00 0.276

D3 5.50 0.216

e 0.50 0.0197

E 9.00 0.354

E1 7.00 0.276

E3 5.50 0.216

L 0.45 0.60 0.75 0.018 0.024 0.030

L1 1.00 0.039

K0°(min.), 7°(max.)

48 37

13 24

12 25

A1 A2

0,25 mm

.010 inch

GAGE PLANE

0,10 mm

.004 inch

SEATING PLANE

TSA1201

20/20