M34D64-RMN6T - STMicroelectronics

1/21April 2003

M34D64

64 Kbit Serial I²C Bus EEPROM

With Hardware Write Control on Top Quarter of Memory

FEATURES SUMMARY

■Two Wire I2C Serial Interface

Supports 400 kHz Protocol

■Single Supply Voltage:

– 2.5V to 5.5V for M34D64-W

– 1.8V to 5.5V for M34D64-R

■Hardware Write Control of th e top quarter of

memory

■BYTE and PAG E WRIT E (u p to 32 Byte s)

■RANDOM and SEQ UEN TIAL READ Modes

■Self-Tim ed P ro g ra m ming Cyc le

■Automatic Addres s Incrementing

■Enhanced E SD/La tch-Up Behavior

■More than 1M Erase/Write Cycles

■More than 40 Year Data Retention

Figure 1. Packages

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

M34D64

2/21

SUMMARY DESCRIPTION

These I2C-compatible electrically erasable

programmable memory (EEPROM) devices are

organized as 8192 x 8.

Figu re 2. L o gi c Diagram

These devices are compatible with the I2C

memory protocol. This is a two wire serial interface

that us es a bi-directional data bus and serial c lock .

The devices carry a built-in 4-bit Device Type

Identifier code (1010) in accordance with the I2C

bus def i nition.

The device behaves as a slave in the I2C protocol,

with all memory operations synchronized by the

serial clock. Read and Write operations are

initiated by a Start condi tion, generated by the bus

master. The Start condition is followed by a Device

Select Code and RW bit (as described in Table 2),

terminated by an acknow ledge bit.

When writing data to the memory, the device

inserts an acknowledge bit during the 9th bit time,

following the bus master’s 8-bit transmission.

When data is read by the bus master, the bus

master acknowledg es the receipt of the data byte

in the same way. Data transfers are terminated by

a Stop condition after an Ack for Write, and after a

NoAck for Read.

Table 1. Sign al Names

Power On Reset: VCC Lock-Out Write Protect

In order to prevent data corruption and inadvertent

Write operations during Power-up, a Power On

Reset (POR) circuit is in cluded. The in ternal reset

is held active until VCC has reached the POR

threshold value, and all opera tio ns are disab led –

the device will not respond to any command. In the

same way, when VCC drops from the operating

voltage, below the POR threshold value, all

operations are disabled and the device will not

respond to any com ma nd. A stab le a nd v alid VCC

must be applied before apply ing any logic signal.

Figure 3. SO and TSSOP Connections

Note: 1. See page 17 (onwards) for package dimensions, and how

to identify pin-1.

AI02850B

E0-E2 SDA

VCC

M34D64

SCL

VSS

E0, E1, E2 Chip Enable

SDA Serial Data

SCL Serial Clock

WC Write Control

VCC Supply Volta ge

VSS Ground

SDAVSS SCL

WCE1

E0 VCC

AI02851C

M34D64

3/21

M34D64

SIGNAL DESCRIPTION

Serial Clock (SCL)

This input signal is used to strobe all data in and

out of the device. I n applications where this signal

is used by slave devices to synchronize the bus to

a slower clock, the bus master must have an open

drain output, and a pull-up resistor must be con-

nected from Serial Clock (SCL) to VCC. (Figure 5

indicates how the v alu e of the p ull-up resistor c an

be calculated). In most applications, though, this

method of synchronization is not employed, and

so the pull-up resistor is not necessary, provided

that the bus master has a push-pull (rather than

open drain) output.

Serial Data (SDA)

This bi-directional signal is used to transfer dat a in

or out of the devi ce. It is an open drain output that

may be wi re-OR’ed with ot her op en drai n or open

collector signals on the bus. A pull up resistor must

be connected from Ser ial Data (SDA) to VCC. (Fi g-

ure 5 indicates how the value of the pull-up resistor

can be calculated).

Chip Enable (E0, E1, E2)

These input signals are used to set the value that

is to be looked f or on the three least significant bits

(b3, b2, b1) of the 7-bit Device Select Code. These

inputs must be tied to VCC or V SS, to establish the

Device Select Code.

Write Control (WC)

The hardware Write Con trol pin (WC) is useful for

protecting the top quarter of the memory (as

shown in Figure 4) from i nadvertent erase or wr ite.

The Write Control signal is used to enable

(WC=VIL) or disable (WC =VIH) write instructions to

the top quarter o f the memory area. When uncon-

nected, the WC input is internally read as VIL, and

write operations are allowed.

Figu re 4. Memory M a p showing W r i te Cont ro l

Area

Figure 5. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus

AI03114C

1FFFh

Write Controlled

Area

1000h

0000h

0800h

1800h

AI01665

VCC

CBUS

SDA

MASTER

SCL CBUS

100

CBUS (pF)

Maximum RP value (kΩ)

10 1000

fc = 400kHz

fc = 100kHz

M34D64

4/21

Figure 6. I2C Bus Protocol

Table 2. Device Select Code

No te : 1. The most signific ant bit, b 7, is sent firs t.

2. E0, E1 and E2 are com par ed agains t the r espect i ve exte rnal pins o n the memory dev i ce.

Table 3. Most Significant Byte Table 4. Least Significant Byte

Device Type Identifier1Chip Enable Address2RW

b7 b6 b5 b4 b3 b2 b1 b0

Device Select Code 1 0 1 0 E2 E1 E 0 RW

SCL

SDA

SCL

SDA

START

Condition

SDA

Input SDA

Change

AI00792B

STOP

Condition

123 789

MSB ACK

START

Condition

SCL 123 789

MSB ACK

STOP

Condition

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

5/21

M34D64

DEVICE OPERATION

The device supports the I2C protocol. This is

summarized in Figure 6. Any device that sends

data on to the bus is defined to be a transmitter,

and any device that reads the data to be a

receiver. The device that controls the data trans fer

is known as the bus master, and the other as the

slave device. A data t ransfer can only be initiated

by the bus master, which will also provide the

serial clock for synchronization. The M34D64

device is always a slave in all communi c ation.

Start Condition

Start is identified by a falling edge of Serial Data

(SDA) while Serial Clock (SCL) is stable in the

High state. A Start condition must precede any

data transfer command. The device continuously

monitors (except during a Write cycle ) Se ri a l Data

(SDA) and Serial Clock (SCL) for a Start condition,

and will not re spond unles s one is given.

Stop Condition

Stop is identified by a rising edge of Serial Data

(SDA) while Serial Clock (SCL) is stable and

driven High. A Stop condition terminates

communication between the device and the bus

master. A Read command that is followed by

NoAck can be followed by a Stop condition to force

the device into the Stand-by mode. A Stop

condition at the end of a Write command triggers

th e int er n a l EEPROM Writ e cycle.

Acknowledge Bit (ACK)

The acknowledge bit is used to indicate a

successful byte transfer. The bus transmitter,

whether it be bus master or slave device, releases

Serial Data (SDA) after sending eight bits of data.

During the 9th clock pulse period, the receiver pulls

Serial Data (SDA) Low to acknowledge the receipt

of the e ight data bits.

Data Input

During data input, the device samples Serial Data

(SDA) on the rising edge of Serial Clock (SCL).

For correct device operation, Serial Data (SDA)

must be stable during the rising edge of Serial

Clock (SCL), and the Serial Data (SDA) signal

must change

only

when Serial Clock (SCL) is

driven Low.

Memory Addressing

To start communication between the bus master

and the slave device, the bus mas ter must initiate

a Start condition. Following this, the bus master

sends the Device Select Code, shown in Table 2

(on Serial Data (SDA ), most significant bit f i rst).

The Device Select Code consists of a 4-bit Device

Type Identifier, and a 3-bit Chip Enable “Add re ss”

(E2, E1, E0). To address the memory array, t he 4-

bit Device Type Identifi er is 1010b.

Up to eight memory devices can be c onnect ed on

a single I 2C bus. Eac h one is given a uniq ue 3-bit

code on the Chip Enable (E0, E1, E2) inputs.

When the Device Select Code is received on

Serial Data (SDA), the device only responds if the

Chip Enable Addres s i s the s ame as the v alue on

the Chip Enable (E0, E1, E2) inputs.

The 8th bit is the Read/Write bit (RW). This bit is

set to 1 fo r Read and 0 for Write operations.

If a match occurs on the Device Select code, the

corresponding device gives an acknowledgment

on Serial Dat a (SDA) du ring the 9th bit time. If the

device does not match the Device Select code, it

deselects itself from the bus, and goes into Stand-

by mode.

Table 5. O per ating Modes

No te: 1. X = VIH or VIL.

Mode RW bit WC 1 Bytes Initial Sequence

Current Address Read 1 X 1 START, Device Select, RW = 1

Random Address Read 0X1

START, Device Select, RW = 0, Address

1 X reSTART, Device Select, RW = 1

Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read

Byte Write 0 VIL 1 START, Device Select, RW = 0

Page Write 0 VIL ≤ 32 START, Device Select, RW = 0

M34D64

6/21

Figu re 7. Wri t e Mode Se qu e nces with W C =0 (data writ e enab led)

Write Operations

Following a Start condition the b us master sends

a Device Select Code with the RW bi t re set to 0 .

The device acknowledges t hi s, as shown in Figure

7, and waits for two address bytes. The device re-

sponds to each addres s byte with an acknowledge

bit, and th en waits for the data byte(s).

Writing to the memory may be inhibited if Write

Control ( WC) is driven High. Any Write instruction

with Write Cont rol (WC ) driven High (during a pe-

riod of time from the Start condition until the end of

the two address byt es) will not modify the contents

of the top quarter of the memory.

Each data byte in the memory has a 16-bit (two

byte wide) addr ess. The Mos t Significant Byte (Ta-

ble 3) is sent first, f oll owed by the Least Significant

Byte (Table 4). Bit s b15 t o b0 form t he add ress of

the byte in memory.

When th e bus mast er generate s a Stop con dition

immediat ely after the Ack bi t (in t he “10th bit” time

slot), either at the end of a Byte Write or a Page

Write, the internal memory Write cycle is triggered.

A Stop condition at any other time slot does not

trigger the internal Write cycle.

During the internal Write cycle, Seria l Da ta (SDA)

is disabled in ternally, and the devi ce does not re-

spond to any requests.

Byte Write

After the Device Select code and the address

bytes, the bus master s ends one dat a byte. If the

addressed location is Wri te-protecte d (top qua rter

of the memory), by Write Control (WC) being driv-

en High, the location is not modified. The bus mas-

ter terminates the transfer by generating a Stop

condition, as shown in Figure 7.

Page Write

The Page Write m ode allows up to 32 by tes to be

written in a single Write cycle, provided that they

are all located in the same ’row’ in the memory:

that is, the most significant memory address bits

(b12-b5) are the same. If more bytes are sent than

will fit u p t o the end of t he row, a condition k nown

as ‘roll-over’ occurs. This should be avoided, as

STOP

START

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

START

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1

DATA IN 2

AI01106C

PAGE WRITE

(cont'd)

WC (cont'd)

STOP

DATA IN N

ACK

R/W

ACK ACK ACK

ACK ACK ACK ACK

R/W

ACKACK

7/21

M34D64

data starts to become overwritten in an i mplemen-

tation dependent way.

The bus master sends fr om 1 to 32 b ytes of data.

If Write Control ( WC) is High, the contents of the

addressed top quarter of the m emo ry location are

not modified. After each byte is transferred, the in-

ternal byte address counter (the 5 least significant

address bits only) is incremented. Th e transfer is

terminated by the bus master generating a Stop

condition.

Figu re 8. Writ e C yc le Polling Fl owchart usi ng ACK

Minimizing System Delays by Polling On ACK

During the internal Write cycle, the device

disconnects its elf fr om the bus, and writes a copy

of the data from its internal latches to the memory

cells. The maximum Write time (tw) is shown in

Tables 13 and 14, but the typical time is shorter.

To make use of this, a polling sequence can be

used by the bus master.

The sequence , as shown in Figure 8, is:

– Initial condition: a Write cycle is in progress.

– Step 1: the bus ma ster issues a Start condition

followed by a Device Select Code (the first byte

of the new instruction).

– Step 2: if the device is busy with the internal

Write cycle, no Ack will be returned and the bus

master goes back to Step 1. If the device has

terminated the internal Write cycle, it responds

with an Ack, indicating that the device is ready

to receive t he second part of t he i nstructi on (the

first byte of this instruction having been sent

during Step 1).

WRITE Cycle

in Progress

AI01847C

Operation is

Addressing the

Memory

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

YES

YESNO

ReSTART

STOP

DATA for the

WRITE Operation DEVICE SELECT

with RW = 1

Send Address

and Receive ACK

First byte of instruction

with RW = 0 already

decoded by the device

YESNO START

Condition

Continue the

WRITE Operation Continue the

Random READ Operation

M34D64

8/21

Figure 9. Read Mode Sequences

No te : 1. The s even mos t si gnific ant bits o f t he Devi ce Sel ect Code of a Ra ndom Read (in the 1st and 4th bytes) must be ide n tical.

Read Operation s

Read operations are performed independently of

the stat e of the Write Cont rol (WC) signal.

Random Address Read

A dummy Write is performed to load the address

into the address counter (as shown in Figure 9) but

without

sending a Stop condition. Then, the bus

master sends another Start condit ion, and repeats

the Device Sel ect Code, with t he RW bit set to 1.

The device acknowledges this, and outputs the

contents of the addressed byte. The bus master

must

not

acknowledge the byte, and terminates

the transfer with a Stop condition.

Current Address Read

The device has an internal address counter which

is incremented each time a byte is read. For the

Current Address Read operation, following a Start

condition, the bus master only sends a Device

Select Code with the RW bit set to 1. The device

acknowledges this, and outputs the byte

addressed by the internal address counter. The

counter is then incremented. The bus master

terminates the transfer with a Stop condition, as

shown in Figure 9,

without

acknowledging the

byte.

START

DEV SEL * BYTE ADDR BYTE ADDR

START

DEV SEL DATA OUT 1

AI01105C

DATA OUT N

STOP

START

CURRENT

ADDRESS

READ DEV SEL DATA OUT

RANDOM

ADDRESS

READ

STOP

START

DEV SEL * DATA OUT

SEQUENTIAL

CURRENT

READ

STOP

DATA OUT N

START

DEV SEL * BYTE ADDR BYTE ADDR

SEQUENTIAL

RANDOM

READ

START

DEV SEL * DATA OUT 1

STOP

ACK

R/W

NO ACK

ACK

R/W

ACK ACK ACK

R/W

ACK ACK ACK NO ACK

R/W

NO ACK

ACK ACK ACK

R/W

ACK ACK

R/W

ACK NO ACK

9/21

M34D64

Sequenti al R ead

This operation can be used after a Current

Address Read or a Random Address Read. The

bus master

does

acknowledge the data byte

output, and sends additional clock pulses so that

the device continues to output the next byte in

sequence. To terminate the stream of bytes, the

bus master must

not

acknowledge the last byte,

and

must

generate a Stop condition, as shown in

Figure 9.

The output data comes from consecutive

addresses, with the internal address counter

automatical ly i ncremen ted af ter each byt e out put.

After the last memory address, the address

counter ‘rolls-over’, and the device continues to

output data from memory address 00h.

Acknowledge in Read Mode

For all Read commands, the device waits, after

each byte read, f or an acknowledgment during the

9th bit time. I f the bus mast er does not drive Ser ial

Data (SDA) Low during this time, the device

terminates the data transfer and switches to its

Stand-by mode.

M34D64

10/21

MA XIMUM R AT I N G

Stressing the device ab ove t he rating listed in the

Absolute Maximum Ratings" table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at t hes e or

any other con ditions ab ove those i ndicated i n the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 6. Absolute Maximum Ratings

Not e: 1 . IPC/JEDEC J- ST D-02 0 A

2. JE DEC Std J ESD22 -A114A (C1=100 pF, R1=15 00 Ω, R2=500 Ω)

Symbol Parameter Min. Max. Unit

TSTG Storage Temperature –65 150 °C

TLEAD Lead Temperature during

Soldering SO: 20 seconds (max) 1

TSSOP: 20 seconds (max) 1235

235 °C

VIO Input or Output range –0.6 6.5 V

VCC Supply Voltage –0.3 6.5 V

VESD Electrostatic Discharge Voltage (Human Body model) 2–4000 4000 V

11/21

M34D64

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, and the DC and AC charac-

teristics of the de vice. The parameters in the DC

and AC Characteristic tables that follow are de-

rived from tests performed under the Measure-

ment Conditions summarized in the relevant

tables. Des igners shoul d c heck that the operating

conditions i n their circuit match the meas urement

conditions when relying on the quoted parame-

ters.

Table 7. Operating Conditions (M34 D64 -W)

Table 8. O perating Conditions (M34D64-R)

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 2.5 5.5 V

TAAmb ient Operati ng Temperatur e –40 85 °C

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 1.8 5.5 V

TAAmb ient Operati ng Temperatur e –4 0 85 ° C

M34D64

12/21

Table 9. AC Measu remen t Conditions

Figure 10. AC Measurement I/O Waveform

Table 10. Input Parameter s

Note: 1. TA = 25 °C, f = 400 kH z

2. Sampled only, not 100% tested.

Symbol Parameter Min. Max. Unit

CLLoad Capacitance 100 pF

Input Rise and Fall Times 50 ns

Input Levels 0.2VCC to 0.8VCC V

Input and Output Timing Reference Levels 0.3VCC to 0.7VCC V

Symbol Parameter1,2 Test Condition Min.Max.Unit

CIN Input Capa citanc e (SDA) 8 pF

CIN Input Capacitance (other pins) 6 pF

ZWCL WC Input Impedance VIN < 0.5 V 50 300 kΩ

ZWCH WC Input Impedance VIN > 0.7VCC 500 kΩ

tNS Pulse width ignored

(Input Filter on SCL and SDA) Single glitch 100 ns

AI00825B

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Input and Output

Timing Reference Levels

Input Levels

13/21

M34D64

Table 11. DC Characteristics (M34D64-W)

Table 12. DC Characteristics (M34D64-R)

Symbol Parameter Test Condition

(in addition to those in Table 7) Min. Max. Unit

ILI Input Leakage Curren t

(SCL, SDA) VIN = VSS or VCC

device in Stand-by mode ± 2 µA

ILO Output Leakage Current VOUT = VSS or VCC, SDA in Hi-Z ± 2 µA

ICC Supply Current VCC =2.5V, fc=400kHz (rise/fall time < 30ns) 1mA

CC1 Stand -by Supply Current VIN = VSS or VCC , VCC = 5 V 10 µA

VIN = VSS or VCC , VCC = 2.5 V 2 µA

VIL

Input Low Vol tage

(E2, E1, E0, SCL, SDA) –0.3 0.3VCC V

Input Low Voltage (WC) –0.3 0.5 V

VIH Input High Volta ge

(E2, E1, E0, SCL, SDA, WC)0.7VCC VCC+1 V

VOL Output Low Voltage IOL = 2.1 mA, VCC = 2.5 V 0.4 V

Symbol Parameter Test Condition

(in addition to those in Table 8) Min. Max. Unit

ILI Input Leakage Curren t

(SCL, SDA) VIN = VSS or VCC

device in Stand-by mode ± 2 µA

ILO Output Leakage Current VOUT = VSS or VCC, SDA in Hi-Z ± 2 µA

ICC Supply Current VCC =1.8V, fc=100kHz (rise/fall time < 30ns) 0.8 mA

ICC1 Stand -by Supply Current VIN = VSS or VCC , VCC = 1.8 V 0.2 µA

VIL

Input Low Vol tage

(E2, E1, E0, SCL, SDA) – 0.3 0.3 VCC V

Input Low Voltage (WC) –0.3 0.5 V

VIH Input High Volta ge

(E2, E1, E0, SCL, SDA, WC)0.7VCC VCC+1 V

VOL Output Low Voltage IOL = 0.7 mA, VCC = 1.8 V 0.2 V

M34D64

14/21

Table 13. AC Characteristics (M34D64-W)

No te : 1. For a r eSTART condition, o r fo l lowing a Writ e cy cl e.

2. Sampled only, not 100% tested.

3. To avoid spurious START and STOP conditions, a minimum delay i s placed between SCL=1 and the falling or rising edge of SDA.

4. The Write Time of 5 ms only applies to devices bearing the process identification letter "B" in the package marking (on the top side

of th e pack -a ge), o ther wis e (for devi ces beari ng th e pr oces s ident if icatio n l etter " N") t he Write T ime is 1 0 ms . For f urthe r details,

plea se conta ct your nearest S T sal es offi ce.

Test conditions specified in Table 9 and Table 7

Symbol Alt. Parameter Min. Max. Unit

fCfSCL Clock Fre quenc y 400 kHz

tCHCL tHIGH Clock Pulse Width High 600 ns

tCLCH tLOW Clock Pulse Width Low 1300 ns

tCH1CH2 tRCl ock Rise T ime 300 ns

tCL1CL2 tFClock Fall Time 300 ns

tDH1DH2 2tRSDA Rise Time 20 300 ns

tDL1DL2 2tFSDA Fall Time 20 300 ns

tDXCX tSU:DAT Data In Set Up Time 100 ns

tCLDX tHD:DAT Data In Hold Time 0 ns

tCLQX tDH Data Out Hold Time 200 ns

tCLQV 3tAA Clock Low to Next Data Valid (Access Time) 200 900 ns

tCHDX 1tSU:STA Start Condition Set Up Time 600 ns

tDLCL tHD:STA Start Condition Hold Time 600 ns

tCHDH tSU:STO Stop Condition Set Up Time 600 ns

tDHDL tBUF Time between Stop Condition and Next Start Condition 1300 ns

tWtWR Write Time 5 or4 10 ms

15/21

M34D64

Table 14. AC Characteristics (M34D64-R)

No te : 1. For a r eSTART condition, o r fo l lowing a Writ e cy cl e.

2. Sampled only, not 100% tested.

3. To avoid spurious START and STOP conditions, a minimum delay i s placed between SCL=1 and the falling or rising edge of SDA.

Test conditions specified in Table 9 and Table 8

Symbol Alt. Parameter Min. Max. Unit

fCfSCL Cl ock Fre quen cy 400 kHz

tCHCL tHIGH Clock Pulse Width High 600 ns

tCLCH tLOW Clock Pulse Width Low 1300 ns

tDL1DL2 2tFSDA Fall Time 20 300 ns

tDXCX tSU:DAT Data In Set Up Time 100 ns

tCLDX tHD:DAT Data In Hold Time 0 ns

tCLQX tDH Data Out Hold Time 200 ns

tCLQV 3tAA Clock Low to Next Data Valid (Access Time) 200 900 ns

tCHDX 1tSU:STA Start Condition Set Up Time 600 ns

tDLCL tHD:STA Start Condition Hold Time 600 ns

tCHDH tSU:STO Stop Condition Set Up Time 600 ns

tDHDL tBUF Time between Stop Condition and Next Start

Condition 1300 ns

tWtWR Write Time 10 ms

M34D64

16/21

Figure 11. AC Waveforms

SCL

SDA In

SCL

SDA Out

SCL

SDA In

tCHCL

tDLCL

tCHDX

START

Condition

tCLCH

tDXCXtCLDX

SDA

Input

SDA

Change tCHDH tDHDL

STOP

Condition

Data Valid

tCLQV tCLQX

tCHDH

STOP

Condition

tCHDX

START

Condition

Write Cycle

AI00795C

START

Condition

17/21

M34D64

PACKAGE MECHANICAL

SO8 narrow – 8 lead Plastic Smal l Outline, 150 mils body wi dth, Pac kage Outline

Not e: Drawing is not to scale.

SO8 narrow – 8 lead Plastic Smal l Outline, 150 mils body wi dth, Pac kage Mechanical Data

SO-a

LA1 α

h x 45˚

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e 1.27 – – 0.050 – –

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 0.90 0.016 0.035

α0° 8° 0° 8°

N8 8

CP 0.10 0.004

M34D64

18/21

TSSOP8 – 8 lead Thin Shrink Small O utline, Packag e Outline

No te s: 1. Dra wi ng is not to scale.

TSSOP8 – 8 lead Thin Shrink Small O utline, Packag e Mec han ical Data

TSSOP8AM

EE1

A2A

Symbol mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.200 0.0472

A1 0.050 0.150 0.0020 0.0059

A2 1.000 0.800 1.050 0.0394 0.0315 0.0413

b 0.190 0.300 0.0075 0.0118

c 0.090 0.200 0.0035 0.0079

CP 0.100 0.0039

D 3.000 2.900 3.100 0.1181 0.1142 0.1220

e 0.650 – – 0.0256 – –

E 6.400 6.200 6.600 0.2520 0.2441 0.2598

E1 4.400 4.300 4.500 0.1732 0.1693 0.1772

L 0.600 0.450 0.750 0.0236 0.0177 0.0295

L1 1.000 0.0394

α0° 8° 0° 8°

19/21

M34D64

PAR T NUMBERING

Table 15. Ordering Information Scheme

Devices are shipped from the factory with the

memory c ontent set at all 1s (FFh). For a list of available options (speed, package,

etc.) or for further information on any aspect of this

device, please con tact your nearest ST Sales O f-

fice.

Example: M34D64 –WMN6T

Device Type

M34 = I2C Application Specific Standard Product serial

access EEPROM

Device Function

64 = 64 Kbit (8192 x 8)

Operating Voltage

W = VCC = 2.5 to 5.5V

R = VCC = 1.8 to 5.5V

Package

MN = SO8 (150 mil width)

DW = TSSOP8 (169 mil width)

Temperature Range

6 = –40 to 85 °C

Option

T = Tape & Reel Packing

M34D64

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RE VISION H IST ORY

Table 16. Document Revisio n History

Date Rev. Description of Revision

23-Mar-1999 1.0 Document written

09-Jun-1999 1.1 Memory Map illustration added. Line removed from Tab-2

16-Nov-2000 1.2 M34D32 removed; PSDIP8 package removed; 4.5 to 5.5V and 1.8 to 3.6V ranges removed; 0

to 70°C and -20 to 85°C ranges removed

13-Sep-2002 2.0 New edition. TSSOP8 package added

04-Apr-2003 2.1 Addresses on Memory Map figure corrected.

tW of 5ms offered on certain versions of the device (bearing process identification letter “B”)

21/21

M34D64

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