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M34D64
DEVICE OPERATION
The device supports the I2C protocol. This is
summarized in Figure 6. Any device that sends
data on to the bus is defined to be a transmitter,
and any device that reads the data to be a
receiver. The device that controls the data trans fer
is known as the bus master, and the other as the
slave device. A data t ransfer can only be initiated
by the bus master, which will also provide the
serial clock for synchronization. The M34D64
device is always a slave in all communi c ation.
Start Condition
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle ) Se ri a l Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not re spond unles s one is given.
Stop Condition
Stop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable and
driven High. A Stop condition terminates
communication between the device and the bus
master. A Read command that is followed by
NoAck can be followed by a Stop condition to force
the device into the Stand-by mode. A Stop
condition at the end of a Write command triggers
th e int er n a l EEPROM Writ e cycle.
Acknowledge Bit (ACK)
The acknowledge bit is used to indicate a
successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases
Serial Data (SDA) after sending eight bits of data.
During the 9th clock pulse period, the receiver pulls
Serial Data (SDA) Low to acknowledge the receipt
of the e ight data bits.
Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change
only
when Serial Clock (SCL) is
driven Low.
Memory Addressing
To start communication between the bus master
and the slave device, the bus mas ter must initiate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in Table 2
(on Serial Data (SDA ), most significant bit f i rst).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable “Add re ss”
(E2, E1, E0). To address the memory array, t he 4-
bit Device Type Identifi er is 1010b.
Up to eight memory devices can be c onnect ed on
a single I 2C bus. Eac h one is given a uniq ue 3-bit
code on the Chip Enable (E0, E1, E2) inputs.
When the Device Select Code is received on
Serial Data (SDA), the device only responds if the
Chip Enable Addres s i s the s ame as the v alue on
the Chip Enable (E0, E1, E2) inputs.
The 8th bit is the Read/Write bit (RW). This bit is
set to 1 fo r Read and 0 for Write operations.
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Dat a (SDA) du ring the 9th bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.
Table 5. O per ating Modes
No te: 1. X = VIH or VIL.
Mode RW bit WC 1 Bytes Initial Sequence
Current Address Read 1 X 1 START, Device Select, RW = 1
Random Address Read 0X1
START, Device Select, RW = 0, Address
1 X reSTART, Device Select, RW = 1
Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read
Byte Write 0 VIL 1 START, Device Select, RW = 0
Page Write 0 VIL ≤ 32 START, Device Select, RW = 0