1
FEATURES DESCRIPTION
IN
NC
NC
EN
8
7
6
5
OUT
NC
NR/FB
GND
1
2
3
4
DRB PACKAGE
(TOP VIEW)
NC – No internal connection
1
2
3
5
4
OUT
NR/FBEN
GNDGND
IN
DBV PACKAGE
(TOP VIEW)
APPLICATIONS
TPS732xx
GNDEN NR
IN OUT
VIN VOUT
Optional
Optional Optional
Typical Application Circuit for Fixed-Voltage Versions
TPS73201-Q1 , , TPS73215-Q1 , , TPS73216-Q1TPS73218-Q1 , TPS73225-Q1 , TPS73230-Q1TPS73233-Q1 , TPS73250-Q1
www.ti.com
........................................................................................................................................................... SGLS303D – MAY 2005 – REVISED MARCH 2009
CAP-FREE NMOS 250-mA LOW-DROPOUT REGULATORWITH REVERSE-CURRENT PROTECTION
•Qualified for Automotive Applications
The TPS732xx family of low-dropout (LDO) voltageregulators uses a new topology: an NMOS pass•Stable with No Output Capacitor or Any Value
element in a voltage-follower configuration. Thisor Type of Capacitor
topology is stable using output capacitors with low•Input Voltage Range: 1.7 V to 5.5 V
ESR, and even allows operation without a capacitor.•Ultralow Dropout Voltage:
It also provides high reverse blockage (low reverse40 mV Typ at 250 mA
current) and ground pin current that is nearly constantover all values of output current.•Excellent Load Transient Response — With orWithout Optional Output Capacitor
The TPS732xx uses an advanced BiCMOS processto yield high precision while delivering low dropout•New NMOS Topology Provides Low Reverse
voltages and low ground pin current. CurrentLeakage Current
consumption, when not enabled, is under 1 µA and•Low Noise: 30 µV
RMS
Typ (10 kHz to 100 kHz)
ideal for portable applications. The extremely low•0.5% Initial Accuracy
output noise (30 µV
RMS
with 0.1 µ F C
NR
) is ideal forpowering VCOs. These devices are protected by•1% Overall Accuracy (Line, Load, and
thermal shutdown and foldback current limit.Temperature)
•Less Than 1 µA Max I
Q
in Shutdown Mode•Thermal Shutdown and Specified Min/MaxCurrent Limit Protection•Available in Multiple Output Voltage Versions– Fixed Outputs of 1.2 V, 1.5 V, 1.6 V, 1.8 V,2.5 V, 3 V, 3.3 V, and 5 V– Adjustable Outputs From 1.2 V to 5.5 V– Custom Outputs Available
•Portable/Battery-Powered Equipment•Post-Regulation for Switching Supplies•Noise-Sensitive Circuitry Such as VCOs•Point of Load Regulation for DSPs, FPGAs,ASICs, and Microprocessors
Figure 1.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
Copyright © 2005 – 2009, Texas Instruments IncorporatedPRODUCTION DATA information current as of publication date.Products conform to specifications per the terms of TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ABSOLUTE MAXIMUM RATINGS
POWER DISSIPATION RATINGS
(1)
TPS73201-Q1 , , TPS73215-Q1 , , TPS73216-Q1TPS73218-Q1 , TPS73225-Q1 , TPS73230-Q1TPS73233-Q1 , TPS73250-Q1
SGLS303D – MAY 2005 – REVISED MARCH 2009 ...........................................................................................................................................................
www.ti.com
ORDERING INFORMATION
(1)
V
OUTT
J
PACKAGE
(3)
ORDERABLE PART NUMBER TOP-SIDE MARKING(TYP)
(2)
SOT23-5 – DBV Reel of 3000 TPS73201QDBVRQ1 PJOQAdjustable
or 1.2 V
(4)
VSON-8 – DRB Reel of 3000 TPS73201QDRBRQ1 PSAQ1.5 V SOT23-5 – DBV Reel of 3000 TPS73215DBVRQ1
(5)
PREVIEW1.6 V SOT23-5 – DBV Reel of 3000 TPS73216DBVRQ1
(5)
PREVIEW– 40 ° C to 125 ° C 1.8 V SOT23-5 – DBV Reel of 3000 TPS73218DBVRQ1
(5)
PREVIEW2.5 V SOT23-5 – DBV Reel of 3000 TPS73225QDBVRQ1 PJNQ3 V SOT23-5 – DBV Reel of 3000 TPS73230DBVRQ1
(5)
PREVIEW3.3 V SOT23-5 – DBV Reel of 3000 TPS73233DBVRQ1
(5)
PREVIEW5 V SOT23-5 – DBV Reel of 3000 TPS73250DBVRQ1
(5)
PREVIEW
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .(2) Custom output voltages from 1.3 V to 4 V in 100-mV increments are available on a quick-turn basis for prototyping. Productionquantities are available; minimum order quantities apply. Contact Texas Instruments for details and availability.(3) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .(4) For fixed 1.2-V operation, tie FB to OUT.(5) Product Preview
over operating junction temperature range unless otherwise noted
(1)
TPS732xx UNIT
V
IN
range – 0.3 to 6 VV
EN
range – 0.3 to 6 VV
OUT
range – 0.3 to 5.5 VPeak output current Internally limitedOutput short-circuit duration IndefiniteContinuous total power dissipation See Power Dissipation RatingsJunction temperature range, T
J
– 55 to +150 ° CStorage temperature range – 65 to +150 ° CESD rating, HBM
(2)
(H2) 4 kVESD rating, CDM
(2)
(C4) 1 kVESD rating, MM
(2)
(M2) 200 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristicsis not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.(2) ESD Protection Level per AEC Q100 Classification
DERATING FACTOR T
A
≤25 ° C T
A
= 70 ° C T
A
= 85 ° CBOARD PACKAGE R
θJC
R
θJA
ABOVE T
A
= 25 ° C POWER RATING POWER RATING POWER RATING
Low-K
(2)
DBV 64 ° C/W 255 ° C/W 3.9 mW/ ° C 390 mW 215 mW 155 mWHigh-K
(3)
DBV 64 ° C/W 180 ° C/W 5.6 mW/ ° C 560 mW 310 mW 225 mWHigh-K
(3)
DRB 1.2 ° C/W 40 ° C/W 25.0 mW/ ° C 2.50 W 1.38 W 1 W
(1) See Power Dissipation in the Application Information section for more information related to thermal design.(2) The JEDEC Low-K (1s) board design used to derive this data was a 3 inch x 3 inch, two-layer board with 2-ounce copper traces on topof the board.(3) The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1-ounce internal power andground planes and 2-ounce copper traces on the top and bottom of the board.
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Product Folder Link(s): TPS73201-Q1 TPS73215-Q1 TPS73216-Q1 TPS73218-Q1 TPS73225-Q1 TPS73230-Q1TPS73233-Q1 TPS73250-Q1
ELECTRICAL CHARACTERISTICS
TPS73201-Q1 , , TPS73215-Q1 , , TPS73216-Q1TPS73218-Q1 , TPS73225-Q1 , TPS73230-Q1TPS73233-Q1 , TPS73250-Q1
www.ti.com
........................................................................................................................................................... SGLS303D – MAY 2005 – REVISED MARCH 2009
Over operating temperature range (T
J
= – 40 ° C to 125 ° C), V
IN
= V
OUT(nom)
+ 0.5 V
(1)
, I
OUT
= 10 mA, V
EN
= 1.7 V, andC
OUT
= 0.1 µF, unless otherwise noted. Typical values are at T
J
= 25 ° C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IN
Input voltage range
(1)
1.7 5.5 VV
FB
Internal reference (TPS73201) T
J
= 25 ° C 1.198 1.2 1.21 VOutput voltage range (TPS73201)
(2)
V
FB
5.5 – V
DO
VAccuracy
(1)
Nominal T
J
= 25 ° C – 0.5% +0.5%V
OUT
(V
OUT
+ 0.5 V) ≤V
IN
≤5.5 V,V
IN
, I
OUT
, and T
J
– 1% 0.5% +1%10 mA ≤I
OUT
≤250 mA
ΔV
OUT
%/ ΔV
IN
Line regulation
(1)
(V
OUT(nom)
+ 0.5 V) ≤V
IN
≤5.5 V 0.06 %/V1 mA ≤I
OUT
≤250 mA 0.002ΔV
OUT
%/ ΔI
OUT
Load regulation %/mA10 mA ≤I
OUT
≤250 mA 0.0008Dropout voltage
(3)V
DO
I
OUT
= 250 mA 40 150 mV(V
IN
= V
OUT
(nom) – 0.1 V)Z
O
(DO) Output impedance in dropout 1.7 V ≤V
IN
≤(V
OUT
+ V
DO
) 0.25 Ω
I
CL
Output current limit V
OUT
= 0.9 × V
OUT(nom)
250 425 600 mAI
SC
Short-circuit current V
OUT
= 0 V 300 mAI
REV
Reverse leakage current
(4)
( – I
IN
) V
EN
≤0.5 V, 0 V ≤V
IN
≤V
OUT
0.1 10 µAI
OUT
= 10 mA (I
Q
) 400 550I
GND
Ground pin current µAI
OUT
= 250 mA 650 950I
SHDN
Shutdown current (I
GND
) V
EN
≤0.5 V, V
OUT
≤V
IN
≤5.5 0.02 1 µAf = 100 Hz, I
OUT
= 250 mA 58Power-supply rejection ratioPSRR dB(ripple rejection)
f = 10 kHz, I
OUT
= 250 mA 37C
OUT
= 10 µF, No C
NR
27 × V
OUTOutput noise voltageV
N
µV
RMSBW = 10 Hz – 100 kHz
C
OUT
= 10 µF, C
NR
= 0.01 µF 8.5 × V
OUT
V
OUT
= 3 V, R
L
= 30 Ωt
STR
Startup time 600 µsC
OUT
= 1 µF, C
NR
= 0.01 µFV
EN
(HI) Enable high (enabled) 1.7 V
IN
VV
EN
(LO) Enable low (shutdown) 0 0.5 VI
EN
(HI) Enable pin current (enabled) V
EN
= 5.5 V 0.02 0.1 µAShutdown, Temperature increasing 160T
SD
Thermal shutdown temperature ° CReset, Temperature decreasing 140
(1) Minimum V
IN
= V
OUT
+ V
DO
or 1.7 V, whichever is greater.(2) TPS73201 is tested at V
OUT
= 2.5 V.(3) V
DO
is not measured for the TPS73215 or TPS73216, because minimum V
IN
= 1.7 V.(4) Fixed-voltage versions only; see the Application Information section for more information.
Copyright © 2005 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPS73201-Q1 TPS73215-Q1 TPS73216-Q1 TPS73218-Q1 TPS73225-Q1 TPS73230-Q1TPS73233-Q1 TPS73250-Q1
Servo
Error
Amp
Ref
27kΩ
8kΩ
Current
Limit
Charge
Pump
Thermal
Protection
Bandgap
NR
OUT
R1
R2
EN
GND
IN
R1+ R2= 80kΩ
VOUT
1.2V
1.5V
1.8V
2.5V
2.8V
3.0V
3.3V
5.0V
R1
Short
23.2kΩ
28.0kΩ
39.2kΩ
44.2kΩ
46.4kΩ
52.3kΩ
78.7kΩ
R2
Open
95.3kΩ
56.2kΩ
36.5kΩ
33.2kΩ
30.9kΩ
30.1kΩ
24.9kΩ
Table 1. Standard 1%
Resistor Values for
Common Output Voltages
NOTE: VOUT = (R1 + R2)/R2 × 1.204;
R1R2 ≅ 19kΩ for best
accuracy.
Servo
Error
Amp
Ref
Current
Limit
Charge
Pump
Thermal
Protection
Bandgap
OUT
FB
R1
R2
EN
GND
IN
80kΩ
8kΩ
27kΩ
TPS73201-Q1 , , TPS73215-Q1 , , TPS73216-Q1TPS73218-Q1 , TPS73225-Q1 , TPS73230-Q1TPS73233-Q1 , TPS73250-Q1
SGLS303D – MAY 2005 – REVISED MARCH 2009 ...........................................................................................................................................................
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FUNCTIONAL BLOCK DIAGRAMS
Figure 2. Fixed Voltage Version
Figure 3. Adjustable Voltage Version
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PIN ASSIGNMENTS
IN
NC
NC
EN
8
7
6
5
OUT
NC
NR/FB
GND
1
2
3
4
DRB PACKAGE
(TOP VIEW)
NC – No internal connection
1
2
3
5
4
OUT
NR/FBEN
GNDGND
IN
DBV PACKAGE
(TOP VIEW)
TPS73201-Q1 , , TPS73215-Q1 , , TPS73216-Q1TPS73218-Q1 , TPS73225-Q1 , TPS73230-Q1TPS73233-Q1 , TPS73250-Q1
www.ti.com
........................................................................................................................................................... SGLS303D – MAY 2005 – REVISED MARCH 2009
TERMINAL FUNCTIONS
TERMINAL
NO. DESCRIPTIONNAME
DBV DRB
IN 1 8 Unregulated input supplyGND 2 4, Pad Ground
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdownEN 3 5 mode. See the Shutdown section under Applications Information for more details. EN can be connected to INif not used.Fixed voltage versions only — connecting an external capacitor to this pin bypasses noise generated by theNR 4 3
internal bandgap. This allows output noise to be reduced to low levels.Adjustable voltage version only — this is the input to the control loop error amplifier, and is used to set theFB 4 3
output voltage of the device.NC — 2, 6, 7 No internal connectionOUT 5 1 Output of the regulator. There are no output capacitor requirements for stability.
Copyright © 2005 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS73201-Q1 TPS73215-Q1 TPS73216-Q1 TPS73218-Q1 TPS73225-Q1 TPS73230-Q1TPS73233-Q1 TPS73250-Q1
TYPICAL CHARACTERISTICS
0.5
0.4
0.3
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
−0.5
Change in VOUT (%)
0 50 100 150 200 250
IOUT (mA)
Referred to IOUT = 10mA
−40_C
+125_C
+25_C
0.20
0.15
0.10
0.05
0
−0.05
−0.10
−0.15
−0.20
Change in VOUT (%)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VIN −VOUT (V)
+125_C+25_C
−40_C
Referred to VIN = VOUT + 0.5V at IOUT = 10mA
100
80
60
40
20
0
VDO (mV)
0 50 100 150 200 250
IOUT (mA)
+125_C
+25_C
−40_C
TPS73225DBV
100
80
60
50
20
0
VDO (mV)
−50 −25 0 25 50 75 100 125
Temperature (_C)
TPS73225DBV
30
25
20
15
10
5
0
Percent of Units (%)
−1.0
−0.9
−0.8
−0.7
−0.6
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VOUT Error (%)
IOUT = 10mA
TPS73201-Q1 , , TPS73215-Q1 , , TPS73216-Q1TPS73218-Q1 , TPS73225-Q1 , TPS73230-Q1TPS73233-Q1 , TPS73250-Q1
SGLS303D – MAY 2005 – REVISED MARCH 2009 ...........................................................................................................................................................
www.ti.com
For all voltage versions at T
J
= 25 ° C, V
IN
= V
OUT(nom)
+ 0.5 V, I
OUT
= 10 mA, V
EN
= 1.7 V, and C
OUT
= 0.1 µF, unless otherwisenoted
LOAD REGULATION LINE REGULATION
Figure 4. Figure 5.
DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs TEMPERATURE
Figure 6. Figure 7.
OUTPUT VOLTAGE ACCURACY HISTOGRAM OUTPUT VOLTAGE DRIFT HISTOGRAM
Figure 8. Figure 9.
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Product Folder Link(s): TPS73201-Q1 TPS73215-Q1 TPS73216-Q1 TPS73218-Q1 TPS73225-Q1 TPS73230-Q1TPS73233-Q1 TPS73250-Q1
1000
900
800
700
600
500
400
300
200
100
0
IGND (µA)
0 50 100 150 200 250
IOUT (mA)
VIN = 5.5V
VIN = 4V
VIN = 2V
800
700
600
500
400
300
200
100
0
IGND (µA)
−50 −25 0 25 50 75 100 125
Temperature (_C)
IOUT = 250mA
VIN = 5.5V
VIN = 4V
VIN = 2V
500
450
400
350
300
250
200
150
100
50
0
Current Limit (mA)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VOUT (V)
TPS73233
ICL
ISC
1
0.1
0.01
IGND (µA)
−50 −25 0 25 50 75 100 125
Temperature (_C)
VENABLE = 0.5V
VIN = VOUT + 0.5V
600
550
500
450
400
350
300
250
Current Limit (mA)
1.5 2.5 3.0 3.5 4.0 4.5 5.02.0 5.5
VIN (V)
600
550
500
450
400
350
300
250
Current Limit (mA)
−50 −25 0 25 50 75 100 125
Temperature (_C)
TPS73201-Q1 , , TPS73215-Q1 , , TPS73216-Q1TPS73218-Q1 , TPS73225-Q1 , TPS73230-Q1TPS73233-Q1 , TPS73250-Q1
www.ti.com
........................................................................................................................................................... SGLS303D – MAY 2005 – REVISED MARCH 2009
TYPICAL CHARACTERISTICS (continued)For all voltage versions at T
J
= 25 ° C, V
IN
= V
OUT(nom)
+ 0.5 V, I
OUT
= 10 mA, V
EN
= 1.7 V, and C
OUT
= 0.1 µF, unless otherwisenoted
GROUND PIN CURRENT vs OUTPUT CURRENT GROUND PIN CURRENT vs TEMPERATURE
Figure 10. Figure 11.
CURRENT LIMIT vs V
OUT
GROUND PIN CURRENT IN SHUTDOWN(FOLDBACK) vs TEMPERATURE
Figure 12. Figure 13.
CURRENT LIMIT vs V
IN
CURRENT LIMIT vs TEMPERATURE
Figure 14. Figure 15.
Copyright © 2005 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TPS73201-Q1 TPS73215-Q1 TPS73216-Q1 TPS73218-Q1 TPS73225-Q1 TPS73230-Q1TPS73233-Q1 TPS73250-Q1
40
35
30
25
20
15
10
5
0
PSRR (dB)
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VIN −VOUT (V)
Frequency = 100kHz
COUT = 10µF
CNR = 0.01µF
10k10
90
80
70
60
50
40
30
20
10
0
Ripple Rejection (dB)
100 1k 100k 1M 10M
Frequency (Hz)
IOUT = 1mA
COUT = 1µF
IOUT = Any
COUT = 0µF
IOUT = 1mA
COUT = Any
IOUT = 1mA
COUT = 10µF
IOUT = 100mA
COUT = Any
IOUT = 100mA
COUT = 10µF
IO=100mA
CO=1µF
1
0.1
0.01
eN(µV/√Hz)
10 100 1k 10k 100k
Frequency (Hz)
COUT = 1µF
COUT = 0µF
COUT = 10µF
IOUT = 150mA
1
0.1
0.01
eN(µV/√Hz)
10 100 1k 10k 100k
Frequency (Hz)
IOUT = 150mA
COUT = 1µF
COUT = 0µF
COUT = 10µF
60
50
40
30
20
10
0
VN(RMS)
COUT (µF)
0.1 1 10
VOUT = 5.0V
VOUT = 3.3V
VOUT = 1.5V
CNR = 0.01µF
10Hz < Frequency < 100kHz
140
120
100
80
60
40
20
0
VN(RMS)
CNR (F)
1p 10p 100p 1n 10n
VOUT = 5.0V
VOUT = 3.3V
VOUT = 1.5V
COUT = 0µF
10Hz < Frequency < 100kHz
TPS73201-Q1 , , TPS73215-Q1 , , TPS73216-Q1TPS73218-Q1 , TPS73225-Q1 , TPS73230-Q1TPS73233-Q1 , TPS73250-Q1
SGLS303D – MAY 2005 – REVISED MARCH 2009 ...........................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (continued)For all voltage versions at T
J
= 25 ° C, V
IN
= V
OUT(nom)
+ 0.5 V, I
OUT
= 10 mA, V
EN
= 1.7 V, and C
OUT
= 0.1 µF, unless otherwisenoted
PSRR (RIPPLE REJECTION) vs FREQUENCY PSRR (RIPPLE REJECTION) vs V
IN
– V
OUT
Figure 16. Figure 17.
NOISE SPECTRAL DENSITY NOISE SPECTRAL DENSITYC
NR
= 0 µF C
NR
= 0.01 µF
Figure 18. Figure 19.
RMS NOISE VOLTAGE vs C
OUT
RMS NOISE VOLTAGE vs C
NR
Figure 20. Figure 21.
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Product Folder Link(s): TPS73201-Q1 TPS73215-Q1 TPS73216-Q1 TPS73218-Q1 TPS73225-Q1 TPS73230-Q1TPS73233-Q1 TPS73250-Q1
10µs/div
50mV/tick
50mV/tick
50mV/tick
50mA/tick
VIN = 3.8V COUT = 0µF
COUT = 1µF
COUT = 10µF
10mA
250mA
VOUT
VOUT
VOUT
IOUT
10µs/div
50mV/div
50mV/div
1V/div
VOUT
VOUT
VIN
IOUT = 250mA
5.5V
4.5V
dVIN
dt = 0.5V/µs
COUT = 0µF
COUT = 100µF
100µs/div
1V/div
1V/div
RL= 20Ω
COUT = 10µF
2V
0V
RL= 1kΩ
COUT = 0µF
RL= 20Ω
COUT = 1µF
VOUT
VEN
100µs/div
1V/div
1V/div
RL= 20Ω
COUT = 10µF
2V
0V
RL= 1kΩ
COUT = 0µF
RL= 20Ω
COUT = 1µF
VOUT
VEN
6
5
4
3
2
1
0
−1
−2
Volts
50ms/div
VIN
VOUT
10
1
0.1
0.01
IENABLE (nA)
−50 −25 0 25 50 75 100 125
Temperature (°C)
TPS73201-Q1 , , TPS73215-Q1 , , TPS73216-Q1TPS73218-Q1 , TPS73225-Q1 , TPS73230-Q1TPS73233-Q1 , TPS73250-Q1
www.ti.com
........................................................................................................................................................... SGLS303D – MAY 2005 – REVISED MARCH 2009
TYPICAL CHARACTERISTICS (continued)For all voltage versions at T
J
= 25 ° C, V
IN
= V
OUT(nom)
+ 0.5 V, I
OUT
= 10 mA, V
EN
= 1.7 V, and C
OUT
= 0.1 µF, unless otherwisenoted
TPS73233 TPS73233LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
Figure 22. Figure 23.
TPS73233 TPS73233TURN-ON RESPONSE TURN-OFF RESPONSE
Figure 24. Figure 25.
TPS73233
POWER UP / POWER DOWN I
ENABLE
vs TEMPERATURE
Figure 26. Figure 27.
Copyright © 2005 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TPS73201-Q1 TPS73215-Q1 TPS73216-Q1 TPS73218-Q1 TPS73225-Q1 TPS73230-Q1TPS73233-Q1 TPS73250-Q1
60
55
50
45
40
35
30
25
20
VN(rms)
CFB (F)
10p 100p 1n 10n
VOUT = 2.5V
COUT = 0µF
R1= 39.2kΩ
10Hz < Frequency < 100kHz
160
140
120
100
80
60
40
20
0
IFB (nA)
−50 −25 0 25 50 75 100 125
Temperature (_C)
5µs/div
100mV/div
100mV/div
VOUT
VOUT
VIN
4.5V
3.5V
COUT = 0µF
VOUT = 2.5V
CFB = 10nF
COUT = 10µF
10µs/div
100mV/div
100mV/div
VOUT
VOUT
IOUT
250mA
10mA
COUT = 0µF
CFB = 10nF
R1= 39.2kΩ
COUT = 10µF
TPS73201-Q1 , , TPS73215-Q1 , , TPS73216-Q1TPS73218-Q1 , TPS73225-Q1 , TPS73230-Q1TPS73233-Q1 , TPS73250-Q1
SGLS303D – MAY 2005 – REVISED MARCH 2009 ...........................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (continued)For all voltage versions at T
J
= 25 ° C, V
IN
= V
OUT(nom)
+ 0.5 V, I
OUT
= 10 mA, V
EN
= 1.7 V, and C
OUT
= 0.1 µF, unless otherwisenoted
TPS73201 TPS73201RMS NOISE VOLTAGE vs C
ADJ
I
FB
vs TEMPERATURE
Figure 28. Figure 29.
TPS73201 TPS73201LOAD TRANSIENT, ADJUSTABLE VERSION LINE TRANSIENT, ADJUSTABLE VERSION
Figure 30. Figure 31.
10 Submit Documentation Feedback Copyright © 2005 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS73201-Q1 TPS73215-Q1 TPS73216-Q1 TPS73218-Q1 TPS73225-Q1 TPS73230-Q1TPS73233-Q1 TPS73250-Q1
APPLICATION INFORMATION
TPS732xx
GNDEN NR
IN OUT
VIN VOUT
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient,
noise, or PSRR.
Optional bypass
capacitor to reduce
output noise.
TPS732xx
GNDEN FB
IN OUT
VIN VOUT
VOUT =×1.204
(R1+ R2)
R1CFB
R2
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient,
noise, or PSRR.
Optional capacitor
reduces output noise.
R2
Input and Output Capacitor Requirements
TPS73201-Q1 , , TPS73215-Q1 , , TPS73216-Q1TPS73218-Q1 , TPS73225-Q1 , TPS73230-Q1TPS73233-Q1 , TPS73250-Q1
www.ti.com
........................................................................................................................................................... SGLS303D – MAY 2005 – REVISED MARCH 2009
The TPS732xx belongs to a family of new generation LDO regulators that use an NMOS pass transistor toachieve ultra-low-dropout performance, reverse current blockage, and freedom from output capacitor constraints.These features, combined with low noise and an enable input, make the TPS732xx ideal for portableapplications. This regulator family offers a wide selection of fixed output voltage versions and an adjustableoutput version. All versions have thermal and over-current protection, including foldback current limit.
Figure 32 shows the basic circuit connections for the fixed voltage models. Figure 33 gives the connections forthe adjustable output version (TPS73201).
Figure 32. Typical Application Circuit for Fixed-Voltage Versions
Figure 33. Typical Application Circuit forAdjustable-Voltage Versions
R
1
and R
2
can be calculated for any output voltage using the formula shown in Figure 33 . Sample resistor valuesfor common output voltages are shown in Figure 3 . For best accuracy, make the parallel combination of R
1
andR
2
approximately 19 k Ω.
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1- µF to1- µF low ESR capacitor across the input supply near the regulator. This counteracts reactive input sources andimproves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary iflarge, fast rise-time load transients are anticipated or the device is located several inches from the power source.
The TPS732xx does not require an output capacitor for stability and has maximum phase margin with nocapacitor. It is designed to be stable for all available types and values of capacitors. In applications whereV
IN
– V
OUT
< 0.5 V and multiple low ESR capacitors are in parallel, ringing may occur when the product of C
OUTand total ESR drops below 50 nF. Total ESR includes all parasitic resistances, including capacitor ESR andboard, socket, and solder joint resistance. In most applications, the sum of capacitor ESR and trace resistancewill meet this requirement.
Copyright © 2005 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TPS73201-Q1 TPS73215-Q1 TPS73216-Q1 TPS73218-Q1 TPS73225-Q1 TPS73230-Q1TPS73233-Q1 TPS73250-Q1
Output Noise
VN+32mVRMS (R1)R2)
R2
+32mVRMS VOUT
VREF
(1)
VN(mVRMS)+27ǒmVRMS
VǓ VOUT(V)
(2)
VN(mVRMS)+8.5ǒmVRMS
VǓ VOUT(V)
(3)
Board Layout Recommendation to Improve PSRR and Noise Performance
Internal Current Limit
Shutdown
TPS73201-Q1 , , TPS73215-Q1 , , TPS73216-Q1TPS73218-Q1 , TPS73225-Q1 , TPS73230-Q1TPS73233-Q1 , TPS73250-Q1
SGLS303D – MAY 2005 – REVISED MARCH 2009 ...........................................................................................................................................................
www.ti.com
A precision band-gap reference is used to generate the internal reference voltage, V
REF
. This reference is thedominant noise source within the TPS732xx and it generates approximately 32 µV
RMS
(10 Hz to 100 kHz) at thereference output (NR). The regulator control loop gains up the reference noise with the same gain as thereference voltage, so that the noise voltage of the regulator is approximately given by:
Since the value of V
REF
is 1.2 V, this relationship reduces to:
for the case of no C
NR
.
An internal 27-k Ωresistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltagereference when an external noise reduction capacitor, C
NR
, is connected from NR to ground. For C
NR
= 10 nF,the total noise in the 10-Hz to 100-kHz bandwidth is reduced by a factor of ~3.2, giving the approximaterelationship:
for C
NR
= 10 nF.
This noise reduction effect is shown as RMS Noise Voltage vs C
NR
in the Typical Characteristics section.
The TPS73201 adjustable version does not have the noise-reduction pin available. However, connecting afeedback capacitor, C
FB
, from the output to the FB pin will reduce output noise and improve load transientperformance.
The TPS732xx uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate ofthe NMOS pass element above V
OUT
. The charge pump generates ~250 µV of switching noise at ~2 MHz;however, charge-pump noise contribution is negligible at the output of the regulator for most values of I
OUT
andC
OUT
.
To improve ac performance such as PSRR, output noise, and transient response, it is recommended that thePCB be designed with separate ground planes for V
IN
and V
OUT
, with each ground plane connected only at theGND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to theGND pin of the device.
The TPS732xx internal current limit helps protect the regulator during fault conditions. Foldback helps to protectthe regulator from damage during output short-circuit conditions by reducing current limit when V
OUT
drops below0.5 V. See Figure 12 in the Typical Characteristics section for a graph of I
OUT
vs V
OUT
.
The Enable pin is active high and is compatible with standard TTL-CMOS levels. V
EN
below 0.5 V (max) turnsthe regulator off and drops the ground pin current to approximately 10 nA. When shutdown capability is notrequired, the Enable pin can be connected to V
IN
. When a pullup resistor is used, and operation down to 1.8 V isrequired, use pullup resistor values below 50 k Ω.
12 Submit Documentation Feedback Copyright © 2005 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS73201-Q1 TPS73215-Q1 TPS73216-Q1 TPS73218-Q1 TPS73225-Q1 TPS73230-Q1TPS73233-Q1 TPS73250-Q1
Dropout Voltage
Transient Response
dVńdt +VOUT
COUT 80kW
(4)
dVńdt +VOUT
COUT 80kWø(R1)R2)
(5)
Reverse Current
TPS73201-Q1 , , TPS73215-Q1 , , TPS73216-Q1TPS73218-Q1 , TPS73225-Q1 , TPS73230-Q1TPS73233-Q1 , TPS73250-Q1
www.ti.com
........................................................................................................................................................... SGLS303D – MAY 2005 – REVISED MARCH 2009
The TPS732xx uses an NMOS pass transistor to achieve extremely low dropout. When (V
IN
– V
OUT
) is less thanthe dropout voltage (V
DO
), the NMOS pass device is in its linear region of operation and the input-to-outputresistance is the R
DS-ON
of the NMOS pass element.
For large step changes in load current, the TPS732xx requires a larger voltage drop from V
IN
to V
OUT
to avoiddegraded transient response. The boundary of this transient dropout region is approximately twice the dcdropout. Values of V
IN
– V
OUT
above this line ensure normal transient response.
Operating in the transient dropout region can cause an increase in recovery time. The time required to recoverfrom a load transient is a function of the magnitude of the change in load current rate, the rate of change in loadcurrent, and the available headroom (V
IN
to V
OUT
voltage drop). Under worst-case conditions [full-scaleinstantaneous load change with (V
IN
– V
OUT
) close to dc dropout levels], the TPS732xx can take a couple ofhundred microseconds to return to the specified regulation accuracy.
The low open-loop output impedance provided by the NMOS pass element in a voltage follower configurationallows operation without an output capacitor for many applications. As with any regulator, the addition of acapacitor (nominal value 1 µF) from the output pin to ground will reduce undershoot magnitude but increaseduration. In the adjustable version, the addition of a capacitor, C
FB
, from the output to the adjust pin will alsoimprove the transient response.
The TPS732xx does not have active pulldown when the output is over-voltage. This allows applications thatconnect higher voltage sources, such as alternate power supplies, to the output. This also results in an outputovershoot of several percent if the load current quickly drops to zero when a capacitor is connected to the output.The duration of overshoot can be reduced by adding a load resistor. The overshoot decays at a rate determinedby output capacitor C
OUT
and the internal/external load resistance. The rate of decay is given by:
(Fixed voltage version)
(Adjustable voltage version)
The NMOS pass element of the TPS732xx provides inherent protection against current flow from the output ofthe regulator to the input when the gate of the pass device is pulled low. To ensure that all charge is removedfrom the gate of the pass element, the enable pin must be driven low before the input voltage is removed. If thisis not done, the pass element may be left on due to stored charge on the gate.
After the enable pin is driven low, no bias voltage is needed on any pin for reverse current blocking. Note thatreverse current is specified as the current flowing out of the IN pin due to voltage applied on the OUT pin. Therewill be additional current flowing into the OUT pin due to the 80-k Ωinternal resistor divider to ground (seeFigure 2 and Figure 3 ).
For the TPS73201, reverse current may flow when V
FB
is more than 1 V above V
IN
.
Copyright © 2005 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS73201-Q1 TPS73215-Q1 TPS73216-Q1 TPS73218-Q1 TPS73225-Q1 TPS73230-Q1TPS73233-Q1 TPS73250-Q1
Thermal Protection
Power Dissipation
PD+(VIN *VOUT) IOUT
(6)
Package Mounting
TPS73201-Q1 , , TPS73215-Q1 , , TPS73216-Q1TPS73218-Q1 , TPS73225-Q1 , TPS73230-Q1TPS73233-Q1 , TPS73250-Q1
SGLS303D – MAY 2005 – REVISED MARCH 2009 ...........................................................................................................................................................
www.ti.com
Thermal protection disables the output when the junction temperature rises to approximately 160 ° C, allowing thedevice to cool. When the junction temperature cools to approximately 140 ° C, the output circuitry is againenabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protectioncircuit may cycle on and off. This limits the dissipation of the regulator, protecting it from damage due tooverheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequateheatsink. For reliable operation, junction temperature should be limited to 125 ° C maximum. To estimate themargin of safety in a complete design (including heatsink), increase the ambient temperature until the thermalprotection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection shouldtrigger at least 35 ° C above the maximum expected ambient condition of your application. This produces aworst-case junction temperature of 125 ° C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS732xx has been designed to protect against overload conditions. Itwas not intended to replace proper heatsinking. Continuously running the TPS732xx into thermal shutdown willdegrade device reliability.
The ability to remove heat from the die is different for each package type, presenting different considerations inthe PCB layout. The PCB area around the device that is free of other components moves the heat from thedevice to the ambient air. Performance data for JEDEC low- and high-K boards are shown in the PowerDissipation Ratings table. Using heavier copper will increase the effectiveness in removing heat from the device.The addition of plated through-holes to heat-dissipating layers will also improve the heat-sink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation is equal to the product of theoutput current times the voltage drop across the output pass element (V
IN
to V
OUT
):
Power dissipation can be minimized by using the lowest possible input voltage necessary to assure the requiredoutput voltage.
Solder pad footprint recommendations for the TPS732xx are presented in the Solder Pad Recommendations forSurface-Mount Devices (SBFA015 ) application bulletin, available from the Texas Instruments web site atwww.ti.com .
14 Submit Documentation Feedback Copyright © 2005 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS73201-Q1 TPS73215-Q1 TPS73216-Q1 TPS73218-Q1 TPS73225-Q1 TPS73230-Q1TPS73233-Q1 TPS73250-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 14-Sep-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS73201QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73201QDRBRQ1 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TPS73225QDBVRQ1 ACTIVE SOT-23 DBV 5 TBD Call TI Call TI
TPS73250QDCQRQ1 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS73201-Q1, TPS73225-Q1, TPS73250-Q1 :
PACKAGE OPTION ADDENDUM
www.ti.com 14-Sep-2012
Addendum-Page 2
•Catalog: TPS73201, TPS73225, TPS73250
•Enhanced Product: TPS73201-EP, TPS73225-EP, TPS73250-EP
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS73250QDCQRQ1 SOT-223 DCQ 6 2500 330.0 12.4 7.05 7.45 1.88 8.0 12.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS73250QDCQRQ1 SOT-223 DCQ 6 2500 358.0 335.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Jul-2012
Pack Materials-Page 2
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