1www.fairchildsemi.com
NM25C040 Rev. D.1
NM25C040 4K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
NM25C040
4K-Bit Serial CMOS EEPROM
(Serial Peripheral Interface (SPI) Synchronous Bus)
General Description
The NM25C040 is a 4096-bit CMOS EEPROM with an SPI
compatible serial interface. The NM25C040 is designed for data
storage in applications requiring both non-volatile memory and in-
system data updates. This EEPROM is well suited for applications
using the 68HC11 series of microcontrollers that support the SPI
interface for high speed communication with peripheral devices
via a serial bus to reduce pin count. The NM25C040 is imple-
mented in Fairchild Semiconductor’s floating gate CMOS process
that provides superior endurance and data retention.
The serial data transmission of this device requires four signal
lines to control the device operation: Chip Select (CS), Clock
(SCK), Data In (SI), and Serial Data Out (SO). All programming
cycles are completely self-timed and do not require an erase
before WRITE.
BLOCK WRITE protection is provided by programming the STA-
TUS REGISTER with one of four levels of write protection.
Additionally, separate WRITE enable and WRITE disable instruc-
tions are provided for data protection.
Hardware data protection is provided by the WP pin to protect
against inadvertent programming. The HOLD pin allows the serial
communication to be suspended without resetting the serial
sequence.
Block Diagram
March 1999
Features
■2.1 MHz clock rate @ 2.7V to 5.5V
■4096 bits organized as 512 x 8
■Multiple chips on the same 3-wire bus with separate chip
select lines
■Self-timed programming cycle
■Simultaneous programming of 1 to 4 bytes at a time
■Status register can be polled during programming to monitor
READY/BUSY
■Write Protect (WP) pin and write disable instruction for both
hardware and software write protection
■Block write protect feature to protect against accidental
writes
■Endurance: 1,000,000 data changes
■Data retention greater than 40 years
■Packages available: 8-pin DIP, 8-pin SO, or 8-pin TSSOP
DS012401-1
© 1999 Fairchild Semiconductor Corporation
Instruction
Decoder
Control Logic
and Clock
Generators
High Voltage
Generator
and
Program
Timer
Instruction
Register
Program
Enable
Data In/Out Register
8 Bits
Data Out
Buffer
Non-Volatile
Status Register
Decoder
1 of 512
Address
Counter/
Register
EEPROM Array
4096 Bits
(512 x 8)
Read/Write Amps
CS
HOLD
SCK
V
CC
V
SS
V
PP
WP
SI
SO
2www.fairchildsemi.com
NM25C040 Rev. D.1
NM25C040 4K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
Connection Diagram
Dual-In-Line Package (N), SO Package (M8),
and TSSOP Package (MT8)
Top View
See Package Number N08E (N), M08A (M8), and MTC08 (MT8)
Pin Names
CS Chip Select Input
SO Serial Data Output
WP Write Protect
VSS Ground
SI Serial Data Input
SCK Serial Clock Input
HOLD Suspends Serial Data
VCC Power Supply
Ordering Information
NM 25 C XX LZ E XX Letter Description
Package N 8-pin DIP
M8 8-pin SO
MT8 8-pin TSSOP
Temp. Range None 0 to 70°C
V -40 to +125°C
E -40 to +85°C
Voltage Operating Range Blank 4.5V to 5.5V
L 2.7V to 4.5V
LZ 2.7V to 4.5V and
<1µA Standby Current
Density/Mode 040 4K, mode 0
C CMOS technology
W Total Array write protect
Interface 25 SPI
NM Fairchild Nonvolatile
Memory Prefix
CS
SO
WP
V
SS
V
CC
HOLD
SCK
SI
8
7
6
5
1
2
3
4
NM25C040
DS012401-2
3www.fairchildsemi.com
NM25C040 Rev. D.1
NM25C040 4K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
Standard Voltage 4.5 ≤ VCC ≤ 5.5V Specifications
Absolute Maximum Ratings (Note 1)
Ambient Storage Temperature -65°C to +150°C
All Input or Output Voltage with
Respect to Ground +6.5V to -0.3V
Lead Temp. (Soldering, 10 sec.) +300°C
ESD Rating 2000V
Operating Conditions
Ambient Operating Temperature
NM25C040 0°C to +70°C
NM25C040E -40°C to +85°C
NM25C040V -40°C to +125°C
Power Supply (VCC) 4.5V to 5.5V
DC and AC Electrical Characteristics 4.5V ≤ VCC ≤ 5.5V (unless otherwise specified)
Symbol Parameter Conditions Min Max Units
ICC Operating Current CS = VIL 3mA
ICCSB Standby Current CS = VCC 50 µA
IIL Input Leakage VIN = 0 to VCC -1 +1 µA
IOL Output Leakage VOUT = GND to VCC -1 +1 µA
VIL CMOS Input Low Voltage -0.3 VCC * 0.3 V
VIH CMOS Input High Voltage 0.7 * VCC VCC + 0.3 V
VOL Output Low Voltage IOL = 1.6 mA 0.4 V
VOH Output High Voltage IOH = -0.8 mA VCC - 0.8 V
fOP SCK Frequency 2.1 MHz
tRI Input Rise Time 2.0 µs
tFI Input Fall Time 2.0 µs
tCLH Clock High Time (Note 2) 190 ns
tCLL Clock Low Time (Note 2) 190 ns
tCSH Min CS High Time (Note 3) 240 ns
tCSS CS Setup Time 240 ns
tDIS Data Setup Time 100 ns
tHDS HOLD Setup Time 90 ns
tCSN CS Hold Time 240 ns
tDIN Data Hold Time 100 ns
tHDN HOLD Hold Time 90 ns
tPD Output Delay CL = 200 pF 240 ns
tDH Output Hold Time 0 ns
tLZ HOLD to Output Low Z 100 ns
tDF Output Disable Time CL = 200 pF 240 ns
tHZ HOLD to Output High Z 100 ns
tWP Write Cycle Time 1–4 Bytes 10 ms
Capacitance TA = 25°C, f = 2.1/1 MHz (Note 4)
Symbol Test Typ Max Units
COUT Output Capacitance 3 8 pF
CIN Input Capacitance 2 6 pF
AC Test Conditions
Output Load CL = 200 pF
Input Pulse Levels 0.1 * VCC – 0.9 * VCC
Timing Measurement Reference Level 0.3 * VCC - .07 * VCC
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 2: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For
example, if the 2.1MHz period = 476ns and tCLH = 190ns, tCLL must be 286ns.
Note 3: CS must be brought high for a minimum of tCSH between consecutive instruction cycles.
Note 4: This parameter is periodically sampled and not 100% tested.
4www.fairchildsemi.com
NM25C040 Rev. D.1
NM25C040 4K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
Low Voltage 2.7V ≤ VCC ≤ 4.5V Specifications
Absolute Maximum Ratings (Note 5)
Ambient Storage Temperature -65°C to +150°C
All Input or Output Voltage with
Respect to Ground +6.5V to -0.3V
Lead Temp. (Soldering, 10 sec.) +300°C
ESD Rating 2000V
Operating Conditions
Ambient Operating Temperature
NM25C040L/LZ 0°C to +70°C
NM25C040LE/LZE -40°C to +85°C
NM25C040LV -40°C to +125°C
Power Supply (VCC) 2.7V–4.5V
DC and AC Electrical Characteristics 2.7V ≤ VCC ≤ 4.5V (unless otherwise specified)
25C040L/LE 25C040LV
25C040LZ/ZE
Symbol Parameter Part Conditions Min. Max. Min Max Units
ICC Operating Current CS = VIL 33mA
ICCSB Standby Current L CS = VCC 10 10 µA
LZ 1 N/A µA
IIL Input Leakage VIN = 0 to VCC -1 1 -1 1 µA
IOL Output Leakage VOUT = GND to VCC -1 1 -1 1 µA
VIL Input Low Voltage -0.3 VCC * 0.3 -0.3 VCC * 0.3 V
VIH Input High Voltage VCC * 0.7 VCC + 0.3 VCC * 0.7 VCC + 0.3 V
VOL Output Low Voltage IOL = 0.8 mA 0.4 0.4 V
VOH Output High Voltage IOH = –0.8 mA VCC - 0.8 VCC - 0.8 V
fOP SCK Frequency 1.0 1.0 MHz
tRI Input Rise Time 2.0 2.0 µs
tFI Input Fall Time 2.0 2.0 µs
tCLH Clock High Time (Note 6) 410 410 ns
tCLL Clock Low Time (Note 6) 410 410 ns
tCSH Min. CS High Time (Note 7) 500 500 ns
tCSS CS Setup Time 500 500 ns
tDIS Data Setup Time 100 100 ns
tHDS HOLD Setup Time 240 240 ns
tCSN CS Hold Time 500 500 ns
tDIN Data Hold Time 100 100 ns
tHDN HOLD Hold Time 240 240 ns
tPD Output Delay CL = 200 pF 500 500 ns
tDH Output Hold Time 0 0 ns
tLZ HOLD Output Low Z 240 240 ns
tDF Output Disable Time CL = 200 pF 500 500 ns
tHZ HOLD to Output Hi Z 240 240 ns
tWP Write Cycle Time 1-4 Bytes 15 15 ms
Capacitance TA = 25°C, f = 2.1/1 MHz (Note 8)
Symbol Test Typ Max Units
COUT Output Capacitance 3 8 pF
CIN Input Capacitance 2 6 pF
AC Test Conditions
Output Load CL = 200pF
Input Pulse Levels 0.1 * VCC - 0.9 * VCC
Timing Measurement Reference Level 0.3 * VCC - 0.7 * VCC
Note 5: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Note 6: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For example,
if the 2.1MHz period = 476ns and tCLH = 190ns, tCLL must be 286ns.
Note 7: CS must be brought high for a minimum of tCSH between consecutive instruction cycles.
Note 8: This parameter is periodically sampled and not 100% tested.
5www.fairchildsemi.com
NM25C040 Rev. D.1
NM25C040 4K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
AC Test Conditions (Continued)
FIGURE 1. Synchronous Data Timing Diagram
SI
SO
SCK
CS
DATA OUT (MOSI)
DATA IN (MISO)
SERIAL CLOCK (CLK)
SS0
SS1
SS2
SS3
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
SPI
CHIP
SELECTION
MASTER MCU NM25C040
DS012401-3
DS012401-4
FIGURE 3. SPI Serial Interface
,
,,
CS
SCK
SI
SO
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
tCSS
tCSH
tCSN
tDIS
tPD tDH tDF
tDIN
tCLH tCLL
SCK
HOLD
SO
tHZ
tHDN
tHDS
tHDN
tHDS
tLZ
FIGURE 2. HOLD Timing
DS012401-6
6www.fairchildsemi.com
NM25C040 Rev. D.1
NM25C040 4K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
Functional Description
TABLE 1. Instruction Set
Instruction Instruction Operation
Name Opcode
WREN 00000110 Set Write Enable Latch
WRDI 00000100 Reset Write Enable Latch
RDSR 00000101 Read Status Register
WRSR 00000001 Write Status Register
READ 0000A011 Read Data from Memory
Array
WRITE 0000A010 Write Data to Memory Array
Note: As the NM25C040 requires 9 address bits (4,096 ÷ 8 = 512 bytes = 29), the
9th bit (for R/W instructions) is inputted in the Instruction Set Byte in bit I3. This
convention only applies to 4K SPI protocol.
MASTER: The device that generates the serial clock is desig-
nated as the master. The NM25C040 can never function as a
master.
SLAVE: The NM25C040 always operates as a slave as the serial
clock pin is always an input.
TRANSMITTER/RECEIVER: The NM25C040 has separate pins
for data transmission (SO) and reception (SI).
MSB: The Most Significant Bit is the first bit transmitted and
received.
CHIP SELECT: The chip is selected when pin CS is low. When the
chip is
not
selected, data will not be accepted from pin SI, and the
output pin SO is in high impedance.
SERIAL OP-CODE: The first byte transmitted after the chip is
selected with CS going low contains the op-code that defines the
operation to be performed.
PROTOCOL: When connected to the SPI port of a 68HC11
microcontroller, the NM25C040 accepts a clock phase of 0 and a
clock polarity of 0. The SPI protocol for this device defines the byte
transmitted on the SI and SO data lines for proper chip operation.
See Figure 4.
HOLD: The HOLD pin is used in conjunction with the CS to select
the device. Once the device is selected and a serial sequence is
underway, HOLD may be forced low to suspend further serial
communication with the device without resetting the serial se-
quence. Note that HOLD must be brought low while the SCK pin
is low. The device must remain selected during this sequence. To
resume serial communication HOLD is brought high while the
SCK pin is low. The SO pin is at a high impedance state during
HOLD.
INVALID OP-CODE: After an invalid code is received, no data is
shifted into the NM25C040, and the SO data output pin remains
high impedance until a new CS falling edge reinitializes the serial
communication. See Figure 5.
FIGURE 5. Invalid Op-Code
CS
SI
SO
INVALID CODE
DS012401-7
…
…
…
CS
SCK
SI
SO
Bit 7 Bit 6 Bit 0
Bit 1Bit 7 Bit 0
DS012401-5
FIGURE 4. SPI Protocol
Data is clocked in on the positive SCK edge and out on the
negative SCK edge.
7www.fairchildsemi.com
NM25C040 Rev. D.1
NM25C040 4K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
Functional Description (Continued)
READ SEQUENCE: Reading the memory via the serial SPI link
requires the following sequence. The CS line is pulled low to select
the device. The READ op-code (which includes A8) is transmitted
on the SI line followed by the byte address (A7–A0) to be read.
After this is done, data on the SI line becomes don’t care. The data
(D7–D0) at the address specified is then shifted out on the SO line.
If only one byte is to be read, the CS line can be pulled back to the
high level. It is possible to continue the READ sequence as the
byte adress is automatically incremented and data will continue to
be shifted out. When the highest address is reached (1FF), the
address counter rolls over to lowest address (000) allowing the
entire memory to be read in one continuous READ cycle. See
Figure 6.
Level Status Register Bits Array
Address
BP1 BP0 Protected
0 0 0 None
1 0 1 180-1FF
2 1 0 100-1FF
3 1 1 000-1FF
WRITE ENABLE (WREN): When VCC is applied to the chip, it
“powers up” in the write disable state. Therefore, all programming
modes must be preceded by a WRITE ENABLE (WREN) instruc-
tion. At the completion of a WRITE or WRSR cycle the device is
automatically returned to the write disable state. Note that a
WRITE DISABLE (WRDI) instruction will also return the device to
the write disable state. See Figure 8.
FIGURE 8. Write Enable
CS
SI
SO
WREN Op-Code
DS012401-10
WRITE DISABLE (WRDI): To protect against accidental data
disturbance the WRITE DISABLE (WRDI) instruction disables all
programming modes. See Figure 9.
FIGURE 9. Write Disable
CS
SI
SO
WRDI Op-Code
DS012401-11
TABLE 3. Block Write Protection Levels
FIGURE 6. Read Sequence
FIGURE 7. Read Status
CS
SI
SO
Read
Op-Code Byte
Addr.
Data
nData
n+1 Data
n+2 Data
n+3
CS
SI
SO
RDSR
Op-Code
SR Data
MSB…LSB
DS012401-8
DS012401-9
READ STATUS REGISTER (RDSR) : The Read Status Register
(RDSR) instruction provides access to the status register is used
to interrogate the READY/BUSY and WRITE ENABLE status of
the chip. Two non-volatile status register bits are used to select
one of four levels of BLOCK WRITE PROTECTION. The status
register format is shown in Table 2.
TABLE 2. Status Register Format
Bit Bit Bit Bit Bit Bit Bit Bit
76543210
X X X X BP1 BP0 WEN RDY
X = Don't Care.
Status register Bit 0 = 0 (RDY) indicates that the device is READY;
Bit 0 = 1 indicates that a program cycle is in progress. Bit 1 = 0
(WEN) indicates that the device is not WRITE ENABLED; Bit 1 =
1 indicates that the device is WRITE ENABLED. Non-volatile
status register Bits 2 and 3 (BP0 and BP1) indicate the level of
BLOCK WRITE PROTECTION selected. The block write protec-
tion levels and corresponding status register control bits are
shown in Table 3. Note that if a RDSR instruction is executed
during a programming cycle only the RDY bit is valid. All
other bits are 1s. See Figure 7.
WRITE SEQUENCE: To program the device, the WRITE PRO-
TECT (WP) pin must be held high and two separate instructions
must be executed. The chip must first be write enabled via the
WRITE ENABLE instruction and then a WRITE instruction must
be executed. Moreover, the address of the memory location(s) to
be programmed must be outside the protected address field
selected by the Block Write Protection Level. See Table 3.
A WRITE command requires the following sequence. The CS line
is pulled low to select the device, then the WRITE op-code (which
includes A8) is transmitted on the SI line followed by the high order
address byte (A10-A8) and the byte address(A7–A0) and the
corresponding data (D7-D0) to be written. Programming will start
after the CS pin is forced back to a high level. Note that the LOW
to HIGH transition of the CS pin must occur during the SCK low time
immediately after clocking in the D0 data bit. See Figure 10.
8www.fairchildsemi.com
NM25C040 Rev. D.1
NM25C040 4K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
SCK
SI
SO
CS
D0D1D2
DS012401-12
Functional Description (Continued)
FIGURE 10. Write Sequence
The READY/BUSY status of the device can be determined by
executing a READ STATUS REGISTER (RDSR) instruction. Bit 0
= 1 indicates that the WRITE cycle is still in progress and Bit 0 =
0 indicates that the WRITE cycle has ended. During the WRITE
programming cycle (Bit 0 = 1) only the READ STATUS REGIS-
TER instruction is enabled.
The NM25C040 is capable of a 4 byte PAGE WRITE operation.
After receipt of each byte of data the two low order address bits are
internally incremented by one. The seven high order bits of the
address will remain constant. If the master should transmit more
than 4 bytes of data, the address counter will “roll over,” and the
previously loaded data will be reloaded. See Figure 11.
The WRSR command requires the following sequence. The CS
line is pulled low to select the device and then the WRSR op-code
is transmitted on the SI line followed by the data to be pro-
grammed. See Figure 12.
CS
SI
SO
Write
Op-Code Byte
Addr (n) Data
(n) Data
(n + 1) Data
(n + 2) Data
(n + 3)
CS
SI
SO
WRSR
Op-Code SR Data
xxxxBP1BP0xx
DS012401-13
DS012401-14
FIGURE 11. 4 Byte Page Write
FIGURE 12. Write Status Register
BP0
SCK
SI
SO
CS
DS012401-15
FIGURE 13. Start WRSR Condition
At the completion of a WRITE cycle the device is automatically
returned to the write disable state.
If the device is not WRITE enabled, the device will ignore the
WRITE instruction and return to the standby state when CS is
forced high. A new CS falling edge is required to re-initialize the
serial communication.
WRITE STATUS REGISTER (WRSR): The WRITE STATUS
REGISTER (WRSR) instruction is used to program the non-
volatile status register Bits 2 and 3 (BP0 and BP1). The WRITE
PROTECT (WP) pin must be held high and two separate instruc-
tions must be executed. The chip must first be write enabled via
the WRITE ENABLE instruction and then a WRSR instruction
must be executed.
Note that the first four bits are don’t care bits followed by BP1 and
BP0 then two additional don’t care bits. Programming will start
after the CS pin is forced back to a high level. As in the WRITE
instruction the LOW to HIGH transition of the CS pin must occur
during the SCK low time immediately after clocking in the last don’t
care bit. See Figure 13.
The READY/BUSY status of the device can be determined by
executing a READ STATUS REGISTER (RDSR) instruction. Bit 0
= 1 indicates that the WRSR cycle is still in progress and Bit 0 =
0 indicates that the WRSR cycle has ended.
At the completion of a WRITE cycle the device is automatically
returned to the write disable state.
9www.fairchildsemi.com
NM25C040 Rev. D.1
NM25C040 4K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
Molded Small Out-Line Package (M8)
Package Number M08A
Molded Dual-In-Line Package (N)
Package Number N08E
1234
8765
0.189 - 0.197
(4.800 - 5.004)
0.228 - 0.244
(5.791 - 6.198) 0.010
(0.254)Max.
Lead #1
IDENT
Seating
Plane
0.004 - 0.010
(0.102 - 0.254)
0.014 - 0.020
(0.356 - 0.508)
0.014
(0.356)
Typ.
0.053 - 0.069
(1.346 - 1.753)
0.050
(1.270)
Typ Typ
0.008
(0.203)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
8° Max, Typ.
All leads
0.150 - 0.157
(3.810 - 3.988)
0.008 - 0.010
(0.203 - 0.254)
Typ. all leads
0.04
(0.102)
All lead tips
0.010 - 0.020
(0.254 - 0.508)x 45°
30° Typ.
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)
0.092
(2.337)DIA
+
1234
8765
0.250 - 0.005
(6.35 ± 0.127)
87
0.032 ± 0.005
(0.813 ± 0.127)
Pin #1
Option 2
RAD
1
0.145 - 0.200
(3.683 - 5.080)
0.130 ± 0.005
(3.302 ± 0.127)
0.125 - 0.140
(3.175 - 3.556) 0.020
(0.508)
Min
0.018 ± 0.003
(0.457 ± 0.076)
90° ± 4°
Typ
0.100 ± 0.010
(2.540 ± 0.254)
0.040
(1.016) 0.039
(0.991)
Typ.
20° ± 1°
0.065
(1.651)
0.050
(1.270)
0.060
(1.524)
Pin #1 IDENT
Option 1
0.280 MIN
0.300 - 0.320
(7.62 - 8.128)
0.030
(0.762)MAX
0.125
(3.175)
DIA
NOM
0.009 - 0.015
(0.229 - 0.381)
0.045 ± 0.015
(1.143 ± 0.381)
0.325 +0.040
-0.015
8.255 +1.016
-0.381
95° ± 5°
0.090
(2.286)
(7.112)
IDENT
10 www.fairchildsemi.com
NM25C040 Rev. D.1
NM25C040 4K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
8-Pin Molded TSSOP, JEDEC (MT8)
Package Number MTC08
0.114 - 0.122
(2.90 - 3.10)
0.123 - 0.128
(3.13 - 3.30)
0.246 - 0.256
(6.25 - 6.50)
14
85
0.169 - 0.177
(4.30 - 4.50)
(7.72) Typ
(4.16) Typ
(1.78) Typ
(0.42) Typ (0.65) Typ
0.002 - 0.006
(0.05 - 0.15)
0.0256 (0.65)
Typ.
Max
0.0433
(1.1)
0.0075 - 0.0098
(0.19 - 0.30)
Pin #1 IDENT
0.0035 - 0.0079
0°-8°
0.020 - 0.028
[0.50 - 0.70]
0.0075 - 0.0098
[0.19 - 0.25]
Seating
plane
Gage
plane
See detail A
Land pattern recommendation
DETAIL A
Typ. Scale: 40X
Physical Dimensions inches (millimeters) unless otherwise noted
Note: Metal mask option for 16-byte page size.
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably ex-
pected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor
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