UT54ACS162245SUCC - Aeroflex / Colorado Springs

UT54ACS162245S

RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose

Low Voltage Transceiver

Datasheet

August 2006

FEATURES

• Voltage translation

- 3.3V bus to 2.5V bus

- 2.5V bus to 3.3V bus

• Cold sparing all pins

• 0.25µ Commercial RadHardTM CMOS

- Total dose: 300Krad(Si) and 1Mrad(Si)

- Single Event Latchup immune

• High speed, low power consumption

• Schmitt trigger inputs to filter noisy signals

• Cold and Warm Spare - all outputs

• Available QML Q or V processes

• Standard Microcircuit Drawing 5962-02543

• Package:

- 48-lead flatpack, 25 mil pitch (.390 x .64 0 )

DESCRIPTION

The 16-bit wide UT54ACS162245S MultiPurpose low voltage

transceiver is built using Aeroflex UTMC’s Commercial

RadHardTM epitaxial CMOS technology and is ideal for space

applications. This high speed, low power UT54ACS162245S

low voltage transceiver is designed to perform multiple func-

tions including: asynchro nou s two-way commun icatio n,

Schmitt input buffering, voltage translation, warm and cold spar-

ing. With VDD equal to zero volts, the UT54ACS162245S out-

puts and inputs present a minimum impedance of 1MΩ making

it ideal for "cold spare" applications. Balanced outputs and low

"on" output impedance make the UT54ACS162245S well suited

for driving high capacitance loads and low impedance back-

planes. The UT54ACS162245S enables system designers to in-

terface 2.5 volt CMOS compatible components with 3.3 volt

CMOS components. For voltage translation, the A port interfac-

es with the 2.5 volt bus; the B port interfaces with the 3.3 volt

bus. The direction control (DIRx) controls the direction of data

flow. The output enable (OEx) overrides the direction control

and disables both ports. These signals can be driven from either

port A or B. The direction and output enable controls op erate

these devices as either two independent 8-bit transceivers or one

16-bit transceiver.

LOGIC SYMBOL

PIN DESCRIPTION

Pin Names Description

OEx Output Enable Input (Active Low)

DIRx Direction Control Inputs

xAx Side A Inputs or 3-State Outputs (2.5V Port)

xBx Side B Inputs or 3-State Outputs (3.3V Port)

(48)

OE1

(47)

1A1

(46)

1A2 (44)

(2) 1B1

(5)

(3) 1B2

1A3 (43)

1A4 (41)

1A5 (40)

1A6

1B3

(9) 1B6

(8) 1B5

(6) 1B4

(38)

1A7 (37)

1A8 (12) 1B8

(11) 1B7

(1)

DIR1 1EN1 (BA)

1EN2 (AB)

11 12

(25)

OE2G1 (24) DIR2

21 22

(36)

2A1 2B1

(13)

(35)

2A2 (33)

2A3 (32)

2A4 (30)

2A5 (29)

2A6 (27)

2A7 (26)

2A8

(16) 2B2

2B3

(20) 2B6

(19) 2B5

(17) 2B4

(23) 2B8

(22) 2B7

(14)

2EN1 (BA)

2EN2 (AB)

PINOUTS

POWER TABLE

When VDD2 is at 2.5 volts, either 2.5 or 3.3 volts CMOS logic

levels can be applied to all control input s. For proper operation

connect power to all VDD and ground all VSS pins (i.e., no float-

ing VDD or VSS input pins). Tie unused inputs to VSS. Always

insure VDD1 > VDD2 during operation of the part.

FUNCTION TABLE

COLD/WARM SPARE FUNCTION

The device will place all outputs into a high-impedance state if

either VDD supply is taken to zero volts (IWS, warm spare), or

if both VDD supplies are set to zero volts (ICS, cold spare).

DEVICE POWER UP FUNCTION

The device will place all outputs into a high-impedance during

power-up. The high impedance state is maintained for a time

period approximately equal to the rise time of VDD1.

Port B Port A OPERATION

3.3 Volts 2.5 Volts Voltage Translator

3.3 Volts 3.3 Volts Non Translating

2.5 Volts 2.5 Volts Non Translating

DIR1

1B1

1B2

1B3

1B4

VDD1

OE1

1A1

1A2

1A3

VDD2

841

1B5 1A5

1A4

940

1B6 1A6

10 39

48-Lead Flatpack

Top View

1B7

1B8

2B1

2B2

2B3

2B4

VDD1

2B5

2B6

2B7

2B8

DIR2

1A7

1A8

2A1

2A2

2A4

31 VDD2

2A3

30 2A5

29 2A6

28 V

27 2A7

26 2A8

25 OE2

ENABLE

OExDIRECTION

DIRx OPERATION

L L B Data To A Bus

L H A Data To B Bus

HX Isolation

LOGIC DIAGRAM

1A1

1A2

1A3

1A4

1A5

1A6

1A7

1A8

DIR1 (1)

(47)

(48)

(2)

(46)

(3)

(44)

(5)

(43)

(6)

(41)

(8)

(40)

(9)

(38)

(11)

(37)

(12)

1B1

1B2

1B3

1B6

1B5

1B4

1B8

1B7

OE1

2A1

2A2

2A3

2A4

2A5

2A6

2A7

2A8

DIR2 (24)

(36)

(25)

(13)

(35)

(14)

(33)

(16)

(32)

(17)

(30)

(19)

(29)

(20)

(27)

(22)

(26)

(23)

2B1

2B2

2B3

2B6

2B5

2B4

2B8

2B7

OE2

2.5V PORT

3.3 V PORT

2.5V PORT

3.3 V PORT

RADIATION HARDNESS SPECIFICATIONS 1

Notes:

1. Logic will not latchup during radiation exposure within the limits defined in the table.

2. Not tested, inherent to CMOS technology.

ABSOLUTE MAXIMUM RATINGS1

Note:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only , functional operation of the device at

these or any other conditions beyond limits in dicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability and performance.

2. For Cold Spare mode (V

DD1

=VSS, V

DD2

=VSS), V

I/O

may be -0.3V to the maximum recommended operating level of V

DD1

+0.3V.

3. Maximum junction temperature may be increased to +175

C during burn-in and life test.

DUAL SUPPLY OPERATING CONDITIONS

PARAMETER LIMIT UNITS

Total Dose 1.0E5 rad(Si)

SEL Latchup >113 MeV-cm2/mg

Neutron Fluence (Note 2) 1.0E14 n/cm2

SYMBOL PARAMETER LIMIT (Mil only) UNITS

VI/O (Note 2) Voltage any pin -.3 to VDD1 +.3 V

VDD1 Supply voltage -0.3 to 4.0 V

VDD2 Supply voltage -0.3 to 4.0 V

TSTG Storage Temperature range -65 to +150 °C

TJ (Note 3) Maximum junction tem perature +150 °C

ΘJC Thermal resistance junction to case 20 °C/W

IIDC input current ±10 mA

PDMaximum power dissipation 1 W

SYMBOL PARAMETER LIMIT UNITS

VDD1 Supply voltag e 2.3 to 3.6 V

VDD2 Supply voltag e 2.3 to 3.6 V

VIN Input voltage any pin 0 to VDD1 V

TCTemperature range -55 to + 125 °C

DC ELECTRICAL CHARACTERISTICS 1

( -55°C < TC < +125°C)

SYMBOL PARAMETER CONDITION MIN MAX UNIT

VT+Schmitt Trigger, positive going threshold2 VDD from 2.3 to 3.6 .7VDD V

VT-Schmitt Trigger , negative going threshold2VDD from 2.3 to 3.6 .3VDD V

VH1 Schmitt Trigger range of hysteresis9 V

DD from 3.0 to 3.6 0.5 V

VH2 Schmitt Trigger range of hysteresis9 VDD from 2.3 to 2.7 0.4 V

IIN Input leakage current9 VDD from 2.7 to 3.6

VIN = VDD or VSS

-1 3 µA

IOZ Three-state output leakage current9 VDD from 2.7 to 3.6

VIN = VDD or VSS

-1 3 µA

ICS Cold sparing input leakage current3,11 VIN = 3.6

VDD = VSS

-5 5 µA

IWS Warm sparing input leakage current3,11 VIN = VSS or VDD, VDD1 = 0,

VDD2 = VDD or VDD1 = VDD, VDD2 = 0

-5 5 µA

IOS1 Short-circuit output current 5, 10 VO = VDD or VSS

VDD from 3.0 to 3.6

-200 200 mA

IOS2 Short-circuit output current 5, 10 VO = VDD or VSS

VDD from 2.3 to 2.7

-100 100 mA

VOL1 Low-level output voltage9 IOL= 8mA

IOL= 100µA

VDD = 3.0

0.4

0.2

VOL2 Low-level output voltage9 IOL= 8mA

IOL= 100µA

VDD = 2.3

0.4

0.2

VOH1 High-level output voltage9IOH= -8mA

IOH= -100µA

VDD = 3.0

VDD - 0.7

VDD - 0.2

VOH2 High-level output voltage9IOH= -8mA

IOH= -100µA

VDD = 2.3

VDD - 0.7

VDD - 0.2

DC ELECTRICAL CHARACTERISTICS 1

( -55°C < TC < +125°C)

Notes:

1. All specifications valid for radiation dose ≤ 1E5 rad(Si) per MIL-STD-883, Method 1019.

2. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V

= V

(min) + 20%, - 0%; V

= V

(max) + 0%, -

50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specifi ed range, bu t are

guaranteed to V

(min) and V

(max).

3. All combinations of OEx and D IR x

4. Guaranteed by characterization.

5. Not more than one output may be shorted at a time for maximum duration of one second.

6. Power does not include po wer co ntr ibu tio n of any C MOS ou tp ut sink curr ent.

7. Power dissipation specified per switching output.

8.Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V

at frequency of 1MHz and a signal amplitude of 50mV rms maximum.

9.Guaranteed; tested on a sample of pins per device.

10. Supplied as a design limit, but not guaranteed or tested.

11. Zero Volts is defined as 0.0 Volts +/- 0.25Volts.

12. V

DD1

and V

DD2

Voltage rise is monotonic.

13. Rise time measured from V

@ Zero Volts to V

@ greater than 2.3 V.

SYMBOL PARAMETER CONDITION MIN MAX UNIT

Ptotal1 Power dissipatio n 4,6,7 CL = 40pF 6.2 mW/

MHz

VDD from 3.0V to 3.6V

Ptotal2 Power dissipatio n 4,6,7 CL = 40pF 3MHz

VDD from 2.3V to 2.7V

IDD Standby Supply Current

VDD1 or VDD2

VIN = VDD or VSS

VDD = 3.6V

OE = VDD

Pre-Rad 25oC10 µA

OE = VDD

Pre-Rad -55oC to +125oC475 µA

OE = VDD

Post-Rad 25oC15 mA

CIN Input Capacitance8f = 1MHz @ 0V 15 pF

VDD from 2.3V to 3.6V

Cout Output Capacitance8f = 1MHz @ 0V 15 pF

VDD from 2.3V to 3.6V

POR VDD1 & VDD2 Power-On4,13 VDD1 or VDD2 Zero Volt Offset 250 mV

VDD1 and VDD2 Rise-Time12 500 mS

AC ELECTRICAL CHARACTERISTICS1 (Port B = 3.3 Volt, Port A = 2.5 Volt)

(VDD1 = 3.0V to 3.6V; VDD2 = 2.3V to 2.7V, -55°C < TC < +125°C)

Notes:

1. All specifications valid for radiation dose ≤ 1E5 rad(Si) per MIL-STD-883, Method 1019.

2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested

3. Output skew is defined as a comparison of any two output transitions high-to-low vs. high-to-low and low-to-high vs. low-to-high

SYMBOL PARAMETER MINIMUM MAXIMUM UNIT

tPLH Propagation delay Data to Bus 2 10 ns

tPHL Propagation delay Data to Bus 2 10 ns

tPZL Output enable time OEx to Bus 2 12 ns

tPZH Output enable time OEx to Bus 2 12 ns

tPLZ Output disable time OEx to Bus high impedance 2 15 ns

tPHZ Output disable time OEx to Bus high impedance 2 15 ns

tPZL2Output enable time DIRx to Bus 2 12 ns

tPZH2Output enable time DIRx to Bus 2 12 ns

tPLZ2Output disable time DIRx to Bus high impedance 2 15 ns

tPHZ2Output disable time DIRx to Bus high impedance 2 15 ns

tSLH3

tSHL3

Skew between outputs (40pF +/- 10 pF on each output)

900

tPLZ

tPZH

tPZL

tPHL

tPHZ

Propagation Delay

Input

Output

VDD

VDD/2

tPLH VOH

VOL

VDD/2

Control Input

3.3V Output

Normally Low

Enable Disable Times

3.3V Output

Normally High

VDD

VDD/2

.8VDD

.2VDD

VDD/2+0.2

VDD/2-0.2 .2VDD + .2V

.8VDD - .2V

tPLZ

tPZH

tPZL

tPHZ

2.5V Output

Normally Low

2.5V Output

Normally High

VDD/2

.7VDD

.2VDD

VDD/2+0.2

VDD/2-0.2 .2VDD + .2V

.7VDD - .2V

AC ELECTRICAL CHARACTERISTICS1 (Port A = Port B, 3.3 Volt Operation)

(VDD1 = 3.0 to 3.6V; VDD2 = 3.0V to 3.6V, -55°C < TC < +125°C)

Notes:

1. All specifications val id fo r radia tion do se ≤ 1E5 rad(Si) per MIL-STD-883, Method 1019.

2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested

3. Output skew is defined as a comparison of any two output transitions high-to-low vs. high-to-low and low-to-high vs. low-to-high

SYMBOL PARAMETER MINIMUM MAXIMUM UNIT

tPLH Propagation delay Data to Bus 2 7.5 ns

tPHL Propagation delay Data to Bus 2 7.5 ns

tPZL Output enable time OEx to Bus 2 10 ns

tPZH Output enable time OEx to Bus 2 10 ns

tPLZ Output disable time OEx to Bus high impedance 2 12 ns

tPHZ Output disable time OEx to Bus high impedance 2 12 ns

tPZL2Output enable time DIRx to Bus 2 10 ns

tPZH2Output enable time DIRx to Bus 2 10 ns

tPLZ2Output disable time DIRx to Bus high impedance 2 12 ns

tPHZ2Output disable time DIRx to Bus high impedance 2 12 ns

tSLH3

tSHL3

Skew between outputs (40pF +/- 10 pF on each output)

900

tPLZ

tPZH

tPZL

tPHZ

Control Input

3.3V Output

Normally Low

Enable Disable Times

3.3V Output

Normally High

VDD

VDD/2

.8VDD

.2VDD

VDD/2+0.2

VDD/2-0.2 .2VDD + .2V

.8VDD - .2V

tPHL

Propagation Delay

Input

Output

VDD

VDD/2

tPLH VOH

VOL

VDD/2

AC ELECTRICAL CHARACTERISTICS1 (Port A = Port B, 2.5 Volt Operation)

(VDD1 = 2.3V TO 2.7V; VDD2 = 2.3V to 2.7V, -55°C < TC < +125°C)

Notes:

1. All specifications valid for radiation dose ≤ 1E5 rad(Si) per MIL-STD-883, Method 1019.

2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested

3. Output skew is defined as a comparison of any two output transitions high-to-low vs. high-to-low and low-to-high vs. low-to-high

SYMBOL PARAMETER MINIMUM MAXIMUM UNIT

tPLH Propagation delay Data to Bus 2 10 ns

tPHL Propagation delay Data to Bus 2 10 ns

tPZL Output enable time OEx to Bus 2 12 ns

tPZH Output enable time OEx to Bus 2 12 ns

tPLZ Output disable time OEx to Bus high impedance 2 15 ns

tPHZ Output disable time OEx to Bus high impedance 2 15 ns

tPZL2Output enable time DIRx to Bus 2 12 ns

tPZH2Output enable time DIRx to Bus 2 1 2 ns

tPLZ2Output disable time DIRx to Bus high impedance 2 15 ns

tPHZ2Output disable time DIRx to Bus high impedance 2 15 ns

tSLH3

tSHL3

Skew between outputs (40pF +/- 10 pF on each output)

900

tPLZ

tPZH

tPZL

tPHL

tPHZ

Propagation Delay

Input

Output

VDD

VDD/2

tPLH

VOH

VOL

VDD/2

Control Input

2.5V Output

Normally Low

Enable Disable Times

2.5V Output

Normally High

VDD

VDD/2

.7VDD

.2VDD

VDD/2+0.2

VDD/2-0.2 .2VDD + .2V

.7VDD - .2V

PACKAGE

Figure 1. 48-Lead Flatpack

1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535.

2. The lid is electrically connected to VSS.

3. Lead finishes are in accordance with MIL-PRF-38535.

4. Lead position and colanarity are not measured.

5. ID mark symbol is vendor option.

6. With solder, increase maximum by 0.003.

ORDERING INFORMATION

UT54ACS1622 45S: SMD

Lead Finish:

(A) = Solder

Case Outline:

(X) = 48 lead FP

Class Designator:

(Q) = Class Q

(V) = Class V

Device Type

(01) = 16-bit MultiPurpose Low Voltage Transceiver

Drawing Number: 02543

Total Dose:

(R) = 1E5 rad(Si)

(F) = 3E5 rad(Si)

(G) = 5E5 rad(Si)

(H) = 1E6 rad(Si)

Federal Stock Class Designator

5962 R 02543 01 * * *

Notes:

1. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.

UT54ACS162245S

T54 *** ****** * * *

Lead Finish:

(A) = Solder

Screening:

(P) = Prototype

Package Type:

(U) = 48-lead FP

Part Number:

(162245S) = 16-bit MultiPurpose Low Voltage Transceiver

I/O Type:

(ACS)= CMOS compatible I/O Level

UTMC Core Part Number

Notes:

1. Military T emperature Range flow per UTMC Manufacturing Flows Document. Devices are tested -55C, room temp, and 125C. Radiation neither tested

nor guaranteed.

2. Prototype flow per UTMC Manufacturing Flows Document Tested at 25C only. Lead finish is gold only.

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to make changes to any products and services herein at any

time without notice. Consult Aeroflex or an authorized sales

representative to verify that the information in this data sheet

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