SBAS258A – JUNE 2002 – REVISED JULY 2002
FEATURES
D3.3V Single-Supply Operation
DDual Simultaneous Sample-and-Hold Inputs
DDifferential or Single-Ended Analog Inputs
DSingle or Dual Parallel Bus Output
D60dB SNR at fIN = 10.5MHz
D73dB SFDR at fIN = 10.5MHz
DLow Power: 240mW
D300MHz Analog Input Bandwidth
D3.3V TTL/CMOS-Compatible Digital I/O
DInternal or External Reference
DAdjustable Reference Input Range
DPower-Down (Standby) Mode
DTQFP-48 Package
APPLICATIONS
DDig it al Co mmu n icat io n s (Baseb an d Sampl i n g )
DVideo Processing
DPortable Instrumentation
DUltrasound
DESCRIPTION
The ADS5203 is a dual 10-bit, 40MSPS Analog-to-Digi-
tal Converter (ADC). It simultaneously converts each
analog input signal into a 10-bit, binary coded digital
word up to a maximum sampling rate of 40MSPS per
channel. All digital inputs and outputs are 3.3V
TTL/CMOS compatible.
An innovative dual-pipeline architecture implemented i n
a CMOS process and the 3.3V supply results in very low
power dissipation. In order to provide maximum flexibil-
ity, both top and bottom voltage references can be set
from user-supplied voltages. Alternatively, i f no external
references are available, the on-chip internal refer-
ences can be used. Both ADCs share a common refer-
ence to improve offset and gain matching. If external
reference voltage levels are available, the internal refer-
ences can be powered down independently from the
rest of the chip, resulting in even greater power savings.
The ADS5203 is characterized for operation from
–40°C to +85°C and is available in a TQFP-48 package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
www.ti.com
Copyright 2002, Texas Instruments Incorporated
SBAS258A – JUNE 2002 – REVISED JULY 2002
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2
ORDERING INFORMATION
PRODUCT PACKAGE–LEAD PACKAGE
DESIGNATOR(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING ORDERING
NUMBER TRANSPORT
MEDIA, QUANTITY
ADS5203 TQFP–48 PFB –40°C to +85°C AZ5203 ADS5203IPFB Tray, 250
ADS5203 TQFP–48 PFB –40°C to +85°C AZ5203 ADS5203IPFBR Tape and Reel, 1000
(1) For the most current specifications and package information, refer to our web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1).
Supply Voltage: AVDD to AGND, DVDD to DGND –0.5V to 3.6V. . . . . . . . . .
Supply Voltage: AVDD to DVDD, AGND to DGND –0.5V to 0.5V. . . . . . . . . .
Digital Input Voltage Range to DGND –0.5V to DVDD + 0.5V. . . . . . . . . . . .
Analog Input Voltage Range to AGND –0.5V to AVDD + 0.5 V. . . . . . . . . . . . .
Digital Output Voltage Appl i ed from Ex t. Source to DGND –0.5V to DVDD + 0.5V. . . . . . .
Reference Voltage Input Range to AGND: VREFT, VREFB –0.5V to AVDD + 0.5V. . . . . .
Operating Free-Air Temperature Range, TA (ADS5203I) –40°C to +8 5 °C. . .
Storage Temperature Range, TSTG –65°C to +150°C. . . . . . . . . . . . . . . . . .
Soldering Temperature 1.6mm (1/16 inch) from case for 10 seconds 300°C. . . . . . . . . . . .
(1) Stresses above these ratings may cause permanent damage. Exposure to
absolute maximum conditions for extended periods may degrade device
reliability. These are stress ratings only, and functional operation of the device
at these or any other conditions b eyond those s pecified is not implied.
This integrated circuit can be damaged by
ESD. Texas Instruments recommends that
all integrated circuits be handled with
appropriate precautions. Failure to observe proper
handling and installation procedures can cause
damage.
ESD damage can range from subtle performance
degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage
because very small parametric changes could cause
the device not to meet its published specifications.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range, TA, unless otherwise noted.
PARAMETER CONDITIONS MIN NOM MAX UNIT
Power Supply AVDD
Supply Voltage DVDD 3.0 3.3 3.6 V
Su ly
Voltage
DRVDD
3.0
3.3
3.6
Analog and Reference Inputs
Reference Input Voltage (top) VREFT fCLK = 1MHz to 80MHz 1.9 2.0 2.15 V
Reference Input Voltage (bottom) VREFB fCLK = 1MHz to 80MHz 0.95 1.0 1.1 V
Reference Voltage Differential VREFT – VREFB fCLK = 1MHz to 80MHz 0.95 1.0 1.1 V
Reference Input Resistance RREF fCLK = 80MHz 1650 Ω
Reference Input Current IREF fCLK = 80MHz 0.62 mA
Analog Input Voltage, Dif ferential VIN –1 1 V
Analog Input Voltage, Single–Ended(1) VIN CML – 1.0 CML + 1.0 V
Analog Input Capacitance CI8 pF
Clock Input(2) 0AVDD V
Analog Outputs
CML Voltage AVDD/2 V
CML Output Resistance 2.3 kΩ
Digital Inputs
High-Level Input Voltage VIH 2.4 DVDD V
Low-Level Input Voltage VIL DGND 0.8 V
Input Capacitance 5 pF
Clock Period tc (80MHz) 12.5 ns
Pulse Duration tw(CLKH), tw(CLKL) (80MHz) Clock HIGH or LOW 5.25 ns
Clock Period tc (40MHz) 25 ns
Pulse Duration tw(CLKH) , tw(CLKL) (40MHz) Clock HIGH or LOW 11.25 ns
(1) Applies only when the signal reference input connects to CML.
(2) Clock pin is referenced to AVDD/AVSS.
SBAS258A – JUNE 2002 – REVISED JULY 2002
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ELECTRICAL CHARACTERISTICS
over recommended operating conditions with fCLK = 80MHz and use of internal voltage references, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power Supply AVDD
AV DV DRV 3 3V
56 62
IDD Operating Supply Current DVDD AVDD = DVDD = DRVDD = 3.3V,
CL=10
p
Ff
IN = 3 5MHz
–
1dBFS
1.7 2.2 mA
IDD
O erating
Su ly
Current
DRVDD
C
L =
10
p
F
,
f
IN =
3
.
5MH
z, –
1dBFS
15 26
mA
Power Dissi
p
ation PD
PWDN_REF = ‘L’240 290
mW
Power Dissipation PDPWDN_REF = ‘H’220 240 mW
Standby Power PD(STBY) STDBY = ‘H’, CLK Held HIGH or LOW 95 150 µW
Power-Up Time for All References from Standby tPD 550 ms
W ake Up Time tWU External Reference 40 µs
Digital Inputs
High-Level Input Current on Digital Inputs incl. CLK IIH
AVDD =DV
DD =DRV
DD =36V
–1 1 µA
Low-Level Input Current on Digital Inputs incl. CLK IIL AVDD = DVDD = DRVDD = 3.6V –1 1 µA
Digital Outputs
High-Level Output Voltage VOH AVDD = DVDD = DRVDD = 3.0V at
IOH = 50µA, Digital Outputs Forced HIGH 2.8 2.96 V
Low-Level Output Voltage VOL AVDD = DVDD = DRVDD = 3.0V at
IOL = 50µA, Digital Outputs Forced LOW 0.04 0.2 V
Output Capacitance CO5 pF
High-Impedance State Output Current to High-Level IOZH
AVDD =DV
DD =DRV
DD =36V
–1 +1 µA
High-Impedance State Output Current to Low-Level IOZL AVDD = DVDD = DRVDD = 3.6V –1 +1 µA
Data Out
p
ut Rise and Fall Time
CLOAD = 10pF, Single–Bus Mode 3 ns
Data Output Rise-and-Fall Time CLOAD = 10pF, Dual–Bus Mode 5 ns
Reference Outputs
Reference Top Voltage VREFTO Absolute Min/Max Values Valid and 1.9 2 2.1 V
Reference Bottom Voltage VREFBO
Absolute
Min/Max
Values
Valid
and
Tested for AVDD = 3.3V 0.95 1 1.05 V
Differential Reference Votage REFT – REFB 0.95 1.0 1.05 V
DC Accuracy
Integral Nonlinearity End Point INL
Internal
TA=40°C to +85°C
15
±04
+1 5
LSB
Integral Nonlinearity, End Point INL
Internal
References(1) TA = –40°C to +85°C–1.5 ±0.4 +1.5 LSB
Differential Nonlinearity DNL Internal
References(2) TA = –40°C to +85°C–0.9 ±0.5 +1 LSB
Missing Codes No Missing Codes Assured
Zero Error(3)
AV DV DRV 3 3V
0.12 ±1.5 %FS
Full–Scale Error AVDD = DVDD = DRVDD = 3.3V
External References (3)
0.28 ±1.5 %FS
Gain Error
E
x
t
erna
l
R
e
f
erences
(3)
0.24 ±1.5 %FS
(1) Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full-scale. The point used as zero occurs ½LSB
before the first code transition. The full-scale point is defined as a level ½LSB beyond the last code transition. The deviation is measured from
the center of each particular code to the best-fit line between these two endpoints.
(2) An ideal ADC exhibits code transitions that are exactly 1LSB apart. DNL is the deviation from this ideal value. Therefore, this measure indicates
how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under test, (i.e., (last transition
level – first transition level)/(2n – 2)). Using this definition for DNL separates the effects of gain and offset error . A minimum DNL better than
–1LSB ensures no missing codes.
(3) Zero error is defined as the difference in analog input voltage—between the ideal voltage and the actual voltage—that will switch the ADC output
from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to ½LSB to the bottom reference level. The
voltage corresponding to 1LSB is found from the dif ference of top and bottom references divided by the number of ADC output levels (1024).
Full-scale error is defined as the difference in analog input voltage—between the ideal voltage and the actual voltage—that will switch the ADC
output from code 1022 to code 1023. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5LSB from the top
reference level. The voltage corresponding to 1LSB is found from the difference of top and bottom references divided by the number of ADC
output levels (1024).
SBAS258A – JUNE 2002 – REVISED JULY 2002
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DYNAMIC PERFORMANCE(1)
TA = TMIN to TMAX, A VDD = DVDD = DRVDD = 3.3V, fIN = –1dBFS, I nternal R eference, f CLK = 80MHz, fS = 4 0MSPS, and Differential Input Range = 2Vp–p,
unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Ef fective Number of Bits ENOB fIN = 3.5MHz 9.7 Bits
fIN = 10.5MHz 9.3 9.7 Bits
fIN = 20MHz 9.6 Bits
Total Harmonic Distortion THD fIN = 3.5MHz –71 dB
fIN = 10.5MHz –71 –66 dB
fIN = 20MHz –68 dB
Signal-to-Noise Ratio SNR fIN = 3.5MHz 60.5 dB
g
fIN = 10.5MHz 60.5 dB
fIN = 20MHz 60 dB
Signal-to-Noise Ratio + Distortion SINAD fIN = 3.5MHz 60 dB
g
fIN = 10.5MHz 57 60 dB
fIN = 20MHz 60 dB
Spurious-Free Dynamic Range SFDR fIN = 3.5MHz 75 dB
yg
fIN = 10.5MHz 69 73 dB
fIN = 20MHz 70.5 dB
Analog Input Bandwidth See Note (2) 300 MHz
2-Tone Intermodulation Distortion IMD f1 = 9.5MHz, f2 = 9.9MHz –68 dBc
A/B Channel Crosstalk –75 dBc
A/B Channel Offset Mismatch 0.016 1.75 % FS
A/B Channel Full-Scale Error Mismatch 0.016 1.0 % FS
(1) These specifications refer to a 25Ω series resistor and 15pF differential capacitor between A/B+ and A/B– inputs; any source impedance will
bring the bandwidth down.
(2) Analog input bandwidth is defined as the frequency at which the sampled input signal is 3dB down on unity gain and is limited by the input switch
impedance.
SBAS258A – JUNE 2002 – REVISED JULY 2002
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PIN CONFIGURATION
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO. I/O DESCRIPTION
DRVDD 1,13 I Supply Voltage for Output Drivers
DRVSS 12, 24 IDigital Ground for Output Drivers
DA 9..0 14-23 O Data Outputs for Bus A. D9 is MSB. This is the primary bus. Data from both input channels can be output on this bus
or data from the A channel only. Pins SELB and MODE select the output mode. The data outputs are in tri-state during
power-down (refer to Timing Options table).
DB 9..0 2-11 O Data Outputs for Bus B. D9 is MSB. This is the second bus. Data is output from the B-channel when dual bus output mode
is selected. The data outputs are in tri-state during power-down and single-bus modes (refer to Timing Options table).
OE 48 I Output Enable. A LOW on this terminal will enable the data output bus, COUT and COUT.
COUT 26 O Latch Clock for the Data Outputs. COUT is in tri-state during power-down.
COUT 25 O Inverted Latch Clock or multiplexer control for the Data Outputs. COUT is in tri-state during power–down.
SELB 44 I Selects either single-bus data output or dual-bus data output. A LOW selects dual-bus data output.
DVSS 43 I Digital Ground
CLK 47 I Clock Input. The input is sampled on each rising edge of CLK when using a 40MHz input and alternate rising edges when
using an 80MHz input. The clock pin is referenced to AVDD and AV SS to reduce noise coupling from digital logic.
DVDD 45 I Digital Supply Voltage
AVDD 27,37,41 I Analog Supply Voltage
MODE 46 I Selects the COUT and COUT output mode.
AVSS 28,36,40 I Analog Ground
B–35 I Negative Input for the Analog B Channel
B+ 34 I Positive Input for the Analog B Channel
REFT 31 I/O Reference Voltage Top. The voltage at this terminal defines the top reference voltage for the ADC. Sufficient filtering
should b e applied to this input: the use of 0.1µF capacitor between REFT and AVSS is recommended. Additionally a 0.1µF
capacitor should be connected between REFT and REFB.
REFB 30 I/O Reference Voltage Bottom. The voltage at this terminal defines the bottom reference voltage for the ADC. Sufficient
filtering should be applied to this input: the us e of 0. 1µF capacitor between REFB and AVSS is recommended. Additionally
a 0.1µF capacitor should be connected between REFT and REFB.
CML 32 O Common-Mode Level. This voltage is equal to (AVDD – AVSS)/2. An external capacitor of 0.1µF should be connected
between this terminal and AVSS when CML is used as a bias voltage. No capacitor is required if CML is not used.
PDWN_REF 33 I Power-Down for Internal Reference V ol tages. A HIGH on this terminal disables the internal reference circuit.
STBY 42 I Standby Input. A HIGH on this terminal will power down the device.
A–39 I Negative Input for the Analog A Channel
A+ 38 I Positive Input for Analog A Channel
TP 29 This pin must be connected to DVDD. It should not be left floating.
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TIMING REQUIREMENTS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input Clock Rate fCLK 1 80 MHz
Conversion Rate 1 40 MSPS
Clock Duty Cycle (40MHz) 45 50 55 %
Clock Duty Cycle (80MHz) 42 50 58 %
Output Delay Time td(o) CL = 10pF 9 14 ns
Mux Setup Time ts(m) 9 10.4 ns
Mux Hold Time th(m) 1.7 2.1 ns
Output Setup Time ts(o) CL = 10pF 9 10.4 ns
Output Hold Time th(o) CL = 10pF 1.5 2.2 ns
Pipeline Delay (latency, channels A and B) td(pipe) MODE = 0, SELB = 0 8CLK Cycles
Pipeline Delay (latency, channels A and B) td(pipe) MODE = 1, SELB = 0 4CLK Cycles
Pipeline Delay (latency, channel A) td(pipe) MODE = 0, SELB = 1 8CLK Cycles
Pipeline Delay (latency, channel B) td(pipe) MODE = 0, SELB = 1 9CLK Cycles
Pipeline Delay (latency, channel A) td(pipe) MODE = 1, SELB = 1 8CLK Cycles
Pipeline Delay (latency, channel B) td(pipe) MODE = 1, SELB = 1 9CLK Cycles
Aperture Delay Time td(a) 3 ns
Aperture Jitter tJ(a) 1.5 ps, rms
Disable Time, OE Rising to Hi–Zt
dis 5 8 ns
Enable T ime, OE Falling to Valid Data ten 5 8 ns
TIMING OPTIONS
OPERATING MODE MODE SELB TIMING DIAGRAM FIGURE
80MHz Input Clock, Dual-Bus Output, COUT = 40MHz 0 0 1
40MHz Input Clock, Dual-Bus Output, COUT = 40MHz 1 0 2
80MHz Input Clock, Single-Bus Output, COUT = 40MHz 0 1 3
80MHz Input Clock, Single-Bus Output, COUT = 80MHz 1 1 4
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TIMING DIAGRAMS
Analog_A
Analog_B
DA[9:0]
DB[9:0]
DAB[19:0]
A1 A2 A3 A4 A5
B1 B2 B3 B4 B5
A1 A2 A3 A4 A5
B1 B2 B3 B4 B5
A&B 1 A&B 2 A&B 3 A&B 4 A&B 5
td(pipe)
t
td(o)
td(pipe)
ts(o) th(o)
0 1 2 3 4 5 6 7 8 9 101112131415161718
Sample A1 and B1
DAB[19:0] is used to illustrate the placement of the busses DA and DB
ADCOUTA[9:0](3)
ADCOUTB[9:0](3)
COUT
COUT
d(o)
CLK(1)
CLK40INT(2)
NOTES: (1) In this option CLK = 80MHz. (2) CLK40INT refers to 40MHz Internal Clock, per channel. (3) Internal signal only.
Figure 1. Dual Bus Output—Option 1.
Analog_A
Analog_B
DA[9:0]
DB[9:0]
DAB[19:0]
A1 A2 A3 A4 A5
B1 B2 B3 B4 B5
A1 A2 A3 A4 A5
B1 B2 B3 B4 B5
A&B 1 A&B 2 A&B 3 A&B 4 A&B 5
td(o)
td(o)
ts(o) th(o)
td(pipe)
td(pipe)
89101234567
Sample A1 and B1
DAB[19:0] is used to illustrate the combined busses DA and DB
ADCOUTA[9:0](2)
ADCOUTB[9:0](2)
COUT
COUT
CLK(1)
NOTE: (1) In this option CLK = 40MHz, per channel. (2) Internal signal only
Figure 2. Dual Bus Output—Option 2.
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TIMING DIAGRAMS (Cont.)
Analog_A
Analog_B
DA[9:0]
A1 A2 A3 A4 A5
B1 B2 B3 B4 B5
A1 B1 A2 B2 A3 B3 A4 B4 A5 B5
td(pipe)
td(o)
td(pipe)
td(o)
th(o)
th(o)
ts(o)
ts(o)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Sample A1 and B1
ADCOUTA[9:0](3)
ADCOUTB[9:0](3)
COUT
COUT
CLK(1)
CLK40INT(2)
NOTES: (1) In this option CLK = 80MHz. (2) CLK40INT refers to 40MHz Internal Clock, per channel. (3) Internal signal only.
Figure 3. Single Bus Output—Option 1.
Analog_A
Analog_B
DA[9:0]
A1 A2 A3 A4 A5
B1 B2 B3 B4 B5
A1 B1 A2 B2 A3 B3 A4 B4 A5 B5
td(pipe)
td(o)
td(pipe)
td(o)
ts(o)
th(o)
ts(m)
th(m)
01 2 3 4 5 6 7 8 9 101112131415161718
Sample A1 and B1
ADCOUTA[9:0](3)
ADCOUTB[9:0](3)
COUT
COUT
CLK(1)
CLK40INT(2)
NOTES: (1) In this option CLK = 80MHz. (2) CLK40INT refers to 40MHz Internal Clock, per channel. (3) Internal signal only.
Figure 4. Single Bus Output—Option 2.
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TYPICAL CHARACTERISTICS
At T A = 25°C, AVDD = DV DD = DRVDD = 3.3V, fIN = –0.5dBFS, Internal Reference, fCLK = 80M Hz, fS = 40MSPS, Differential Input Range = 2Vp-p,
25Ω series r esistor, and 15pF differential capacitor at A/B+ and A/B– inputs, unless otherwise noted.
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Typical Characteristics (Cont.)
At T A = 25°C, AVDD = DV DD = DRVDD = 3.3V, fIN = –0.5dBFS, Internal Reference, fCLK = 80M Hz, fS = 40MSPS, Differential Input Range = 2Vp-p,
25Ω series r esistor, and 15pF differential capacitor at A/B+ and A/B– inputs, unless otherwise noted.
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PRINCIPLE OF OPERATION
The ADS5203 implements a dual high-speed, 10-bit,
40MSPS converter in a cost-effective CMOS process.
The differential inputs on each channel are sampled
simultaneously. Signal inputs are differential and the
clock signal is single-ended. The clock signal is either
80MHz or 40MHz, depending on the device
configuration set by the user. Powered from 3.3V, the
dual-pipeline design architecture ensures low-power
operation and 10-bit resolution. The digital inputs are
3.3V TTL/CMOS compatible. Internal voltage
references are included for both bottom and top
voltages. Alternatively, the user may apply externally
generated reference voltages. In doing so, the input
range can be modified to suit the application.
The ADC is a 5-stage pipelined ADC with 4 stages of
fully-differential switched capacitor sub-ADC/MDAC
pairs and a single sub-ADC in stage 5. All stages deliver
2 bits of the final conversion result. A digital error
correction is used to compensate for modest
comparator offsets in the sub-ADCs.
SAMPLE-AND-HOLD AMPLIFIER
Figure 5 shows the internal SHA architecture. The
circuit is balanced and fully differential for good supply
noise rejection. The sampling circuit has been kept as
simple as possible to obtain good performance for
high-frequency input signals.
Figure 5. SHA Architecture.
The analog input signal is sampled on capacitors CSP
and CSN while the internal device clock is low. The
sampled voltage is transferred to capacitors CHP and
CHN and held on these while the internal device clock
is high. The SHA can sample both single-ended and
differential input signals.
The load presented to the AIN pin consists of the
switched input sampling capacitor CS (approximately
2pF) and its various stray capacitances. A simplified
equivalent circuit for the switched capacitor input is
shown in Figure 6. The switched capacitor circuit is
modeled a s a r e s i s t o r R IN. fCLK is the clock frequency,
which is 40MHz at full speed, and CS is the sampling
capacitor. Using 25Ω series resistors and a differential
15pF capacitor at the A/B+ and A/B– inputs is
recommended to reduce noise.
NOTE: AIN can be any variation
of A or B inputs.
VCM = 0.5 S (V(A/B+) + V(A/B–))
VCM
fCLK = 40MHz
Figure 6. Equivalent Circuit for the Switched
Capacitor Input.
ANALOG INPUT, DIFFERENTIAL
CONNECTION
The analog input of the ADS5203 is a differential
architecture that can be configured in various ways
depending on the signal source and the required level
of performance. A fully differential connection will
deliver the best performance from the converter. The
analog inputs must not go below AVSS or above AVDD.
The inputs can be biased with any common-mode
voltage provided that the minimum and maximum input
voltages stay within the range AVSS to AVDD. It is
recommended to bias the inputs with a common-mode
voltage around AVDD/2. This can be accomplished
easily with the output voltage source CML, which is
equal to AVDD/2. CML is made available to the user to
help simplify circuit design. This output voltage source
is not designed to be a reference or to be loaded but
makes an excellent DC bias source and stays well
within the analog input common-mode voltage range
over temperature.
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Table 1 lists the digital outputs for the corresponding
analog input voltages.
Ta ble 1. Output For ma t for Diffe re ntial C onfigura tion
DIFFERENTIAL INPUT
VIN = (A+/B+) – (A–/B–), REFT – REFB = 1V
ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE
VIN = +1V 3FFH
VIN = 0 200H
VIN = –1V 000H
DC–COUPLED DIFFERENTIAL ANALOG
INPUT CIRCUIT
Driving the analog input differentially can be achieved
in various ways. Figure 7 gives an example where a
single-ended signal is converted into a di fferential signal
by using a fully differential amplifier such as the
THS4141. The input voltage applied to VOCM of the
THS4141 shifts the output signal into the desired
common-mode level. VOCM can be connected to CML
of the ADS5203, the common-mode level is shifted to
AVDD/2.
Figure 7. Single-Ended to Differential Conversion
Using the THS4141.
AC–COUPLED DIFFERENTIAL ANALOG
INPUT CIRCUIT
Driving the analog input differentially can be achieved by
using a transformer-coupling, as illustrated in Figure 8.
The center tap o f the t ransformer i s connected to t he v olt-
age sour c e CML, whic h set s the comm on- mode voltage
to AVDD/2. No b uffer i s r equired at the o utput o f CML s ince
the ci rcuit is balanced and no c urrent is drawn from CML.
Figure 8. AC-Coupled Differential Input with
Transformer.
ANALOG INPUT, SINGLE–ENDED
CONFIGURATION
For a single-ended configuration, the input signal is
applied to only one of the two inputs. The signal applied
to the analog input must not go below AVSS or above
AVDD. The inputs can b e b iased with any c ommon-mode
voltage provided that the minimum and maximum input
voltage stays within the range AVSS to AVDD. It is
recommended to bias the inputs with a common-mode
voltage around AVDD/2. This can be accomplished easily
with the output voltage source CML, which is equal to
AVDD/2. An example for this is shown in Figure 9.
Figure 9. AC–Coupled, Single-Ended Configuration.
The signal amplitude to achieve full scale is 2Vp-p. The
signal, which is applied at A/B+ is centered at the bias
voltage. The input A/B– is also centered at the bias
voltage. The CML output is connected via a 4.7kΩ
resistor to bias the input signal. There is a direct
DC-coupling from CML to A/B– while this input is
AC-decoupled through the 10µF and 0.1µF capacitors.
The decoupling minimizes the coupling of A/B+ into the
A/B– path.
SBAS258A – JUNE 2002 – REVISED JULY 2002
www.ti.com
13
Table 2 lists the digital outputs for the corresponding
analog input voltages.
Table 2. Output Format for Single-Ended Configu-
ration.
SINGLE–ENDED INPUT, REFT – REFB = 1V
ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE
V(A/B+) = VCML + 1V 3FFH
V(A/B+) = VCML 200H
V(A/B+) = VCML – 1V 000H
REFERENCE TERMINALS
The ADS5203’s input range is determined by the voltages
on its REF B and REF T pins. The ADS5203 has an int er -
nal voltage reference generator that sets the ADC refer-
ence voltages REFB = 1V and REFT = 2V. The internal
ADC references must be decoupled to the PCB AVSS
plane. The recommended decoupling scheme is shown
in Figure 10. The internal reference voltages common-
mode voltage is 1. 5V.
Figure 10. Recommended External Decoupling for
the Internal ADC Reference.
External ADC references can also be chosen. The
ADS5203 internal references must be disabled by tying
PWDN_REF HIGH before applying the external
reference sources to the REFT and REFB pins. The
external reference voltages common-mode voltage
should be 1.5V for best ADC perform ance.
Figure 11. External ADC Reference Configuration.
DIGITAL INP UTS
Digital inputs a re C LK, STDBY, P WDN_REF, OE, MODE,
and SE LB . Thes e input s don’t have a pull-down resistor
to ground, theref ore, they should not be lef t floating.
The C LK signal a t h igh frequencies should b e considered
as an ‘analog’ input. CLK should be referenced to AVDD
and AVSS to reduce noise coupling from the digital logic.
Overshoot/undershoot should be minimized by proper
termination of the signal close to the ADS5203. An
important cause of performance degradation for a
high-speed ADC is clock jitter. Clock jitter causes
uncertainty i n the s ampling instant of the ADC, in a ddition
to t he inherent u ncertainty on t he s ampling instant caused
by the part it self, as specified by its aperture jitter. There
is a theor et ical relations hip between the fr equency f and
resolution (2N) of a signal that needs to be sampled on
one hand, and on the other hand the maximum amount
of aperture error dtmax that is tolerable. It is given by the
following relation:dtmax = 1/[π f 2(N+1)]
As an e xample, for a 10-bit converter with a 2 0MHz input,
the jitter needs to be kept less than 7.8ps in order not to
have changes in the LS B of the ADC output due to the
total aperture error.
DIGITAL OUTPUTS
The output of ADS5203 is an unsigned binary code.
Capacitive l oading on the o utput should be kept a s low a s
possible (a maxim um loading of 10pF is recom m ended)
to ensure best performance. Higher output loading
causes higher dynamic output currents and can,
theref ore, increase noise coupling into the part’s analog
front end. To d rive higher l oads, t he u se of a n o utput buffer
is rec omm ended.
When clocking output data f rom ADS5203, it is important
to ob s er ve its timin g r e l a ti o n to COUT. Please refer to the
timing section for detailed information on the pipeline
latency in the different modes.
For s afest system timing, COUT and COUT s hould be u sed
to latch the output data, (see Figures 1 to 4). In Figure 4,
COUT can be used by the receiving device to identify
whether the data presently on the bus is from channel A
or B.
LAYOUT, DECOUPLING , AND GROUNDING
RULES
Proper grounding and layout of the PCB on which the
ADS5203 is populat ed is ess ent ial to achieve the stated
performance. It is advised to use separate analog and
digital ground planes that ar e spliced underneath the IC.
The ADS5203 has digital and analog pins on opposite
sides of the package to make this easier. Since there is
no connection internally between analog and digital
grounds, they have to be joined on t he PCB. It is a dvised
to do this at one point in close proximity to the ADS5203.
SBAS258A – JUNE 2002 – REVISED JULY 2002
www.ti.com
14
As for power supplies, separate analog and digital
supply pins are provided on the part (AVDD/DVDD). The
supply to the digital output drivers is kept separate as
well (DRVDD). Lowering the voltage on this supply to
3.0V in s t ead of the nominal 3.3V improves performance
because of the lower switching noise caused by the
output buffers.
Due to the high sampling rate and switched-capacitor
architecture, the ADS5203 generates transients on the
supply and reference lines. Proper decoupling of these
lines is, therefore, essential.
NOTES
1. Integral Nonlinearity (INL)—Integral nonlinearity
refers to the deviation of each individual code from a line
drawn from zero to full-scale. The point used as zero
occurs ½LSB before the first code transition. The
full-scale point is defined as a level ½LSB beyond the
last code transition. The deviation is measured from t h e
center of each particular code to the true straight line
between these two endpoints.
2. Differential Nonlinearity (DNL)—An ideal ADC
exhibits code t ransitions that a re e xactly 1LSB a part. DNL
is the deviation from this ideal value. Therefore, this
measure indicates how uniform the transfer function step
sizes are. The ideal step size is defined here as the step
size for the device under tes t (i.e. , (las t trans ition lev el –
first transition level)/(2n – 2 )). Using this d efinition for DNL
separates the effects of gain and offset err or.
A minimum DNL better than –1LSB ensures no missing
codes.
3. Zero and Full-Scale Error—Zero error is defined as
the difference in analog input voltage—between the
ideal voltage and the actual voltage—that will switch the
ADC output from code 0 to code 1. The ideal voltage
level i s d e t e r m i ned by adding the voltage corresponding
to ½LSB to the bottom reference level. The voltage
corresponding to 1LSB is found from the difference of
top and bottom references divided by the number of
ADC output levels (1024).
Full-scale error is defined as the difference in analog
input vo l t a g e —between the ideal voltage and the actual
voltage—that will switch the ADC output from code
1022 to code 1023. The ideal voltage level is
determined by subtracting the voltage corresponding to
1.5LSB from the top reference level. The voltage
corresponding to 1LSB is found from the difference of
top and bottom references divided by the number of
ADC output levels (1024).
4. Analog Input Bandwidth—The analog input
bandwidth i s defined as the max. frequency of a 1dBFS
input sine that can be applied to the device for which an
extra 3dB attenuation is observed in the reconstructed
output signal.
5. Output Timing—Output timing td(o) is measured
from the 1.5V level of the CLK input falling edge to the
10%/90% level of the digital output. The digital output
load is not higher than 10pF.
Output hold time th(o) is measured from the 1.5V level
of the COUT input rising edge to the 10%/90% level of
the digital output. The digital output is load is not less
than 2pF. Aperture delay td(A) is measured from the
1.5V level of the CLK input to the actual sampling
instant.
The OE signal is asynchronous. OE timing tdis is
measured from the VIH(MIN) level of OE to the
high-impedance state of the output data. The digital
output load is not higher than 10pF. OE timing ten is
measured from the VIL(MAX) level of OE to the instant
when the output data reaches VOH(min) or VOL(max)
output levels. The digital output load is not higher than
10pF.
6. Pipeline Delay (latency)—The number of clock
cycles be t ween conversion initiation on an input sample
and the corresponding output data being made
available from the ADC pipeline. Once the data pipeline
is full, new valid output data is provided on every clock
cycle. The first valid data is available on the output pins
after the latency time plus the output delay time td(o)
through the digital output buf fers. Note that a minimum
td(o) is not guaranteed because data can transition
before or after a CLK edge. It is possible to use CLK for
latching data, but at the risk of the prop delay varying
over temperature, causing data to transition one CLK
cycle earlier or later. The recommended method is to
use the latch signals COUT and COUT which are
designed to provide reliable setup and hold times with
respect to the data out.
7. Wake-Up Time—Wake-up time is from the
power-down state to accurate ADC samples being
taken, and is specified for external reference sources
applied t o the device and an 80MHz clock applied at the
time of release of STDBY. Cells that need to power up
are the bandgap, bias generator, SHAs, and ADCs.
8. Power-Up Time—Power-up time is from the
power-down state to accurate ADC samples being
taken with an 80MHz clock applied at the time of release
of STDBY. Cells that need to power up are the bandgap,
internal reference circuit, bias generator, SHAs, and
ADCs.
SBAS258A – JUNE 2002 – REVISED JULY 2002
www.ti.com
15
PACKAGE DRAWING
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
ADS5203IPFB ACTIVE TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS5203IPFBG4 ACTIVE TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS5203IPFBR ACTIVE TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS5203IPFBRG4 ACTIVE TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2006
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS5203IPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS5203IPFBR TQFP PFB 48 1000 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 2
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