7/20/04
IRF820ASPbF
IRF820ALPbF
SMPS MOSFET
HEXFET® Power MOSFET
lSwitch Mode Power Supply (SMPS)
lUninterruptable Power Supply
lHigh speed power switching
lLead-Free
Benefits
Applications
lLow Gate Charge Qg Results in Simple
Drive Requirement
lImproved Gate, Avalanche and Dynamic
dv/dt Ruggedness
lFully Characterized Capacitance and
Avalanche Voltage and Current
lEffective COSS specified (See AN 1001)
VDSS RDS(on) max ID
500V 3.0Ω2.5A
Typical SMPS Topologies:
l Two Transistor Forward
l Half Bridge and Full Bridge
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V2.5
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V1.6 A
IDM Pulsed Drain Current 10
PD @TC = 25°C Power Dissipation 50 W
Linear Derating Factor 0.4 W/°C
VGS Gate-to-Source Voltage ± 30 V
dv/dt Peak Diode Recovery dv/dt 3.4 V/ns
TJOperating Junction and -55 to + 150
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
°C
Mounting torqe, 6-32 or M3 screw 10 lbf•in (1.1N•m)
Absolute Maximum Ratings
PD - 95533
Notes through are on page 8
D2Pak
IRF820AS
TO-262
IRF820AL
Document Number: 91058
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1
IRF820AS/LPbF
Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 1.4 ––– ––– S VDS = 50V, ID = 1.5A
QgTotal Gate Charge ––– ––– 17 ID = 2.5A
Qgs Gate-to-Source Charge ––– ––– 4.3 nC VDS = 400V
Qgd Gate-to-Drain ("Miller") Charge ––– ––– 8.5 VGS = 10V, See Fig. 6 and 13
td(on) Turn-On Delay Time ––– 8.1 ––– VDD = 250V
trRise Time ––– 12 ––– ID = 2.5A
td(off) Turn-Off Delay Time ––– 16 ––– RG = 21Ω
tfFall Time ––– 13 ––– RD = 97Ω,See Fig. 10
Ciss Input Capacitance ––– 340 ––– VGS = 0V
Coss Output Capacitance ––– 53 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 2.7 ––– pF ƒ = 1.0MHz, See Fig. 5
Coss Output Capacitance ––– 490 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss Output Capacitance ––– 15 ––– VGS = 0V, VDS = 400V, ƒ = 1.0MHz
Coss eff. Effective Output Capacitance ––– 28 ––– VGS = 0V, VDS = 0V to 400V
Dynamic @ TJ = 25°C (unless otherwise specified)
ns
Parameter Typ. Max. Units
EAS Single Pulse Avalanche Energy ––– 140 mJ
IAR Avalanche Current––– 2.5 A
EAR Repetitive Avalanche Energy––– 5.0 mJ
Avalanche Characteristics
S
D
G
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) ––– ––– showing the
ISM Pulsed Source Current integral reverse
(Body Diode) ––– ––– p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.6 V TJ = 25°C, IS = 2.5A, VGS = 0V
trr Reverse Recovery Time ––– 330 500 ns TJ = 25°C, IF = 2.5A
Qrr Reverse RecoveryCharge ––– 760 1140 nC di/dt = 100A/µs
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Diode Characteristics
2.5
10
A
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 500 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.60 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 3.0 ΩVGS = 10V, ID = 1.5A
VGS(th) Gate Threshold Voltage 2.0 ––– 4.5 V VDS = VGS, ID = 250µA
––– ––– 25 µA VDS = 500V, VGS = 0V
––– ––– 250 VDS = 400V, VGS = 0V, TJ = 125°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 30V
Gate-to-Source Reverse Leakage ––– ––– -100 nA VGS = -30V
IGSS
IDSS Drain-to-Source Leakage Current
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 2.5 °C/W
RθJA Junction-to-Ambient ( PCB Mounted, steady-state)* ––– 62
Thermal Resistance
Document Number: 91058
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2
IRF820AS/LPbF
Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
0.01
0.1
1
10
0.1 1 10 100
20µs PULSE WIDTH
T = 25 C
J°
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
4.5V
0.1
1
10
1 10 100
20µs PULSE WIDTH
T = 150 C
J°
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
4.5V
0.01
0.1
1
10
4.0 5.0 6.0 7.0 8.0 9.0
V = 50V
20µs PULSE WIDTH
DS
V , Gate-to-Source Voltage (V)
I , Drain-to-Source Current (A)
GS
D
T = 25 C
J°
T = 150 C
J°
-60 -40 -20 020 40 60 80 100 120 140 160
0.0
0.5
1.0
1.5
2.0
2.5
3.0
T , Junction Temperature ( C)
R , Drain-to-Source On Resistance
(Normalized)
J
DS(on)
°
V =
I =
GS
D
10V
2.5A
Document Number: 91058
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3
IRF820AS/LPbF
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
0.1
1
10
0.4 0.6 0.8 1.0 1.2
V ,Source-to-Drain Voltage (V)
I , Reverse Drain Current (A)
SD
SD
V = 0 V
GS
T = 25 C
J°
T = 150 C
J°
0.1
1
10
100
10 100 1000 10000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
Single Pulse
T
T
= 150 C
= 25 C
°
°
J
C
V , Drain-to-Source Voltage (V)
I , Drain Current (A)I , Drain Current (A)
DS
D
10us
100us
1ms
10ms
0 4 8 12 16
0
5
10
15
20
Q , Total Gate Charge (nC)
V , Gate-to-Source Voltage (V)
G
GS
FOR TEST CIRCUIT
SEE FIGURE
I =
D
13
2.5A
V = 100V
DS
V = 250V
DS
V = 400V
DS
110 100 1000
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
10000
C, Capacitance(pF)
Coss
Crss
Ciss
VGS
= 0V, f = 1 MHZ
Ciss
= C
gs + C
gd, C
ds SHORTED
Crss
= C
gd
Coss
= C
ds
+ C
gd
Document Number: 91058
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4
IRF820AS/LPbF
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-
VDD
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
25 50 75 100 125 150
0.0
0.5
1.0
1.5
2.0
2.5
3.0
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
Document Number: 91058
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5
IRF820AS/LPbF
QG
QGS QGD
VG
Charge
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
25 50 75 100 125 150
0
50
100
150
200
250
300
Starting T , Junction Temperature ( C)
E , Single Pulse Avalanche Energy (mJ)
J
AS
°
ID
TOP
BOTTOM
1.1A
1.6A
2.5A
Fig 12d. Typical Drain-to-Source Voltage
Vs. Avalanche Current
0.0 0.5 1.0 1.5 2.0 2.5
IAV , Avalanche Current ( A)
550
600
650
700
V DSav , Avalanche Voltage ( V )
Document Number: 91058
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6
IRF820AS/LPbF
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P. W .
Period
+
-
+
+
+
-
-
-
Fig 14. For N-Channel HEXFET® power MOSFETs
* VGS = 5V for Logic Level Devices
Peak Diode Recovery dv/dt Test Circuit
RG
VDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
*
Document Number: 91058
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7
IRF820AS/LPbF
N ote: "P " in as s embly line
pos ition indicates "L ead-F ree"
F530S
T H IS IS AN IR F 530S WIT H
LOT CODE 8024
ASS EMB LED ON WW 02, 2000
IN THE ASSEMBLY LINE "L"
AS S E MB L Y
LOT CODE
IN T E R N AT IONAL
RECTIFIER
LOGO
PART NUMBER
DATE CODE
YEAR 0 = 2000
WEEK 02
LINE L
OR
F530S
A = AS S E MB L Y S IT E CO D E
WE EK 02
P = DE S IGN AT E S L E AD-F R E E
PRODUCT (OPTIONAL)
R E CT IF IE R
INT E R NAT IONAL
LOGO
LOT CODE
ASSEMBLY
YEAR 0 = 2000
DATE CODE
PART NUMBER
D2Pak Part Marking Information (Lead-Free)
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
Document Number: 91058
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8
IRF820AS/LPbF
TO-262 Part Marking Information
TO-262 Package Outline
ASSEMBLY
LOT CODE
RE CTIF IE R
INT ERNATIONAL
ASS E MBLED ON WW 19, 1997
Note: "P" in ass embly line
pos ition in di cates "L ead-F ree"
IN THE AS S EMBLY LINE "C" LOGO
THIS IS AN IRL3103L
LOT CODE 1789
EXAMPLE:
LINE C
DATE CODE
WEEK 19
YEAR 7 = 1997
PART NUMBER
PART NUMBER
LOGO
LOT CODE
ASSEMBLY
INTERNATIONAL
RE CTIF IE R
PRODUCT (OPTIONAL)
P = DES IGNATES LEAD-FREE
A = AS SE MB L Y S IT E CODE
WEEK 19
YEAR 7 = 1997
DATE CODE
OR
Document Number: 91058
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9
IRF820AS/LPbF
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
ISD ≤ 2.5A, di/dt ≤ 270A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C
Notes:
Starting TJ = 25°C, L = 45mH
RG = 25Ω, IAS = 2.5A. (See Figure 12)
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Uses IRF820A data and test conditions
* When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
07/04
3
4
4
TRR
FEED DIRECTION
1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
TRL
FEED DIRECTION
10.90 (.429)
10.70 (.421)
16.10 (.634)
15.90 (.626)
1.75 (.069)
1.25 (.049)
11.60 (.457)
11.40 (.449) 15.42 (.609)
15.22 (.601)
4.72 (.136)
4.52 (.178)
24.30 (.957)
23.90 (.941)
0.368 (.0145)
0.342 (.0135)
1.60 (.063)
1.50 (.059)
13.50 (.532)
12.80 (.504)
330.00
(14.173)
MAX.
27.40 (1.079)
23.90 (.941)
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
D2Pak Tape & Reel Infomation
Document Number: 91058
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10
Legal Disclaimer Notice
Vishay
Document Number: 99901 www.vishay.com
Revision: 12-Mar-07 1
Notice
The products described herein were acquired by Vishay Intertechnology, Inc., as part of its acquisition of
International Rectifier’s Power Control Systems (PCS) business, which closed in April 2007. Specifications of the
products displayed herein are pending review by Vishay and are subject to the terms and conditions shown below.
Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or
anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.
Information contained herein is intended to provide a product description only. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's
terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express
or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness
for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications.
Customers using or selling these products for use in such applications do so at their own risk and agree to fully
indemnify Vishay for any damages resulting from such improper use or sale.
International Rectifier®, IR®, the IR logo, HEXFET®, HEXSense®, HEXDIP®, DOL®, INTERO®, and POWIRTRAIN®
are registered trademarks of International Rectifier Corporation in the U.S. and other countries. All other product
names noted herein may be trademarks of their respective owners.
