16-Bit, 1.5 LSB INL, 500 kSPS PulSAR™
Differential ADC in MSOP/LFCSP
Data Sheet
AD7688
FEATURES
16-bit resolution with no missing codes
Throughput: 500 kSPS
INL: ±0.4 LSB typ, ±1.5 LSB max (±23 ppm of FSR)
Dynamic range: 96.5 dB
SNR: 95.5 dB at 20 kHz
THD: −118 dB at 20 kHz
True differential analog input range
±VREF
0 V to VREF with VREF up to VDD on both inputs
No pipeline delay
Single-supply 5 V operation with
1.8 V/2.5 V/3 V/5 V logic interface
Proprietary serial interface
SPI®/QSPI™/MICROWIRE™/DSP-compatible1
Daisy-chain multiple ADCs and BUSY indicator
Power dissipation
3.75 mW at 5 V/100 kSPS
3.75 µW at 5 V/100 SPS
Standby current: 1 nA
10-lead MSOP (MSOP-8 size) and
3 mm × 3 mm LFCSP (SOT-23 size)
Pin-for-pin compatible with AD7685, AD7686, and AD7687
APPLICATIONS
Battery-powered equipment
Data acquisitions
Instrumentation
Medical instruments
Process controls
CODE
INL (LSB)
1.5
1.0
0.5
0
–0.5
–1.0
–1.5 0 16384 32768 49152 65535
02973-001
POSITIVE INL = +0.31LSB
NEGATIVE INL = –0.39LSB
Figure 1. Integral Nonlinearity vs. Code
APPLICATION DIAGRAM
AD7688
REF
GND
VDD
IN+
IN–
VIO
SDI
SCK
SDO
CNV
1.8V TO VDD
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
0.5V TO 5V 5V
VREF
0
02973-002
VREF
0
Figure 2.
Table 1. MSOP, LFCSP/SOT-23 16-Bit PulSAR ADC
Type 100 kSPS 250 kSPS 500 kSPS
True Differential AD7684 AD7687 AD7688
Pseudo AD7683 AD7685 AD7686
Differential/Unipolar AD7694
Unipolar AD7680
GENERAL DESCRIPTION
The AD7688 is a 16-bit, charge redistribution, successive
approximation, analog-to-digital converter (ADC) that operates
from a single 5 V power supply, VDD. It contains a low power,
high speed, 16-bit sampling ADC with no missing codes, an
internal conversion clock, and a versatile serial interface port.
The part also contains a low noise, wide bandwidth, short
aperture delay track-and-hold circuit. On the CNV rising edge,
it samples the voltage difference between IN+ and IN− pins.
The voltages on these pins usually swing in opposite phase
between 0 V and REF. The reference voltage, REF, is applied
externally and can be set up to the supply voltage.
Its power scales linearly with throughput.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single,
3-wire bus and provides an optional BUSY indicator. It is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate
supply VIO.
The AD7688 is housed in a 10-lead MSOP or a 10-lead LFCSP
with operation specified from −40°C to +85°C.
1 Protected by U.S. Patent 6,703,961.
Rev. B Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Technical Support www.analog.com
AD7688 Data Sheet
Rev. B | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Application Diagram ........................................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications ....................................................................... 5
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Terminology ...................................................................................... 8
Typical Performance Characteristics ............................................. 9
Circuit Information .................................................................... 12
Converter Operation .................................................................. 12
Typical Connection Diagram ................................................... 13
Analog Input ............................................................................... 14
Driver Amplifier Choice ........................................................... 15
Single-to-Differential Driver .................................................... 15
Voltage Reference Input ............................................................ 15
Power Supply ............................................................................... 15
Supplying the ADC from the Reference .................................. 16
Digital Interface .......................................................................... 16
CS MODE 3-Wire, No BUSY Indicator .................................. 17
CS Mode 3-Wire with BUSY Indicator ................................... 18
CS Mode 4-Wire, No BUSY Indicator ..................................... 19
CS Mode 4-Wire with BUSY Indicator ................................... 20
Chain Mode, No BUSY Indicator ............................................ 21
Chain Mode with BUSY Indicator ........................................... 22
Application Hints ........................................................................... 23
Layout .......................................................................................... 23
Evaluating the AD7688 Performance ...................................... 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 25
REVISION HISTORY
6/14—Rev. A to Rev. B
Added Patent Footnote .................................................................... 1
Change to Evaluating the AD7688 Performance Section ......... 23
Updated Outline Dimensions (Dimensions Not Changed,
Lead-to-Pad Dimension Updated for JEDEC Compliance) ..... 24
Changes to Ordering Guide .......................................................... 25
2/11—Rev. 0 to Rev. A
Deleted QFN in Development Note ............................ Throughout
Changes to Table 5 ............................................................................ 6
Added Thermal Resistance Section and Table 6 .......................... 6
Changes to Figure 6 and Table 7 ..................................................... 7
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 25
4/05—Revision 0: Initial Version
Data Sheet AD7688
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range IN+ − IN− −VREF +VREF V
Absolute Input Voltage
IN+, IN−
−0.1
V
REF
+ 0.1
V
Common-Mode Input Range IN+, IN− 0 VREF/2 VREF/2 + 0.1 V
Analog Input CMRR fIN = 250 kHz 65 dB
Leakage Current at 25°C Acquisition phase 1 nA
Input Impedance See the Analog Input section
ACCURACY
No Missing Codes 16 Bits
Differential Linearity Error −1 ±0.4 +1 LSB1
Integral Linearity Error −1.5 ±0.4 +1.5 LSB
Transition Noise
REF = VDD = 5 V
0.4
LSB
Gain Error2, TMIN to TMAX ±2 ±6 LSB
Gain Error Temperature Drift ±0.3 ppm/°C
Zero Error2, TMIN to TMAX ±0.1 ±1.6 mV
Zero Temperature Drift ±0.3 ppm/°C
Power Supply Sensitivity
VDD = 5 V ± 5%
±0.05
LSB
THROUGHPUT
Conversion Rate 0 500 kSPS
Transient Response
Full-scale step
400
ns
AC ACCURACY
Dynamic Range VREF = 5 V 95.8 96.5 dB3
Signal-to-Noise
f
IN
= 20 kHz, V
REF
= 5 V
94
95.5
dB
fIN = 20 kHz, VREF = 5 V 92.5 dB
Spurious-Free Dynamic Range fIN = 20 kHz −118 dB
Total Harmonic Distortion fIN = 20 kHz −118 dB
Signal-to-(Noise + Distortion) fIN = 20 kHz, VREF = 5 V 93.5 95 dB
fIN = 20 kHz, VREF = 5 V, −60 dB input 36.5 dB
Intermodulation Distortion4 115 dB
1 LSB means least significant bit. With the ±5 V input range, one LSB is 152.6 µV.
2 See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference.
3All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
4 fIN1 = 21.4 kHz, fIN2 = 18.9 kHz, each tone at −7 dB below full-scale.
Rev. B | Page 3 of 28
AD7688 Data Sheet
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted.
Table 3.
Parameter Conditions Min Typ Max Unit
REFERENCE
Voltage Range 0.5 VDD + 0.3 V
Load Current 500 kSPS, REF = 5 V 100 µA
SAMPLING DYNAMICS
−3 dB Input Bandwidth 9 MHz
Aperture Delay VDD = 5 V 2.5 ns
DIGITAL INPUTS
Logic Levels
VIL –0.3 +0.3 × VIO V
VIH 0.7 × VIO VIO + 0.3 V
IIL −1 +1 µA
IIH −1 +1 µA
DIGITAL OUTPUTS
Data Format Serial 16 bits twos complement
Pipeline Delay Conversion results available immediately
after completed conversion
VOL ISINK = +500 µA 0.4 V
V
OH
I
SOURCE
= −500 µA
VIO − 0.3
V
POWER SUPPLIES
VDD Specified performance 4.5 5.5 V
VIO
Specified performance
2.3
VDD + 0.3
V
VIO Range 1.8 VDD + 0.3 V
Standby Current1, 2 VDD and VIO = 5 V, 25°C 1 50 nA
Power Dissipation VDD = 5 V, 100 SPS throughput 3.75 µW
VDD = 5 V, 100 kSPS throughput 3.75 4.3 mW
VDD = 5 V, 500 kSPS throughput
21.5
mW
TEMPERATURE RANGE3
Specified Performance TMIN to TMAX −40 +85 °C
1 With all digital inputs forced to VIO or GND as required.
2 During acquisition phase.
3 Contact sales for extended temperature range.
Rev. B | Page 4 of 28
Data Sheet AD7688
TIMING SPECIFICATIONS
−40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
See Figure 3 and Figure 4 for load conditions.
Table 4.
Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available
t
CONV
0.5
1.6
µs
Acquisition Time tACQ 400 ns
Time Between Conversions tCYC 2 µs
CNV Pulse Width (CS Mode) tCNVH 10 ns
SCK Period (CS Mode) tSCK 15 ns
SCK Period (Chain Mode)
t
SCK
VIO Above 4.5 V 17 ns
VIO Above 3 V 18 ns
VIO Above 2.7 V 19 ns
VIO Above 2.3 V 20 ns
SCK Low Time tSCKL 7 ns
SCK High Time
t
SCKH
7
ns
SCK Falling Edge to Data Remains Valid tHSDO 5 ns
SCK Falling Edge to Data Valid Delay tDSDO
VIO Above 4.5 V 14 ns
VIO Above 3 V 15 ns
VIO Above 2.7 V 16 ns
VIO Above 2.3 V 17 ns
CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN
VIO Above 4.5 V 15 ns
VIO Above 2.7 V 18 ns
VIO Above 2.3 V 22 ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
t
DIS
25
ns
SDI Valid Setup Time from CNV Rising Edge (CS Mode) tSSDICNV 15 ns
SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 5 ns
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
t
SSDISCK
3
ns
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 4 ns
SDI High to SDO High (Chain Mode with BUSY indicator) tDSDOSDI
VIO Above 4.5 V 15 ns
VIO Above 2.3 V 26 ns
Rev. B | Page 5 of 28
AD7688 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Analog Inputs
IN+
1
, IN−
1
GND − 0.3 V to VDD + 0.3 V
or ±130 mA
REF GND − 0.3 V to VDD + 0.3 V
Supply Voltages
VDD, VIO to GND −0.3 V to +7 V
VDD to VIO
±7 V
Digital Inputs to GND −0.3 V to VIO + 0.3 V
Digital Outputs to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Lead Temperature Range JEDEC J-STD-20
1 See the Analog Input section.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 6. Thermal Resistance
Package Type θJA θJC Unit
10-Lead LFCSP 48.7 2.96 °C
10-Lead MSOP 200 44 °C
ESD CAUTION
500µA I
OL
500µA I
OH
1.4V
TO SDO C
L
50pF
02973-003
Figure 3. Load Circuit for Digital Interface Timing
30% VIO 70% VIO
2V OR VIO – 0.5V1
0.8V OR 0.5V2
0.8V OR 0.5V2
2V OR VIO – 0.5V1
t
DELAY
t
DELAY
02973-004
12V IF VIO ABOVE 2.5V, VIO– 0.5V IF VIO BELOW 2.5V.
20.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
Figure 4. Voltage Levels for Timing
Rev. B | Page 6 of 28
Data Sheet AD7688
Rev. B | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
02973-005
REF
1
VDD
2
IN+
3
IN–
4
GND
5
VIO
10
SDI
9
SCK
8
SDO
7
CNV
6
AD7688
TOP VIEW
(Not to Scale)
Figure 5. 10-Lead MSOP Pin Configuration
02973-006
1REF
2VDD
3IN+
4IN–
5GND
10 VIO
9SDI
8SCK
7SDO
6 CNV
NOTES
1. F O R T HE LF CSP PACKAG E O NLY,
THE EXPOSED PADDLE MUST BE
CONNE CTE D TO G N D.
TOP VIEW
(No t to Scale)
AD7688
Figure 6. 10-Lead LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Type1 Function
1 REF AI
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should
be decoupled closely to the pin with a 10 μF capacitor.
2 VDD P Power Supply.
3 IN+ AI Differential Positive Analog Input.
4 IN− AI Differential Negative Analog Input.
5 GND P Power Supply Ground.
6 CNV DI
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
selects the interface mode, chain or CS. In CS mode, it enables the SDO pin when low. In chain mode, the
data should be read when CNV is high.
7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
9 SDI DI
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to
daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on
SDI is output on SDO with a delay of 16 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY
indicator feature is enabled.
10 VIO P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V,
or 5 V).
EPAD N/A For the LFCSP package only, the exposed paddle must be connected to GND.
1AI = Analog Input, DI = Digital Input, DO = Digital Output, P = Power, and N/A = not applicable.
AD7688 Data Sheet
TERMINOLOGY
Integral Nonlinearity Error (INL)
It refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (Figure 25).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Zero Error
It is the difference between the ideal midscale voltage, that is, 0
V, from the actual voltage producing the midscale output code,
that is, 0 LSB.
Gain Error
The first transition (from 100 . . . 00 to 100 . . . 01) should occur
at a level ½ LSB above nominal negative full scale (−4.999924 V
for the ±5 V range). The last transition (from 011…10 to
011…11) should occur for an analog voltage 1½ LSB below the
nominal full scale (+4.999771 V for the ±5 V range.) The gain
error is the deviation of the difference between the actual level
of the last transition and the actual level of the first transition
from the difference between the ideal levels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) by the following formula
ENOB = (S/[N + D]dB − 1.76)/6.02
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Dynamic Range
It is the ratio of the rms value of the full scale to the total rms
noise measured with the inputs shorted together. The value for
dynamic range is expressed in dB.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Signal-to-(Noise + Distortion) Ratio (S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in dB.
Aperture Delay
Aperture delay is the measure of the acquisition performance. It
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.
Transient Response
It is the time required for the ADC to accurately acquire its
input after a full-scale step function was applied.
Rev. B | Page 8 of 28
Data Sheet AD7688
TYPICAL PERFORMANCE CHARACTERISTICS
CODE
INL (LSB)
1.5
1.0
0.5
0
–0.5
–1.0
–1.5 0 16384 32768 49152 65535
02973-001
POSITIVE INL = +0.31LSB
NEGATIVE INL = –0.39LSB
Figure 7. Integral Nonlinearity vs. Code
02973-007
COUNTS
300000
250000
150000
200000
100000
50000
0
CODE IN HEX 73 74 756F 70 71 72
0 0 2930 0 0
256159
2031
VDD = REF = 5V
Figure 8. Histogram of a DC Input at the Code Center
FREQUENCY (kHz)
AMPLITUDE (dB of Full Scale)
0
–20
–40
–60
–80
–100
–120
–160
–140
–180 025 50 75 100 125 150 200175 225 250
02973-008
16384 POINT FFT
VDD = REF = 5V
F
S
= 500KSPS
F
IN
= 2kHz
SNR = 95.6dB
THD = –117.7dB
SFDR = –117.9dB
2nd HARM = –125dB
3rd HARM = –119dB
Figure 9. FFT Plot
CODE
DNL (LSB)
1.5
1.0
0.5
0
–0.5
–1.0
–1.5 0 16384 32768 49152 65535
02973-009
POSITIVE DNL = +0.37LSB
NEGATIVE DNL = –0.21LSB
Figure 10. Differential Nonlinearity vs. Code
02973-010
COUNTS
160000
120000
140000
100000
80000
40000
20000
60000
0
CODE IN HEX
74 7671 73
0
72
0
75
0 0
136187
124933
VDD = REF = 5V
Figure 11. Histogram of a DC Input at the Code Transition
02973-011
INPUT LEVEL (dB) 0–10 –8 –6 –4 –2
SNR (dB)
100
99
98
97
96
95
94
93
92
91
90
Figure 12. SNR vs. Input Level
Rev. B | Page 9 of 28
AD7688 Data Sheet
02973-012
REFERENCE VOLTAGE (V) 5.52.3 2.7 3.5 4.3 5.13.1 3.9 4.7
SNR, S/(N + D) (dB)
100
95
85
90
70
SNR
ENOB
ENOB (Bits)
17.0
15.0
16.0
14.0
13.0
S/[N + D]
Figure 13. SNR, S/(N + D), and ENOB vs. Reference Voltage
02973-013
TEMPERATURE (°C) 125–55 –35 –15 5 25 45 65 85 105
SNR (dB)
100
95
90
85
80
VREF = 5V
Figure 14. SNR vs. Temperature
02973-014
FREQUENCY (kHz) 2000 50 100 150
S/(N + D) (dB)
100
95
85
90
80
75
70
VREF = 5V,–10dB
VREF = 5V,–1dB
Figure 15. S/(N + D) vs. Frequency
02973-015
REFERENCE VOLTAGE (V) 5.52.3 2.7 3.5 4.3 5.13.1 3.9 4.7
THD, SFDR (dB)
–100
–110
–105
–115
–120
–125
–130
SFDR
THD
Figure 16. THD, SFDR vs. Reference Voltage
02973-016
TEMPERATURE (°C) 125–55 –35 –15 5 25 45 65 85 105
THD (dB)
–90
–100
–110
–120
–130
VREF = 5V
Figure 17. THD vs. Temperature
02973-017
FREQUENCY (kHz) 2000 50 100 150
THD (dB)
–60
–70
–90
–80
–100
–110
–120
VREF = 5V,–10dB
VREF = 5V,–1dB
Figure 18. THD vs. Frequency
Rev. B | Page 10 of 28
Data Sheet AD7688
SUPPLY (V)
OPERATING CURRENT (µA)
1000
750
500
250
0
4.50 4.75 5.00 5.25 5.5
02973-018
VIO
VDD
f
S
= 100kSPS
Figure 19. Operating Currents vs. Supply
TEMPERATURE (°C)
POWER-DOWN CURRENT (nA)
1000
750
500
250
0
–55 –35 –15 5 25 45 65 85 105 125
02973-019
VDD + VIO
Figure 20. Power-Down Currents vs. Temperature
TEMPERATURE (°C)
OPERATING CURRENT (µA)
1000
750
500
250
0
–55 –35 –15 5 25 45 65 85 105 125
02973-020
VIO
VDD
f
S
= 100kSPS
Figure 21. Operating Currents vs. Temperature
02973-021
TEMPERATURE (°C) 125–55 –35 –15 5 25 45 65 85 105
OFFSET, GAIN ERROR (LSB)
6
4
2
0
–2
–4
–6
GAIN ERROR
OFFSET ERROR
Figure 22. Offset and Gain Error vs. Temperature
02973-022
SDO CAPACITIVE LOAD (pF) 1200 20 40 60 80 100
T
DSDO
DELAY (ns)
25
20
15
10
5
0
VDD = 5V, 85°C
VDD = 5V, 25°C
Figure 23. tDSDO Delay vs. Capacitance Load and Supply
Rev. B | Page 11 of 28
AD7688 Data Sheet
SW+MSB
16,384C
IN+
LSB
COMP CONTROL
LOGIC
SWITCHES CONTROL
BUSY
OUTPUT CODE
CNV
REF
GND
IN–
4C 2C C C32,768C
SW–MSB
16,384C
LSB
4C 2C C C32,768C
02973-023
Figure 24. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7688 is a fast, low power, single-supply, precise 16-bit
ADC using a successive approximation architecture.
The AD7688 is capable of converting 500,000 samples per
second (500 kSPS) and powers down between conversions.
When operating at 100 SPS, for example, it consumes 3.75 µW
typically, ideal for battery-powered applications.
The AD7688 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
The AD7688 is specified from 4.5 V to 5.5 V and can be
interfaced to any of the 1.8 V to 5 V digital logic family. It is
housed in a 10-lead MSOP or a tiny 10-lead LFCSP that
combines space savings and allows flexible configurations.
It is pin-for-pin-compatible with the AD7685, AD7686, and
AD7687.
CONVERTER OPERATION
The AD7688 is a successive approximation ADC based on a
charge redistribution DAC. Figure 24 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the IN+ and IN− inputs. When the
acquisition phase is complete and the CNV input goes high, a
conversion phase is initiated. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. Therefore, the differential voltage between the
inputs IN+ and IN− captured at the end of the acquisition phase
is applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and REF, the comparator input varies by
binary weighted voltage steps (VREF/2, VREF/4 . . . VREF/65536).
The control logic toggles these switches, starting with the MSB,
in order to bring the comparator back into a balanced
condition. After the completion of this process, the part returns
to the acquisition phase and the control logic generates the
ADC output code and a BUSY signal indicator.
Because the AD7688 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Rev. B | Page 12 of 28
Data Sheet AD7688
Rev. B | Page 13 of 28
Transfer Functions
The ideal transfer characteristic for the AD7688 is shown in
Figure 25 and Table 8.
100...000
100...001
100...010
011...101
011...110
011...111
ADC CODE (TWOS COMPLEMENT)
ANALOG INPUT
+FSR – 1.5 LSB
+FSR – 1 LSB
–FSR + 1 LSB
–FSR
–FSR + 0.5 LSB
02973-024
Figure 25. ADC Ideal Transfer Function
Table 8. Output Codes and Ideal Input Voltages
Description
Analog Input
VREF = 5 V Digital Output Code Hexa
FSR – 1 LSB +4.999847 V 7FFF1
Midscale + 1 LSB +152.6 μV 0001
Midscale 0 V 0000
Midscale – 1 LSB −152.6 μV FFFF
–FSR + 1 LSB −4.999847 V 8001
–FSR −5 V 80002
TYPICAL CONNECTION DIAGRAM
Figure 26 shows an example of the recommended connection
diagram for the AD7688 when multiple supplies are available.
1 This is also the code for an overranged analog input (VIN+ − VIN− above VREF −
VGND).
2 This is also the code for an underranged analog input (VIN+ − VIN− below −VREF
+ VGND).
AD7688
REF
GND
VDD
IN–
IN+ VIOSDI
SCK
SDO
CNV
3- OR 4-WIRE INTERFACE
5
100nF
100nF 5V
10F
2
7V
7V
–2V
1.8V TO VDD
REF
1
0 TO VREF
33
2.7nF
3
4
7V
–2V
VREF TO 0
33
2.7nF
3
4
02973-025
1
SEE REFERENCE SECTION FOR REFERENCE SELECTION.
2
C
REF
IS USUALLY A 10F CERAMIC CAPACITOR (X5R).
3
SEE DRIVER AMPLIFIER CHOICE SECTION.
4
OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
5
SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE.
Figure 26. Typical Application Diagram with Multiple Supplies
AD7688 Data Sheet
ANALOG INPUT
Figure 27 shows an equivalent circuit of the input structure of
the AD7688.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs IN+ and IN−. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V because this causes these diodes to begin to forward-
bias and start conducting current. These diodes can handle a
forward-biased current of 130 mA maximum. For instance,
these conditions could eventually occur when the input buffer’s
(U1) supplies are different from VDD. In such a case, an input
buffer with a short-circuit current limitation can be used to
protect the part.
CIN
RIN
D1
D2
CPIN
IN+
OR IN–
GND
VDD
02973-026
Figure 27. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected,
as shown in Figure 28, which represents the typical CMRR over
frequency.
02973-027
FREQUENCY (kHz) 100001 10 100 1000
CMRR (dB)
80
70
60
VDD = 5V
Figure 28. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog
inputs (IN+ or IN−) can be modeled as a parallel combination
of capacitor, CPIN, and the network formed by the series
connection of RIN and CIN. CPIN is primarily the pin capacitance.
RIN is typically 600 Ω and is a lumped component made up of
some serial resistors and the on resistance of the switches. CIN is
typically 30 pF and is mainly the ADC sampling capacitor.
During the conversion phase, where the switches are opened,
the input impedance is limited to CPIN. RIN and CIN make a
1-pole, low-pass filter that reduces undesirable aliasing effects
and limits the noise.
When the source impedance of the driving circuit is low, the
AD7688 can be driven directly. Large source impedances
significantly affect the ac performance, especially total
harmonic distortion (THD). The dc performances are less
sensitive to the input impedance. The maximum source
impedance depends on the amount of THD that can be
tolerated. The THD degrades as a function of the source
impedance and the maximum input frequency, as shown in
Figure 29.
FREQUENCY (kHz)
THD (dB)
–60
–70
–80
–90
–100
–110
–120 0 25 50 75 100
02973-028
R
S
= 250Ω
R
S
= 100Ω
R
S
= 50Ω
R
S
= 33Ω
Figure 29. THD vs. Analog Input Frequency and Source Resistance
Rev. B | Page 14 of 28
Data Sheet AD7688
DRIVER AMPLIFIER CHOICE
Although the AD7688 is easy to drive, the driver amplifier
needs to meet the following requirements:
• The noise generated by the driver amplifier needs to be
kept as low as possible in order to preserve the SNR and
transition noise performance of the AD7688. Note that the
AD7688 has a noise much lower than most of the other
16-bit ADCs and, therefore, can be driven by a noisier op
amp while preserving the same or better system perform-
ance. The noise coming from the driver is filtered by the
AD7688 analog input circuit 1-pole, low-pass filter made
by RIN and CIN or by the external filter, if one is used.
Because the typical noise of the AD7688 is 53 µV rms,
the SNR degradation due to the amplifier is
+
=
−2
2
)
(
2
π
5
53
20log
N
3dB
LOSS
Ne
f
SNR
3
where:
f–3dB is the input bandwidth in MHz of the AD7688
(9 MHz) or the cutoff frequency of the input filter, if one
is used.
N is the noise gain of the amplifier (for example, +1 in
buffer configuration).
eN is the equivalent input noise voltage of the op amp,
in nV/√Hz.
• For ac applications, the driver should have a THD
performance commensurate with the AD7688. Figure 18
shows the THD vs. frequency that the driver should
exceed.
• For multichannel multiplexed applications, the driver
amplifier and the AD7688 analog input circuit must settle
for a full-scale step onto the capacitor array at a 16-bit level
(0.0015%, 15 ppm). In the amplifier’s data sheet, settling at
0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 16-bit level
and should be verified prior to driver selection.
Table 9. Recommended Driver Amplifiers
Amplifier Typical Application
AD8021 Very low noise and high frequency
AD8022
Low noise and high frequency
OP184 Low power, low noise, and low frequency
AD8605, AD8615 5 V single-supply, low power
AD8519 Small, low power and low frequency
AD8031 High frequency and low power
SINGLE-TO-DIFFERENTIAL DRIVER
For applications using a single-ended analog signal, either
bipolar or unipolar, a single-ended-to-differential driver
allows for a differential input into the part. The schematic is
shown in Figure 30. When provided a single-ended input signal,
this configuration produces a differential ±VREF with midscale
at VREF/2.
U2
10kΩ
590Ω
AD7688
IN+
IN–
REF
U1
ANALOG INPUT
(±10V, ±5V, ..)
590Ω
10µF
100nF
10kΩ
VREF
VREF
590Ω
100nF
VREF
02973-029
Figure 30. Single-Ended-to-Differential Driver Circuit
VOLTAGE REFERENCE INPUT
The AD7688 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source, for
example, a reference buffer using the AD8031 or the AD8605, a
10 µF (X5R, 0805 size) ceramic chip capacitor is appropriate for
optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 µF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
If desired, smaller reference decoupling capacitor values down
to 2.2 µF can be used with a minimal impact on performance,
especially DNL.
Regardless, there is no need for an additional lower value
ceramic decoupling capacitor (for example, 100 nF) between the
REF and GND pins.
POWER SUPPLY
The AD7688 is specified at 4.5 V to 5.5 V. It has, unlike other
low voltage converters, a low enough noise to design a 16-bit
resolution system with low supply and respectable performance.
It uses two power supply pins: a core supply VDD and a digital
input/output interface supply VIO. VIO allows direct interface
with any logic between 1.8 V and VDD. To reduce the supplies
needed, the VIO and VDD can be tied together. The AD7688 is
independent of power supply sequencing between VIO and
VDD. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in Figure 31,
which represents PSRR over frequency.
Rev. B | Page 15 of 28
AD7688 Data Sheet
02973-030
FREQUENCY (kHz) 100001 100010 100
PSRR (dB)
95
90
85
80
75
70
65
60
Figure 31. PSRR vs. Frequency
The AD7688 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, as shown in Figure 32. This makes the part
ideal for low sampling rate (even a few Hz) and low battery-
powered applications.
SAMPLING RATE (SPS)
OPERATING CURRENT (µA)
1000
10
0.1
0.00110 100 1000 10000 100000 1000000
02973-031
VIO
VDD
Figure 32. Operating Currents vs. Sampling Rate
SUPPLYING THE ADC FROM THE REFERENCE
For simplified applications, the AD7688, with its low operating
current, can be supplied directly using the reference circuit
shown in Figure 33. The reference line can be driven by either:
• The system power supply directly.
• A reference voltage with enough current output capability,
such as the ADR43x.
• A reference buffer, such as the AD8031, which can also
filter the system power supply, as shown in Figure 33.
AD8031
AD7688
VIO
REF VDD
10µF1µF
10Ω
10kΩ
5V
5V
5V
1µF
1
02973-032
1
OPTIONAL REFERENCE BUFFER AND FILTER.
Figure 33. Example of Application Circuit
DIGITAL INTERFACE
Though the AD7688 has a reduced number of pins, it offers
flexibility in its serial interface modes.
The AD7688, when in CS mode, is compatible with SPI, QSPI,
digital hosts, and DSPs, e.g., Blackfin® ADSP-BF53x or ADSP-
219x. This interface can use either 3-wire or 4-wire. A 3-wire
interface using the CNV, SCK, and SDO signals minimizes
wiring connections useful, for instance, in isolated applications.
A 4-wire interface using the SDI, CNV, SCK, and SDO signals
allows CNV, which initiates the conversions, to be independent
of the readback timing (SDI). This is useful in low jitter
sampling or simultaneous sampling applications.
The AD7688, when in chain mode, provides a daisy chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is always selected.
In either mode, the AD7688 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be
used as a BUSY signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a BUSY indicator,
the user must time out the maximum conversion time prior to
readback.
The BUSY indicator feature is enabled as:
• In the CS mode, if CNV or SDI is low when the ADC
conversion ends (Figure 37 and Figure 41).
• In the chain mode, if SCK is high during the CNV rising edge
(Figure 45).
Rev. B | Page 16 of 28
Data Sheet AD7688
CS MODE 3-WIRE, NO BUSY INDICATOR
This mode is usually used when a single AD7688 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 34 and the corresponding timing is given in
Figure 35.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues to
completion irrespective of the state of CNV. For instance, it
could be useful to bring CNV low to select other SPI devices,
such as analog multiplexers, but CNV must be returned high
before the minimum conversion time and held high until the
maximum conversion time to avoid the generation of the BUSY
signal indicator. When the conversion is complete, the AD7688
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
are then clocked by subsequent SCK falling edges. The data is
valid on both SCK edges. Although the rising edge can be used
to capture the data, a digital host using the SCK falling edge
allows a faster reading rate provided it has an acceptable hold
time. After the 16th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
CNV
SCK
SDOSDI DATA IN
CLK
CONVERT
VIO DIGITAL HOST
AD7688
02973-033
Figure 34. CS Mode 3-Wire, No BUSY Indicator
Connection Diagram (SDI High)
SDO D15 D14 D13 D1 D0
tDIS
SCK
12 3 14 15 16
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
CONVERSION
ACQUISITION
tCONV
tCYC
ACQUISITION
SDI = 1
tCNVH
tACQ
tEN
02973-034
Figure 35. CS Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High)
Rev. B | Page 17 of 28
AD7688 Data Sheet
CS MODE 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7688 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 36 and the
corresponding timing is given in Figure 37.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV could be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time and
held low until the maximum conversion time to guarantee the
generation of the BUSY signal indicator. When the conversion
is complete, SDO goes from high impedance to low. With a
pull-up on the SDO line, this transition can be used as an
interrupt signal to initiate the data reading controlled by the
digital host. The AD7688 then enters the acquisition phase and
powers down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate provided it has an acceptable hold time. After the optional
17th SCK falling edge, or when CNV goes high, whichever is
earlier, SDO returns to high impedance.
If multiple AD7688s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
DATA IN
IRQ
CLK
CONVERT
VIO DIGITAL HOST
02973-035
47kΩ
CNV
SCK
SDOSDI
VIO
AD7688
Figure 36. CS Mode 3-Wire with BUSY Indicator
Connection Diagram (SDI High)
SDO
D15 D14 D1 D0
t
DIS
SCK
1 2 3 15 16 17
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
CNV
CONVERSIONACQUISITION
t
CONV
t
CYC
t
CNVH
t
ACQ
ACQUISITION
SDI = 1
02973-036
Figure 37. CS Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High)
Rev. B | Page 18 of 28
Data Sheet AD7688
CS MODE 4-WIRE, NO BUSY INDICATOR
This mode is usually used when multiple AD7688s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7688s is shown in
Figure 38 and the corresponding timing is given in Figure 39.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time and held high until the maximum conversion time to
avoid the generation of the BUSY signal indicator. When the
conversion is complete, the AD7688 enters the acquisition
phase and powers down. Each ADC result can be read by
bringing low its SDI input which consequently outputs the MSB
onto SDO. The remaining data bits are then clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate provided it has an acceptable hold time. After the 16th SCK
falling edge, or when SDI goes high, whichever is earlier, SDO
returns to high impedance and another AD7688 can be read.
DATA IN
CLK
CS1
CONVERT
CS2
DIGITAL HOST
02973-037
CNV
SCK
SDO
SDI AD7688
CNV
SCK
SDO
SDI AD7688
Figure 38. CS Mode 4-Wire, No BUSY Indicator Connection Diagram
SDO D15 D14 D13 D1 D0
tDIS
SCK 1 2 3 30 31 32
tHSDO tDSDO
tEN
CONVERSIONACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI(CS1)
CNV
tSSDICNV
tHSDICNV
D1
14 15
tSCK
tSCKL
tSCKH
D0 D15 D14
17 1816
SDI(CS2)
02973-038
Figure 39. CS Mode 4-Wire, No BUSY Indicator Serial Interface Timing
Rev. B | Page 19 of 28
AD7688 Data Sheet
CS MODE 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7688 is connected
to an SPI-compatible digital host, which has an interrupt input,
and it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 40 and the
corresponding timing is given in Figure 41.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the BUSY signal indicator. When
the conversion is complete, SDO goes from high impedance to
low. With a pull-up on the SDO line, this transition can be used
as an interrupt signal to initiate the data readback controlled by
the digital host. The AD7688 then enters the acquisition phase
and powers down. The data bits are then clocked out, MSB first,
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate provided it has an acceptable hold time. After the optional
17th SCK falling edge, or SDI going high, whichever is earlier,
the SDO returns to high impedance.
DATA IN
IRQ
CLK
CONVERT
CS1
VIO DIGITAL HOST
02973-039
47kΩ
CNV
SCK
SDOSDI
AD7688
Figure 40. CS Mode 4-Wire with BUSY Indicator Connection Diagram
SDO D15 D14 D1 D0
tDIS
SCK 1 2 3 15 16 17
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
CONVERSIONACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI
CNV
tSSDICNV
tHSDICNV
02973-040
Figure 41. CS Mode 4-Wire with BUSY Indicator Serial Interface Timing
Rev. B | Page 20 of 28
Data Sheet AD7688
CHAIN MODE, NO BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7688s on a
3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7688s is shown in
Figure 42 and the corresponding timing is given in Figure 43.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the BUSY indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7688 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are then clocked by subsequent SCK falling edges.
For each ADC, SDI feeds the input of the internal shift register
and is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N clocks are required to
readback the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and, consequently more AD7688s in the chain, provided
the digital host has an acceptable hold time. The maximum
conversion rate may be reduced due to the total readback time.
For instance, with a 3 ns digital host set-up time and 3 V
interface, up to four AD7688s running at a conversion rate of
360 kSPS can be daisy-chained on a 3-wire port.
CLK
CONVERT
DATA IN
DIGITAL HOST
02973-041
CNV
SCK
SDO
SDI
AD7688
B
CNV
SCK
SDO
SDI
AD7688
A
Figure 42. Chain Mode, No BUSY Indicator Connection Diagram
SDO
A
= SDI
B
D
A
15 D
A
14 D
A
13
SCK 1 2 3 30 31 32
t
SSDISCK
t
HSDISC
t
EN
CONVERSIONACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
CNV
D
A
1
14 15
t
SCK
t
SCKL
t
SCKH
D
A
0
17 1816
SDI
A
= 0
SDO
B
D
B
15 D
B
14 D
B
13 D
A
1D
B
1 D
B
0 D
A
15 D
A
14
t
HSDO
t
DSDO
t
SSCKCNV
t
HSCKCNV
D
A
0
02973-042
Figure 43. Chain Mode, No BUSY Indicator Serial Interface Timing
Rev. B | Page 21 of 28
AD7688 Data Sheet
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7688s
on a 3-wire serial interface while providing a BUSY indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter
applications or for systems with a limited interfacing capacity.
Data readback is analogous to clocking a shift register.
A connection diagram example using three AD7688s is shown
in Figure 44 and the corresponding timing is given in Figure 45.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the BUSY indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the nearend ADC (ADC C in
Figure 44) SDO is driven high. This transition on SDO can be
used as a BUSY indicator to trigger the data readback controlled
by the digital host. The AD7688 then enters the acquisition
phase and powers down. The data bits stored in the internal
shift register are then clocked out, MSB first, by subsequent
SCK falling edges. For each ADC, SDI feeds the input of the
internal shift register and is clocked by the SCK falling edge.
Each ADC in the chain outputs its data MSB first, and 16 × N +
1 clocks are required to readback the N ADCs. Although the
rising edge can be used to capture the data, a digital host using
the SCK falling edge allows a faster reading rate and
consequently more AD7688s in the chain, provided the digital
host has an acceptable hold time. For instance, with a 3 ns
digital host setup time and 3 V interface, up to four AD7688s
running at a conversion rate of 360 kSPS can be daisy-chained
to a single 3-wire port.
CLK
CONVERT
DATA IN
IRQ
DIGITAL HOST
02973-043
CNV
SCK
SDOSDI
AD7688
C
CNV
SCK
SDOSDI
AD7688
A
CNV
SCK
SDOSDI
AD7688
B
Figure 44. Chain Mode with BUSY Indicator Connection Diagram
SDOA = SDIBDA15 DA14 DA13
SCK 1 2 3 35 47 48
t
EN
CONVERSION
ACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
CNV = SDIA
DA1
415
t
SCK
t
SCKH
t
SCKL
DA0
17 34
16
SDOB = SDICDB15 DB14 DB13 DA1
DB1DB0DA15 DA14
49
t
SSDISCK
t
HSDISC
t
HSDO
t
DSDO
SDOCDC15 DC14 DC13 DA1 DA0DC1 DC0 DA14
19 31 3218 33
DB1 DB0DA15DB15 DB14
t
DSDOSDI
t
SSCKCNV
t
HSCKCNV
02973-044
DA0
t
DSDOSDI
t
DSDOSDI
t
DSDOSDI
t
DSDOSDI
Figure 45. Chain Mode with BUSY Indicator Serial Interface Timing
Rev. B | Page 22 of 28
Data Sheet AD7688
APPLICATION HINTS
LAYOUT
The printed circuit board that houses the AD7688 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7688, with all its analog signals on the left side and all its
digital signals on the right side, eases this task.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7688 is used as a shield. Fast switching signals, such as CNV
or clocks, should never run near analog signal paths. Crossover
of digital and analog signals should be avoided.
At least one ground plane should be used. It could be common
or split between the digital and analog sections. In the latter
case, the planes should be joined underneath the AD7688s.
The AD7688 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and connecting it with wide, low impedance
traces.
Finally, the power supplies VDD and VIO of the AD7688
should be decoupled with ceramic capacitors (typically 100 nF)
placed close to the AD7688 and connected using short and wide
traces to provide low impedance paths and reduce the effect of
glitches on the power supply lines.
An example of layout following these rules is shown in
Figure 46 and Figure 47.
EVALUATING THE AD7688 PERFORMANCE
Other recommended layouts for the AD7688 are outlined
in the documentation of the evaluation board for the AD7688
(EVAL-AD7688SDZ). The evaluation board package includes
a fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the
EVAL-SDP-CD1Z.
02973-045
Figure 46. Example of Layout of the AD7688 (Top Layer)
02973-046
Figure 47. Example of Layout of the AD7688 (Bottom Layer)
Rev. B | Page 23 of 28
AD7688 Data Sheet
OUTLINE DIMENSIONS
COMPLIANT TOJEDEC STANDARDS MO-187-BA
091709-A
6°
0°
0.70
0.55
0.40
5
10
1
6
0.50BSC
0.30
0.15
1.10 MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN1
IDENTIFIER
15°MAX
0.95
0.85
0.75
0.15
0.05
Figure 48. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
2.48
2.38
2.23
0.50
0.40
0.30
10
1
6
5
0.30
0.25
0.20
PIN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.74
1.64
1.49
0.20 REF
0.05 M AX
0.02 NO M
0.50 BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
PIN 1
INDICATOR
(R 0. 15)
FO R P ROPE R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE P IN CO NFI GURAT IO N AND
FUNCTION DES CRIPTI ONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
02-05-2013-C
TOP VIEW BOTTOM VIEW
0.20 M I N
Figure 49. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
Rev. B | Page 24 of 28
Data Sheet AD7688
ORDERING GUIDE
Model1, 2, 3
Integral
Nonlinearity Temperature Range
Transport Media,
Quantity
Package
Description
Package
Option Branding
AD7688BRMZ ±1.5 LSB max –40°C to +85°C Tube, 50 10-Lead MSOP RM-10 C3K
AD7688BRMZRL7 ±1.5 LSB max –40°C to +85°C Reel, 1,000 10-Lead MSOP RM-10 C3K
AD7688BCPZRL ±1.5 LSB max –40°C to +85°C Reel, 5,000 10-Lead LFCSP_WD CP-10-9 #C04
AD7688BCPZRL7 ±1.5 LSB max –40°C to +85°C Reel, 1,500 10-Lead LFCSP_WD CP-10-9 #C04
EVAL-AD7688SDZ Evaluation Board
EVAL-SDP-CB1Z
Controller Board
1 Z = RoHS Compliant Part, # denotes RoHS compliant product, may be top or bottom marked.
2 The EVAL-AD7688SDZ can be used as a standalone evaluation board or in conjunction with the EVAL-SDP-CB1Z for evaluation/demonstration purposes.
3 The EVAL-SDP-CB1Z allows a PC to control and communicate with all Analog Devices evaluation boards ending in the SD designators.
Rev. B | Page 25 of 28
AD7688 Data Sheet
NOTES
Rev. B | Page 26 of 28
Data Sheet AD7688
NOTES
Rev. B | Page 27 of 28
