19-3631; Rev 0; 4/05 KIT ATION EVALU E L B A AVAIL 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs Features The MAX5894 programmable interpolating, modulating, 500Msps, dual digital-to-analog converter (DAC) offers superior dynamic performance and is optimized for highperformance wideband, single-carrier transmit applications. The device integrates a selectable 2x/4x/8x interpolating filter, a digital quadrature modulator, and dual 14-bit, high-speed DACs on a single integrated circuit. At 30MHz output frequency and 500Msps update rate, the in-band SFDR is 86dBc while consuming 1.1W. The device also delivers 73dB ACLR for two-carrier WCDMA at a 61.44MHz output frequency. The selectable interpolating filters allow lower input data rates while taking advantage of the high DAC update rates. These linear-phase interpolation filters ease reconstruction filter requirements and enhance the passband dynamic performance. Individual offset and gain programmability allow the user to calibrate out local oscillator (LO) feedthrough and sideband suppression errors generated by analog quadrature modulators. The MAX5894 features a fIM / 4 digital image-reject modulator. This modulator generates a quadrature-modulated IF signal that can be presented to an analog I/Q modulator to complete the upconversion process. A second digital modulation mode allows the signal to be frequency-translated with image pairs at fIM / 2 or fIM / 4. The MAX5894 features a standard 1.8V CMOS, 3.3V tolerant data input bus for easy interface. A 3.3V SPITM port is provided for mode configuration. The programmable modes include the selection of 2x/4x/8x interpolating filters, fIM / 2, fIM / 4 or no digital quadrature modulation with image rejection, channel gain and offset adjustment, and offset binary or two's complement data interface. Pin-compatible 12- and 16-bit devices are also available. Refer to the MAX5893 data sheet for the 12-bit version and the MAX5895 data sheet for the 16-bit version. 74dB ACLR at fOUT = 61.44MHz (Single-Carrier WCDMA) Meets 3G UMTS, cdma2000(R), GSM Spectral Masks (fOUT = 122MHz) Noise Spectral Density = -154dBFS/Hz at fOUT = 16MHz 91dBc SFDR at Low-IF Frequency (10MHz) 88dBc SFDR at High-IF Frequency (50MHz) Applications Base Stations: 3G UMTS, CDMA, and GSM Broadband Wireless Transmitters Broadband Cable Infrastructure Instrumentation and Automatic Test Equipment (ATE) Low Power: 886mW (fCLK = 250MHz) User Programmable Selectable 2x, 4x, or 8x Interpolating Filters <0.01dB Passband Ripple >99dB Stopband Rejection Selectable Real or Complex Modulator Operation Selectable Modulator LO Frequency: OFF, fIM / 2 or fIM / 4 Selectable Output Filter: Lowpass or Highpass Channel Gain and Offset Adjustment EV Kit Available (Order the MAX5894 EV Kit) Ordering Information PART TEMP RANGE PIN-PACKAGE PKG CODE MAX5894EGK -40C to +85C 68 QFN-EP* (10mm x 10mm) G6800-4 *EP = Exposed paddle. Selector Guide RESOLUTION (BITS) DAC UPDATE RATE (Msps) INPUT LOGIC MAX5893 12 500 CMOS MAX5894 14 500 CMOS MAX5895 16 500 CMOS MAX5898** 16 500 LVDS PART **Future product--contact factory for availability. Simplified Diagram Analog Quadrature Modulation Architectures 2x INTERPOLATING FILTERS DATA PORT B MODULATOR SPI is a trademark of Motorola, Inc. cdma2000 is a registered trademark of Telecommunications Industry Association. DATACLK 1x/2x/4x INTERPOLATING FILTERS Pin Configuration appears at end of data sheet. DATA SYNCH AND DEMUX DATA PORT A DAC DAC OUTI OUTQ ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX5894 General Description MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs ABSOLUTE MAXIMUM RATINGS DVDD1.8, AVDD1.8 to GND, DACREF ..................-0.3V to +2.16V AVDD3.3, AVCLK, DVDD3.3 to GND, DACREF ........-0.3V to +3.9V DATACLK, A0-A13, B0-B11, SELIQ/B13, DATACLK/B12, CS, RESET, SCLK, DIN and DOUT to GND, DACREF ...-0.3V to (DVDD3.3 + 0.3V) CLKP, CLKN to GND, DACREF..............-0.3V to (AVCLK + 0.3V) REFIO, FSADJ to GND, DACREF ........-0.3V to (AVDD3.3 + 0.3V) OUTIP, OUTIN, OUTQP, OUTQN to GND, DACREF..................-1V to (AVDD3.3 + 0.3V) DOUT, DATACLK, DATACLK/B12 Continuous Current........8mA Continuous Power Dissipation (TA = +70C) 68-Pin QFN (derate 41.7mW/C above +70C) (Note 1) ...................................................................3333.3mW Junction Temperature ......................................................+150C Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C Thermal Resistance JC (Note 1)....................................0.8C/W Note 1: Thermal resistance based on a multilayer board with 4 x 4 via array in exposed paddle area. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, dual-port mode, 50 double-terminated outputs, external reference at 1.25V, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution Differential Nonlinearity DNL Integral Nonlinearity INL Offset Error OS 0.003 LSB +0.01 0.03 GEFS -4 Gain-Error Drift Full-Scale Output Current Bits LSB 1.0 -0.01 Offset Drift Full-Scale Gain Error 14 0.5 -0.6 ppm/C +4 110 IOUTFS 2 Output Compliance %FS ppm/C 20 -0.5 %FS +1.1 mA V Output Resistance ROUT 1 M Output Capacitance COUT 5 pF DYNAMIC PERFORMANCE Maximum Clock Frequency fCLK Minimum Clock Frequency fCLK 500 Maximum DAC Update Rate fDAC fDAC = fCLK or fDAC = fCLK / 2 Minimum DAC Update Rate fDAC fDAC = fCLK or fDAC = fCLK / 2 Maximum Input Data Rate fDATA 500 Noise Spectral Density fDATACLK = 125MHz, fOUT = 16MHz, fOFFSET = 10MHz, 0dBFS MHz Msps 1 125 fDATACLK = 125MHz, fOUT = 16MHz, fOFFSET = 10MHz, -12dBFS 2 MHz 1 Msps MWps No interpolation -154 2x interpolation -154 4x interpolation -154 4x interpolation -151 _______________________________________________________________________________________ dBFS/ Hz 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs (DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, dual-port mode, 50 double-terminated outputs, external reference at 1.25V, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS fDATACLK = 125MHz, interpolation off, 0dBFS MIN 91 fOUT = 30MHz 85 fOUT = 50MHz In-Band SFDR (DC to fDATA / 2) SFDR fDATACLK = 125MHz, 2x interpolation, 0dBFS fDATACLK = 125MHz, 4x interpolation, 0dBFS fOUT = 10MHz Two-Tone IMD Four-Tone IMD ACLR for WCDMA (Note 3) TTIMD FTIMD ACLR UNITS 89 86 fOUT = 50MHz 85 fOUT = 10MHz 91 fOUT = 30MHz 86 dBc 88 No interpolation -102 2x interpolation -102 4x interpolation -102 2x interpolation, fIM / 4 complex fDATA = 125MHz, fOUT1 modulation = 79MHz, fOUT2 = 4x interpolation, 80MHz, -6.1dBFS fIM / 4 complex modulation MAX 73 77 fOUT = 30MHz fOUT = 50MHz fDATACLK = 125MHz, fOUT1 = 9MHz, fOUT2 = 10MHz, -6.1dBFS TYP fOUT = 10MHz -73 -75 dBc fDATACLK = 62.5MHz, fOUT1 = 9MHz, fOUT2 = 10MHz, -6.1dBFS 8x interpolation -99 fDATACLK = 62.5MHz, fOUT1 = 69MHz, fOUT2 = 70MHz, -6.1dBFS 8x interpolation, fIM / 4 complex modulation -70 8x, highpass fDATACLK = 62.5MHz, interpolation, fOUT1 = 179MHz, fOUT2 fIM / 4 complex = 180MHz, -6.1dBFS modulation -63 fDATACLK = 125MHz, fOUT spaced 1MHz apart from 32MHz, -12dBFS, 2x interpolation -95 fDATACLK = 61.44MHz, fOUT = baseband 4x interpolation 78 8x interpolation 78 fDATACLK = 122.88MHz, fOUT = 61.44MHz 2x interpolation, fIM / 4 complex modulation 74 fDATACLK = 122.88MHz, fOUT = 122.88MHz 4x interpolation, fIM / 4 complex modulation 69 dBc dB _______________________________________________________________________________________ 3 MAX5894 ELECTRICAL CHARACTERISTICS (continued) MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs ELECTRICAL CHARACTERISTICS (continued) (DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, dual-port mode, 50 double-terminated outputs, external reference at 1.25V, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C, unless otherwise noted.) (Note 2) PARAMETER Output Propagation Delay SYMBOL tPD CONDITIONS MIN TYP 1x interpolation (Note 4) 2.9 MAX UNITS ns Output Rise Time tRISE 10% to 90% (Note 5) 0.75 ns Output Fall Time tFALL 10% to 90% (Note 5) 1 ns Output Settling Time To 0.5% (Note 5) 11 ns Output Bandwidth -1dB bandwidth (Note 6) 240 MHz Passband Width 0.4 x fDATA Ripple < -0.01dB Stopband Rejection 0.604 x fDATA, 2x interpolation 100 0.604 x fDATA, 4x interpolation 100 0.604 x fDATA, 8x interpolation 100 1x interpolation 22 dB 2x interpolation 70 4x interpolation 146 8x interpolation 311 fOUT = DC - 80MHz, IOUTFS = 20mA 0.1 dB IOUTFS = 20mA 0.02 ppm/C fOUT = 60MHz, IOUTFS = 20mA 0.13 Deg Phase/C fOUT = 60MHz, IOUTFS = 20mA 0.006 Deg/C Data Latency Clock Cycles DAC INTERCHANNEL MATCHING Gain Match Gain-Match Tempco Phase Match Phase-Match Tempco Gain Gain/C Phase DC Gain Match IOUTFS = 20mA Channel-to-Channel Crosstalk fOUT = 50MHz, fDAC = 250MHz, 0dBFS -0.25 0.04 +0.25 -90 dB dB REFERENCE Reference Input Range 0.125 Reference Output Voltage VREFIO Reference Input Resistance RREFIO Internal reference 1.14 Reference Voltage Drift 1.250 1.20 1.27 V V 10 k 50 ppm/C CMOS LOGIC INPUT/OUTPUT (A13-A0, SELIQ/B13, DATACLK/B12, B11-B0, DATACLK) Input High Voltage VIH Input Low Voltage VIL Input Current IIN Input Capacitance CIN 4 0.7 x DVDD1.8 -20 V 1 3 _______________________________________________________________________________________ 0.3 x DVDD1.8 V +20 A pF 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs (DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, dual-port mode, 50 double-terminated outputs, external reference at 1.25V, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS Output High Voltage VOH 200A load Output Low Voltage VOL 200A load Output Leakage Current Three-state Rise/Fall Time CLOAD = 10pF, 20% to 80% MIN TYP MAX 0.8 x DVDD3.3 UNITS V 0.2 x DVDD3.3 V 1 A 1.6 ns CLOCK INPUT (CLKP, CLKN) Differential Input Voltage Swing VDIFF Sine-wave input >1.5 Square-wave input >0.5 Differential Input Slew Rate Common-Mode Voltage VCOM AC-coupled VP-P >100 V/s AVCLK / 2 V Input Resistance RCLK 5 k Input Capacitance CCLK 3 pF Minimum Clock Duty Cycle 45 % Maximum Clock Duty Cycle 55 % 6.2 ns CLKP/CLKN, DATACLK TIMING (Figure 4) (Note 7) CLK to DATACLK Delay tD Data Hold Time, DATACLK Input/Output (Pin 14) tDH Data Setup Time, DATACLK Input/Output (Pin 14) tDS Data Hold Time, DATACLK/B10 Input/Output (Pin 27) tDH Data Setup Time, DATACLK/B10 Input/Output (Pin 27) tDS DATACLK output mode, CLOAD = 10pF Capturing rising edge 1.0 Capturing falling edge 2.1 Capturing rising edge 0.4 Capturing falling edge -0.7 Capturing rising edge 1.0 Capturing falling edge 2.3 Capturing rising edge 0.2 Capturing falling edge -0.4 ns ns ns ns SERIAL-PORT INTERFACE TIMING (Figure 3) (Note 7) SCLK Frequency fSCLK 10 MHz CS Setup Time tSS 2.5 ns Input Hold Time tSDH 0 ns Input Setup Time tSDS 4.5 ns Data Valid Duration tSDV 6.5 16.5 ns _______________________________________________________________________________________ 5 MAX5894 ELECTRICAL CHARACTERISTICS (continued) MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs ELECTRICAL CHARACTERISTICS (continued) (DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, dual-port mode, 50 double-terminated outputs, external reference at 1.25V, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1.71 1.8 1.89 V POWER SUPPLIES Digital Supply Voltage DVDD1.8 Digital I/O Supply Voltage DVDD3.3 3.0 3.3 3.6 V AVCLK 3.135 3.3 3.465 V AVDD3.3 3.135 3.3 3.465 AVDD1.8 1.71 1.8 1.89 Clock Supply Voltage Analog Supply Voltage V IAVDD3.3 fCLK = 250MHz, 2x interpolation, 0dBFS, fOUT = 10MHz 110 130 IAVDD1.8 fCLK = 250MHz, 2x interpolation, 0dBFS, fOUT = 10MHz 27 32 Digital Supply Current IDVDD1.8 fCLK = 250MHz, 2x interpolation, 0dBFS, fOUT = 10MHz 225 250 mA Digital I/O Supply Current IDVDD3.3 fCLK = 250MHz, 2x interpolation, 0dBFS, fOUT = 10MHz 21 32 mA Clock Supply Current IAVCLK fCLK = 250MHz, 2x interpolation, 0dBFS, fOUT = 10MHz 3 5 mA Total Power Dissipation PTOTAL fCLK = 250MHz, 2x interpolation, 0dBFS, fOUT = 10MHz 886 Analog Supply Current AVDD3.3 All I/O are static high or low, bit 2 to bit 4 of address 00h are set high Power-Down Current Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: 6 PSRRA (Note 8) mW 450 AVDD1.8 1 DVDD1.8 10 DVDD3.3 100 AVCLK AVDD3.3 Power-Supply Rejection Ratio mA A 1 0.05 %FS/V All limit specifications are 100% tested at TA +25C. Specifications at TA < +25C are guaranteed by design and characterization. 3.84MHz bandwidth, single carrier. Excludes data latency. Measured single-ended into a 50 load. Excludes sin(x)/x rolloff. Guaranteed by design and characterization. Parameter defined as the change in midscale output caused by a 5% variation in the nominal supply voltage. _______________________________________________________________________________________ 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs -6dBFS 80 -12dBFS 40 60 60 -6dBFS -12dBFS 50 40 0 0 10 20 30 0 50 40 0 10 20 UPPER SIDEBAND MODULATION SPURS MEASURED BETWEEN 62.5MHz AND 125MHz 10 0 30 50 40 62.5 72.5 82.5 92.5 102.5 112.5 OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz) IN-BAND SFDR vs. OUTPUT FREQUENCY fDATA = 125Mwps, 4x INTERPOLATION OUT-OF-BAND SFDR vs. OUTPUT FREQUENCY fDATA = 125Mwps, 4x INTERPOLATION IN-BAND SFDR vs. OUTPUT FREQUENCY fDATA = 125Mwps, 4x INTERPOLATION 70 60 60 SFDR (dBc) 80 -12dBFS 40 70 60 -6dBFS -12dBFS 50 40 30 0 10 20 30 SPURS MEASURED BETWEEN 62.5MHz AND 250MHz 10 50 LOWER SIDEBAND MODULATION SPURS MEASURED BETWEEN 62.5MHz AND 125MHz 10 0 40 -12dBFS 40 20 20 0 -6dBFS 50 30 20 SPURS MEASURED BETWEEN 0MHz AND 62.5MHz -0.1dBFS 80 SFDR (dBc) -6dBFS -0.1dBFS 80 90 MAX5894 toc05 100 90 MAX5894 toc04 -0.1dBFS MAX5894 toc06 OUTPUT FREQUENCY (MHz) 120 0 0 10 20 30 50 40 75 85 95 105 115 125 OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz) IN-BAND SFDR vs. OUTPUT FREQUENCY fDATA = 125Mwps, 4x INTERPOLATION TWO-TONE IMD vs. OUTPUT FREQUENCY fDATA = 125Mwps, 2x INTERPOLATION TWO-TONE IMD vs. OUTPUT FREQUENCY fDATA = 125Mwps, 4x INTERPOLATION -12dBFS 40 30 20 UPPER SIDEBAND MODULATION SPURS MEASURED BETWEEN 125MHz AND 187.5MHz 10 0 125 135 145 155 -40 -6dBFS -60 -9dBFS -80 -12dBFS -100 -6dBFS -120 165 OUTPUT FREQUENCY (MHz) 175 0 25 1MHz CARRIER SPACING COMPLEX MODULATION FOR OUTPUT FREQUENCIES GREATER THAN 50MHz -20 -40 -60 -9dBFS -80 -12dBFS -100 -6dBFS -120 50 75 CENTER FREQUENCY (MHz) 100 MAX5894 toc09 0 TWO-TONE IMD (dBc) 60 1MHz CARRIER SPACING COMPLEX MODULATION FOR OUTPUT FREQUENCIES GREATER THAN 50MHz -20 TWO-TONE IMD (dBc) 70 50 0 MAX5894 toc08 -6dBFS -0.1dBFS 80 MAX5894 toc07 90 SFDR (dBc) -0.1dBFS 20 SPURS MEASURED BETWEEN 62.5MHz AND 125MHz 10 40 -12dBFS 50 30 20 SPURS MEASURED BETWEEN 0MHz AND 62.5MHz -0.1dBFS 70 30 20 -6dBFS 80 SFDR (dBc) 60 SFDR (dBc) SFDR (dBc) 90 70 80 SFDR (dBc) -0.1dBFS 90 IN-BAND SFDR vs. OUTPUT FREQUENCY fDATA = 125Mwps, 2x INTERPOLATION MAX5894 toc02 -0.1dBFS 100 100 MAX5894 toc01 120 0UT-OF-BAND SFDR vs. OUTPUT FREQUENCY fDATA = 125Mwps, 2x INTERPOLATION MAX5894 toc03 IN-BAND SFDR vs. OUTPUT FREQUENCY fDATA = 125Mwps, 2x INTERPOLATION 10 40 70 100 130 160 CENTER FREQUENCY (MHz) _______________________________________________________________________________________ 7 MAX5894 Typical Operating Characteristics (DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, output is transformer-coupled to 50 load, TA = +25C, unless otherwise noted.) Typical Operating Characteristics (continued) (DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, output is transformer-coupled to 50 load, TA = +25C, unless otherwise noted.) GAIN MISMATCH vs. TEMPERATURE fDATA = 125Mwps, 2x INTERPOLATION DNL (LSB) 0.050 0.025 0 1.0 0.25 0.5 -15 10 35 60 0 -0.25 -0.5 -0.50 -1.0 -0.75 -1.5 -1.00 -40 -2.0 0 85 4096 8192 12,288 0 16,384 4096 8192 12,288 16,384 TEMPERATURE (C) DIGITAL INPUT CODE DIGITAL INPUT CODE SUPPLY CURRENT vs. DAC UPDATE RATE 2x INTERPOLATION, fOUT = 5MHz SUPPLY CURRENT vs. DAC UPDATE RATE 4x INTERPOLATION, fOUT = 5MHz SUPPLY CURRENT vs. DAC UPDATE RATE 8x INTERPOLATION, fOUT = 5MHz 350 300 250 1.8V TOTAL 200 150 100 3.3V TOTAL 50 0 1.8V TOTAL 350 300 250 200 150 150 200 fDAC (MHz) 250 300 450 400 3.3V TOTAL 1.8V TOTAL 350 300 250 200 150 100 100 50 50 0 100 500 MAX5894 toc15 400 SUPPLY CURRENT (mA) 400 450 SUPPLY CURRENT (mA) 450 MAX5894 toc14 500 MAX5894 toc13 500 8 1.5 0.50 0 MAX5894 toc12 0.75 0.075 2.0 MAX5894 toc11 1.00 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE INL (LSB) fOUT = 22.7MHz AOUT = -6dBFS GAIN MISMATCH (dB) DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE MAX5894 toc10 0.100 SUPPLY CURRENT (mA) MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs 3.3V TOTAL 0 100 200 300 400 500 100 200 fDAC (MHz) _______________________________________________________________________________________ 300 fDAC (MHz) 400 500 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs TWO-CARRIER ADJACENT CHANNEL 50 60 TWO-CARRIER ALTERNATE CHANNEL TWO-CARRIER ALTERNATE CHANNEL MAX5894 toc18 -50 -60 -70 -80 -90 -100 50 ACLR2 = 77dB 60 70 TWO-CARRIER ADJACENT CHANNEL -40 ACLR1 = 75dB 70 -30 CARRIER = -11dBm 80 ACLR (dB) ACLR (dB) 80 ONE-CARRIER ALTERNATE CHANNEL ACLR1 = 76dB 90 -20 OUTPUT POWER (dBm) ONE-CARRIER ALTERNATE CHANNEL ONE-CARRIER ADJACENT CHANNEL WCDMA ACLR SPECTRAL PLOT fDATA = 61.44Mwps, 8x INTERPOLATION MAX5894 toc17 ONE-CARRIER ADJACENT CHANNEL 90 100 MAX5894 toc16 100 WCDMA ACLR vs. OUTPUT FREQUENCY fDATA = 76.8Mwps, 4x INTERPOLATION ACLR2 = 78dB WCDMA ACLR vs. OUTPUT FREQUENCY fDATA = 122.88Mwps, 4x INTERPOLATION -110 40 40 fCENTER = 61.44MHz SPAN = 25.5MHz 80 -110 -80 -90 -100 MAX5894 toc20 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -110 fCENTER = 61.44MHz SPAN = 30.5MHz ACLR2 = 69dB -70 ACLR1 = 67dB -60 CARRIER = -14dBm -50 ACLR1 = 67dB ACLR2 = 74dB -40 ACLR2 = 70dB -100 ACLR1 = 73dB -90 ACLR1 = 74dB -80 ACLR2 = 75dB -60 CARRIER = -14dBm -50 -30 OUTPUT POWER (dBm) -40 -70 -20 MAX5894 toc19 -30 TWO-CARRIER WCDMA ACLR SPECTRAL PLOT fDATA = 122.88Mwps, 4x INTERPOLATION MAX5894 toc21 WCDMA ACLR SPECTRAL PLOT fDATA = 122.88Mwps, 4x INTERPOLATION ACLR2 = 67dB TWO-CARRIER WCDMA ACLR SPECTRAL PLOT fDATA = 61.44Mwps, 8x INTERPOLATION ACLR1 = 65dB 40 fCENTER (MHz) -20 OUTPUT POWER (dBm) 0 CARRIER = -17dBm 160 120 ACLR1 = 65dB 80 fCENTER (MHz) ACLR2 = 68dB 40 OUTPUT POWER (dBm) 0 fCENTER = 122.88MHz SPAN = 25.5MHz fCENTER = 122.88MHz SPAN = 30.5MHz _______________________________________________________________________________________ 9 MAX5894 Typical Operating Characteristics (continued) (DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, output is transformer-coupled to 50 load, TA = +25C, unless otherwise noted.) MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs Pin Description PIN NAME 1 CLKP Noninverting Differential Clock Input. Internally biased to AVCLK / 2. 2 CLKN Inverting Differential Clock Input. Internally biased to AVCLK / 2. 3, 4, 5, 24, 25, 42, 43 N.C. 6, 21, 30, 37 DVDD1.8 Digital Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to ground with a 0.1F capacitor as close to the pin as possible. 7-12, 15-20, 22, 23 A13-A0 A-Port Data Inputs. Dual-port mode: I-channel data input. Data is latched on the rising/falling edge (programmable) of the DATACLK. Single-port mode: I-channel and Q-channel data input, with SELIQ. 13, 44 DVDD3.3 CMOS I/O Power Supply. Accepts a 3.0V to 3.6V supply range. Bypass each pin to ground with a 0.1F capacitor as close to the pin as possible. 14 DATACLK Programmable Data Clock Input/Output. See the DATACLK Modes section for details. SELIQ/B13 Select I-/Q-Channel Input or B-Port MSB Input. Single-port mode: If SELIQ = LOW, data is latched into Q-channel on the rising/falling edge (programmable) of the DATACLK. If SELIQ = HIGH, data is latched into I-channel on the rising/falling edge (programmable) of the DATACLK. Dual-port mode: Q-channel MSB input. 26 27 FUNCTION Internally Connected. Do not connect. Alternate DATACLK Input/Output or B-Port Bit 12 Input. Single-port mode: See the DATACLK Modes section for details. DATACLK/B12 Dual-port mode: Q-channel bit 12 input. If unused connect to GND. B-Port Data Bits 11-0. Dual-port mode: Q-channel inputs. Data is latched on the rising/falling (programmable) edge of the DATACLK. Single-port mode: Connect to GND. 28, 29, 31-36, 38-41 B11-B0 45 DOUT 46 DIN 47 SCLK 48 CS 49 RESET 50 REFIO Reference Input/Output. Bypass to ground with a 1F capacitor as close to the pin as possible. 51 DACREF Current-Set Resistor Return Path. For a 20mA full-scale output current, connect a 2k resistor between FSADJ and DACREF. Internally connected to GND. DO NOT USE AS AN EXTERNAL GROUND CONNECTION. 52 FSADJ Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For a 20mA fullscale output current, connect a 2k resistor between FSADJ and DACREF. 10 Serial-Port Data Output Serial-Port Data Input Serial-Port Clock Input. Data on DIN is latched on the rising edge of SCLK. Serial-Port Interface Select. Drive CS low to enable serial-port interface. Reset Input. Set RESET low during power-up. ______________________________________________________________________________________ 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs PIN NAME FUNCTION 53, 67 AVDD1.8 54, 56, 59, 61, 64, 66 GND 55, 60, 65 AVDD3.3 57 OUTQN Inverting Differential DAC Current Output for Q-Channel 58 OUTQP Noninverting Differential DAC Current Output for Q-Channel 62 OUTIN Inverting Differential DAC Current Output for I-Channel 63 OUTIP Noninverting Differential DAC Current Output for I-Channel 68 AVCLK Clock Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass to ground with a 0.1F capacitor as close to the pin as possible. EP GND Low Analog Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to GND with a 0.1F capacitor as close to the pin as possible. Ground Analog Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass each pin to GND with a 0.1F capacitor as close to the pin as possible. Exposed Paddle. Must be connected to GND through a low-impedance path. Functional Diagram MODULATOR MUX MUX 2x INTERPOLATING FILTER 2x INTERPOLATING FILTER 2x INTERPOLATING FILTER DIGITAL OFFSET ADJUST fDAC DATA SYNCH AND DEMUX B0-B13 OUTIP IDAC OUTIN A0-A13 DATACLK DIGITAL GAIN ADJUST I Q fIM / 2, fIM / 4 I Q DIGITAL OFFSET ADJUST MUX MUX 2x INTERPOLATING FILTER 2x INTERPOLATING FILTER 2x INTERPOLATING FILTER SELIQ MAX5894 DIGITAL GAIN ADJUST OUTQP QDAC OUTQN fDAC /2 /2 /2 /2 CONTROL REGISTERS fCLK SERIAL INTERFACE RESET DOUT DIN CS CLOCK BUFFERS AND DIVIDERS REFERENCE SCLK DACREF FSADJ REFIO CLKN CLKP ______________________________________________________________________________________ 11 MAX5894 Pin Description (continued) MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs Detailed Description The MAX5894 dual, 500Msps, high-speed, 14-bit, current-output DAC provides superior performance in communication systems requiring low-distortion analog-signal reconstruction. The MAX5894 combines two DAC cores with 8x/4x/2x/1x programmable digital interpolation filters, a digital quadrature modulator, an SPIcompatible serial interface for programming the device, and an on-chip 1.20V reference. The full-scale output current range is programmable from 2mA to 20mA to optimize power dissipation and gain control. Each channel contains three selectable interpolating filters making the MAX5894 capable of 1x, 2x, 4x, or 8x interpolation, which allows for low input data rates and high DAC update rates. When operating in 8x interpolation mode, the interpolator increases the DAC conversion rate by a factor of eight, providing an eight-fold increase in separation between the reconstructed waveform spectrum and its first image. The MAX5894 accepts either two's complement or offset binary input data format and can operate from either a single- or dual-port input bus. The MAX5894 includes modulation modes at fIM / 2 and fIM / 4, where fIM is the data rate at the input of the modulator. If 2x interpolation is used, this data rate is 2x the input data rate. If 4x or 8x interpolation is used, this data rate is 4x the input data rate. Table 1 summarizes the modulator operating data rates for dual-port mode. The power-down modes can be used to turn off each DAC's output current or the entire digital section. Programming both DACs into power-down simultaneously automatically powers down the digital interpolator filters. Note the SPI section is always active. The analog and digital sections of the MAX5894 have separate power-supply inputs (AV DD3.3 , AV DD1.8 , AVCLK, DVDD3.3, and DVDD1.8), which minimize noise coupling from one supply to the other. AVDD1.8 and DVDD1.8 operate from a typical 1.8V supply, and all other supply inputs operate from a typical 3.3V supply. Serial Interface The SPI-compatible serial interface programs the MAX5894 registers. The serial interface consists of the CS, DIN, SCLK, and DOUT. Data is shifted into DIN on the rising edge of the SCLK when CS is low. When CS is high, data presented at DIN is ignored and DOUT is in high-impedance mode. Note: CS must transition high after each read/write operation. DOUT is the serial data output for reading registers to facilitate easy debugging during development. DIN and DOUT can be connected together to form a 3-wire serial interface bus or remain separate and form a 4-wire SPI bus. The serial interface supports two-byte transfer in a communication cycle. The first byte is a control byte written to the MAX5894 only. The second byte is a data byte and can be written to or read from the MAX5894. Table 1. Quadrature Modulator Operating Data Rates (fIM is the Data Rate at the Input of the Modulator) for Dual-Port Mode INTERPOLATION RATE 1x 2x 4x 8x 12 MODULATION MODE (fLO) MODULATION FREQUENCY RELATIVE TO fDAC MODULATION FREQUENCY RELATIVE TO fDATA fIM / 2 fDAC / 2 fDATA / 2 fDATA / 4 fIM / 4 fDAC / 4 fIM / 2 fDAC / 2 fDATA fIM / 4 fDAC / 4 fDATA / 2 fIM / 2 fDAC / 2 2 x fDATA fIM / 4 fDAC / 4 fDATA fIM / 2 fDAC / 4 2 x fDATA fIM / 4 fDAC / 8 fDATA ______________________________________________________________________________________ 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs read operation. The most significant bit (MSB) is shifted in first in default mode. If the serial port is set to LSB-first mode, both the control byte and data byte are shifted LSB in first. Figures 1 and 2 show the SPI serial-interface operation in the default write and read mode, respectively. Figure 3 is a timing diagram for the SPI serial interface. CS SCLK DIN 0 0 0 0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 HIGH IMPEDANCE DOUT Figure 1. SPI Serial-Interface Write Cycle, MSB-First Mode CS READ CYCLE N - 1 READ CYCLE N READ CYCLE N + 1 SCLK DIN DOUT ADDRESS 1 0 0 0 3 2 1 0 HIGH IMPEDANCE DATA IGNORED DATA N - 2 ADDRESS 1 0 0 0 3 2 1 0 HIGH IMPEDANCE DATA IGNORED DATA N - 1 ADDRESS 1 0 0 0 3 2 1 0 HIGH IMPEDANCE DATA IGNORED DATA N Figure 2. SPI Serial-Interface Read Cycle, MSB-First Mode ______________________________________________________________________________________ 13 MAX5894 When writing to the MAX5894, data is shifted into DIN; data is shifted out of DOUT in a read operation. Bits 0 to 3 of the control byte are the address bits. These bits set the address of the register to be written to or read from. Bits 4 to 6 of the control byte must always be set to 0. Bit 7 is a read/write bit: 0 for write operation and 1 for MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs tSS CS SCLK tSDH tSDS DIN tSDV DOUT Figure 3. SPI Serial-Interface Timing Diagram 14 ______________________________________________________________________________________ 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs of the registers. The following are descriptions of each register. Table 2. MAX5894 Programmable Registers ADD BIT 7 BIT 6 0 = MSB first 1 = LSB first BIT 4 BIT 3 Software Reset 0 = Normal 1 = Reset all registers BIT 5 Interpolator Power-Down 0 = Normal 1 = Power-down IDAC PowerDown 0 = Normal 1 = Power-down Third Interpolation Filter Configuration 0 = Lowpass 1 = Highpass 0 = Clock output on DATACLK 1 = Clock output on DATACLK/B12 BIT 2 BIT 1 QDAC PowerDown 0 = Normal 1 = Power-down Unused Modulation Mode (Bit 4, Bit 3) 00 = Modulation off 01 = fIM / 2 10 = fIM / 4 11 = fIM / 4 Mixer Modulation Mode 0 = Complex 1 = Real Modulation Sign 0 = e-j 1 = e-j 0 = Input data latched on rising clock edge 1 = Input data latched on falling clock edge Data Synchronizer 0 = Enabled 1 = Disabled Unused BIT 0 00h Unused 01h Interpolation Rate (Bit 7, Bit 6) 00 = No interpolation 01 = 2x interpolation 10 = 4x interpolation 11 = 8x interpolation 02h 0 = Two's complement input data 1 = Offset binary input data 03h Unused 04h 8-Bit IDAC Fine-Gain Adjustment (see the Gain Adjustment section). Bit 7 is MSB and bit 0 is LSB. Default: 00h 05h Unused 06h 10-Bit IDAC Offset Adjustment (see the Offset Adjustment section). Bits 7 to 0 of the 06h register are the MSB bits. Bit 1 and bit 0 are the LSB bits in 07h register. Default: 000h 0 = Single port (A), interleaved I/Q 1 = Dual port I/Q input 0 = Data clock input enabled 1 = Data clock output enabled Unused 4-Bit IDAC Coarse-Gain Adjustment (see the Gain Adjustment section). Bit 3 is MSB and bit 0 is LSB. Default: Fh 08h IDAC IOFFSET IDAC Offset Direction Adjustment 0 = Current on Unused Bit 1 OUTIN (see 06h 1 = Current on register) OUTIP 8-Bit QDAC Fine-Gain Adjustment (see the Gain Adjustment section). Bit 7 is MSB and bit 0 is LSB. Default: 00h 09h Unused 0Ah 10-Bit QDAC Offset Adjustment (see the Offset Adjustment section). Bits 7 to 0 of the 0Ah register are the MSB bits. Bit 1 and bit 0 are the LSB bits in 0Bh register. Default: 000h 0Bh QDAC IOFFSET Direction 0 = Current on OUTQN 1 = Current on OUTQP 0Ch Reserved, do not write to these bits. 0Dh Reserved, do not write to these bits. 0Eh Reserved, do not write to these bits. 07h IDAC Offset Adjustment Bit 0 (see 06h register) 4-Bit QDAC Coarse-Gain Adjustment (see the Gain Adjustment section). Bit 3 is MSB and bit 0 is LSB. Default: Fh Unused QDAC Offset Adjustment Bit 1 (see 0Ah register) QDAC Offset Adjustment Bit 0 (see 0Ah register) Conditions in bold are default states after reset. ______________________________________________________________________________________ 15 MAX5894 Programming Registers Programming its registers with the SPI serial interface sets the MAX5894 operation modes. Table 2 shows all MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs e -jw (default), cancelling the upper image when used with an external quadrature modulator. A logic 1 sets the complex modulation to be e+jw, cancelling the lower image when used with an external quadrature modulator. Address 00h Bit 6 Logic 0 (default) causes the serial port to use MSB first address/data format. When set to a logic 1, the serial port uses LSB first address/ data format. Bit 5 Bit 4 Bit 3 When set to a logic 1, all registers reset to their default state (this bit included). Logic 1 stops the clock to the digital interpolators. DAC outputs hold last value prior to interpolator power-down. IDAC power-down mode. A logic 1 to this bit powers down the IDAC. Bit 2 QDAC power-down mode. A logic 1 to this bit powers down the QDAC. Note: If both bit 2 and bit 3 are 1, the MAX5894 is in full-power-down mode, leaving only the serial interface active. Address 01h Bits 7, 6 Configure the interpolation filters according to the following table: 00 1x (no interpolation) 01 10 11 Bit 5 2x 4x 8x (default) Logic 0 configures FIR3 as a lowpass digital filter (default). A logic 1 configures FIR3 as a highpass digital filter. Bits 4, 3 Configure the modulation frequency according to the following table: 00 No modulation 01 fIM / 2 modulation 10 fIM / 4 modulation (default) Bit 2 Bit 1 16 11 fIM / 4 modulation where fIM is the data rate at the input of the modulator. Configures the modulation mode for either real or complex (image reject) modulation. Logic 1 sets the modulator to the real mode (default). Complex modulation is only available for fIM / 4 modulation. Quadrature modulator sign inversion. With Ichannel data leading Q-channel data by 90, logic 0 sets the complex modulation to be Address 02h Bit 7 Logic 0 (default) configures the data port for two's complement. A logic 1 configures the data ports for offset binary. Bit 6 Logic 0 (default) configures the data bus for single-port, interleaved I/Q data. I and Q data enter through one 14-bit bus. Logic 1 configures the data bus for dual-port I/Q data. I and Q data enter on separate buses. Bit 5 Logic 0 (default) configures the data clock for pin 14. A logic 1 configures the data clock for pin 27 (DATACLK/B12). Bit 4 Bit 3 Bit 2 Logic 0 (default) sets the internal latches to latch the data on the rising edge of DATACLK. A logic 1 sets the internal latches to latch the data on the falling edge of DATACLK. Logic 0 (default) configures the DATACLK pin (pin 14 or pin 27) to be an input. A logic 1 configures the DATACLK pin to be an output. Logic 0 (default) enables the data synchronizer circuitry. A logic 1 disables the data synchronizer circuitry. Address 03h Bits 7-0 Unused. Address 04h Bits 7-0 These 8 bits define the binary number for fine-gain adjustment of the IDAC full-scale current (see the Gain Adjustment section). Bit 7 is the MSB. Default is all zeros. Address 05h Bits 3-0 These four bits define the binary number for the coarse-gain adjustment of the IDAC fullscale current (see the Gain Adjustment section). Bit 3 is the MSB. Default is all ones. Address 06h, Bits 7-0; Address 07h, Bit 1 and Bit 0 These 10 bits represent a binary number that defines the magnitude of the offset added to the IDAC output (see the Offset Adjustment section). Default is all zeros. ______________________________________________________________________________________ 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs These 10 bits represent a binary number that defines the magnitude of the offset added to the QDAC output (see the Offset Adjustment section). Default is all zeros. Address 0Bh Bit 7 Logic 0 (default) adds the 10 bits offset to OUTQN. A logic 1 adds the 10 bits offset to OUTQP. Offset Adjustment Offset adjustment is achieved by adding a digital code to the DAC inputs. The code OFFSET (see equation below), as stored in the relevant control registers, has a range from 0 to 1023 and a sign bit. The applied DAC offset is stored in the register, providing an offset adjustment range of 1023 LSB codes. The resolution is 1 LSB. IOFFSET = OFFSET 214 x IOUTFS Gain Adjustment Gain adustment is peformed by varying the full-scale current according to the following formula: 3 x IREF COARSE + 1 3 x IREF FINE 1024 IOUTFS = - 32 256 24 4 16 where IREF is the reference current (see the Reference Input/Output section). COARSE is the register content of registers 05h and 09h for the I- and Q-channel, respectively. FINE is the register content of register 04h and 08h for the I- and Q-channel, respectively. The range of coarse is from 0 to 15, with 15 being the default. The range for FINE is from 0 to 255 with 0 being the default. The gain can be adjusted in steps of approximately 0.01dB. Single-Port/Dual-Port Data-Input Modes The MAX5894 is capable of capturing data in singleport and dual-port modes (selected through bit 6, address 02h). In single-port mode, the data for both DAC channels is latched on the A port (A13-A0). The channel for the input data is determined by the state of the SELIQ/B13 (pin 26) bit. When SELIQ is set to logic-high, the input data is presented to the I-channel, when set to logic-low, the input data is presented to the Q-channel. The unused B-port inputs (DATACLK/B12, B11-B0) should be grounded when running in single-port mode. Dual-port mode, as the name implies, requires that each channel receives its data from a separate data bus. SELIQ/B13 and DATACLK/B12 revert to data bit inputs for the Q-channel in dual-port mode. The MAX5894 control registers can be programmed to allow either signed or unsigned binary format (bit 7, address 02h) data in either single-port or dual-port mode. Table 3 shows the corresponding DAC output levels when using signed or unsigned data modes. Table 3. DAC Output Code Table DIGITAL INPUT CODE OFFSET BINARY (UNSIGNED) TWO'S COMPLEMENT (SIGNED) OUT_P OUT_N 00 0000 0000 0000 10 0000 0000 0000 0 IOUTFS 01 1111 1111 1111 00 0000 0000 0000 IOUTFS / 2 IOUTFS / 2 11 1111 1111 1111 01 1111 1111 1111 IOUTFS 0 Data Synchronization Modes Data synchronization circuitry is provided to allow operation with an input data clock. The data clock must be frequency locked to the DAC clock (f DAC), but can have arbitrary phase with respect to the DAC clock. The synchronization circuitry allows for phase jitter on the input data clock of up to 1 data clock cycles. Synchronization is initially established when the reset pin is asynchronously deasserted and the input data clock has been running for at least four clock cycles. ______________________________________________________________________________________ 17 MAX5894 Address 07h Bit 7 Logic 0 (default) adds the 10 bits offset current to OUTIN. A logic 1 adds the 10 bits offset current to OUTIP. Address 08h Bits 7-0 These 8 bits define the binary number for fine-gain adjustment of the QDAC full-scale current (see the Gain Adjustment section). Bit 7 is the MSB. Default is all zeros. Address 09h Bits 3-0 These four bits define the binary number for the coarse-gain adjustment of the QDAC fullscale current (see the Gain Adjustment section). Bit 3 is the MSB. Default is all ones. Address 0Ah, Bits 7-0; Address 0Bh, Bit 1 and Bit 0 MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs Subsequently, the MAX5894 monitors the phase relationship and detects if the phase drifts more than 1 data clock cycle. If this occurs, the synchronizer automatically re-establishes synchronization. However, during the resynchronization phase, up to 8 data words may be lost or repeated. Bit 2 of register 02h disables or enables (default) the automatic data clock phase detection. Disabling the data synchronization circuitry requires the data clock and the DAC clock phase to be locked. Table 4. Clock Frequency Ratios in Various Modes INPUT MODE Single Port DATACLK Modes The MAX5894 has a main DATACLK available at pin 14. An alternate DATACLK is available at pin 27 (DATACLK/B12) when configured in single-port data input mode (bit 5, address 02h). The DATACLK can be configured to accept an input clock signal for latching the input data, or to source a clock signal that can drive up to 10pF load while latching the input data (bit 3, address 02h). If DATACLK is configured as an output, it is frequency divided from the CLKP/CLKN input, depending on the operating mode, see Table 4. Dual Port INTERPOLATION RATE fDATA:fCLK fDAC:fCLK 1x 1:1 1:2 2x 1:1 1:1 4x 1:2 1:1 8x 1:4 1:1 1x 1:1 1:1 2x 1:2 1:1 4x 1:4 1:1 8x 1:8 1:1 The MAX5894 can be configured to latch the input data on either the rising edge or falling edge of the DATACLK signal (bit 4, address 02h). Figure 4 shows the timing requirements between the DATACLK signal and the input-data bus with latching on the rising edge. CLKP-CLKN tCLK DATACLK tD tDS tDH A0-A13/B0-B13 Figure 4. Data-Input Timing Diagram 18 ______________________________________________________________________________________ 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs ter is located after the modulator. In the 8x interpolation mode, the last filter (FIR3) can be configured as lowpass or highpass (bit 5, address 01h) to select the lower or upper sideband from the modulation output. The frequency responses of these three filters are plotted in Figures 5-8. 0 0 -20 -20 PASSBAND DETAIL -40 0 GAIN (dBFS) GAIN (dBFS) MAX5894 Interpolating Filter The MAX5894 features three cascaded FIR half-band filters. The interpolating filters are enabled or disabled in combinations to support 1x (no interpolation), 2x, 4x, or 8x interpolation. Bits 7 and 6 of register 01h set the interpolation rate (see Table 2). The last interpolation fil- -0.0002 -60 -0.0004 0.4 0.3 0.2 0.1 0 PASSBAND DETAIL -40 0 -0.0002 -60 -0.0004 0 -80 -80 -100 -100 0.1 0.2 0.3 2.0 2.5 0.4 -120 -120 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.5 1.0 1.5 3.0 3.5 4.0 fOUT - NORMALIZED TO INPUT DATA RATE fOUT - NORMALIZED TO INPUT DATA RATE Figure 5. Interpolation Filter Frequency Response, 2x Interpolation Mode Figure 6. Interpolation Filter Frequency Response, 4x Interpolation Mode 0 0 0 -0.0002 -20 PASSBAND DETAIL -40 0 GAIN (dBFS) GAIN (dBFS) -20 -0.0002 -60 -0.0004 0.1 0 0.2 0.3 0.4 -40 -0.0004 -0.0002 -60 -0.0004 -80 -80 -100 -100 -120 PASSBAND DETAIL 0 3.6 3.8 4.0 4.2 4.4 -120 0 1 2 3 4 5 6 7 8 fOUT - NORMALIZED TO INPUT DATA RATE Figure 7. Interpolation Filter Frequency Response, 8x Interpolation Mode (FIR3 Lowpass Mode) 0 1 2 3 4 5 6 7 8 fOUT - NORMALIZED TO INPUT DATA RATE Figure 8. Interpolation Filter Frequency Response, 8x Interpolation Mode (FIR3 Highpass Mode) ______________________________________________________________________________________ 19 0 MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs The programmable interpolation filters multiply the MAX5894 input data rate by a factor of 2x, 4x, or 8x to separate the reconstructed waveform spectrum and the DAC image. The original spectral images, appearing at around multiples of the input data rate, are attenuated by the internal digital filters. This feature provides three benefits: 1) Image separation reduces complexity of analog reconstruction filters. INPUT SPECTRUM AND FIRST FILTER RESPONSE SIGNAL OUTPUT SPECTRUM OF THE FIRST FILTER 4fS 5fS 6fS 7fS 8fS 2x INTERPOLATION 3fS 4fS 5fS 2fS 6fS 7fS 8fS 6fS 7fS 8fS FILTER RESPONSE IMAGE 3fS 4fS 5fS SIGNAL 4x INTERPOLATION IMAGE 2fS 3fS 4fS SIGNAL 2fS 3fS 5fS 6fS 7fS 8fS 5fS 6fS 7fS 8fS IMAGE FILTER RESPONSE fS OUTPUT SPECTRUM OF THE THIRD FILTER 2fS SIGNAL fS INPUT SPECTRUM AND THIRD FILTER RESPONSE 3fS NO INTERPOLATION IMAGE fS OUTPUT SPECTRUM OF THE SECOND FILTER 2fS SIGNAL fS INPUT SPECTRUM AND SECOND FILTER RESPONSE Figure 9 illustrates a practical example of the benefits when using the MAX5894 in 2x, 4x, and 8x interpolation modes with the third filter configured as a lowpass filter. With no interpolation filter, the first image signal appears in the second Nyquist zone between fS / 2 and fS. The first interpolating filter removes this image. In fact, all of the FILTER RESPONSE IMAGE fS 2) Lower input data rates eliminate board-level highspeed data transmission. 3) Sin(x)/x rolloff is reduced over the effective bandwidth. 4fS SIGNAL 8x INTERPOLATION IMAGE fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS Figure 9. Spectral Representation of Interpolating Filter Responses (Output Frequencies are Relative to the Data Input Frequency, fS) 20 ______________________________________________________________________________________ 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs INPUT SPECTRUM AND FIRST FILTER RESPONSE SIGNAL FILTER RESPONSE IMAGE 2fS fS OUTPUT SPECTRUM OF THE FIRST FILTER SIGNAL SIGNAL FILTER RESPONSE 4fS 2x INTERPOLATION 3fS 4fS 3fS 4fS IMAGE 2fS SIGNAL 4x INTERPOLATION IMAGE fS OUTPUT SPECTRUM OF THE MODULATOR 3fS 2fS fS OUTPUT SPECTRUM OF THE SECOND FILTER NO INTERPOLATION IMAGE fS INPUT SPECTRUM AND SECOND FILTER RESPONSE 10fS, etc. Finally, the third filter removes images at 4fS, 12fS, 20fS, etc. Figures 10, 11, and 12 similarly illustrate the spectral responses when using the interpolating filters combined with the digital modulator. LOWER SIDEBAND SIGNAL fS 2fS 3fS UPPER SIDEBAND 4fS IMAGE 2fS 3fS 4fS FOR COMPLEX MODULATION THE MODULATION SIGN (BIT 1, ADDRESS 01h) SELECTS UPPER OR LOWER SIDEBAND Figure 10. Spectral Representation of 4x Interpolation Filter with fIM / 4 Modulation (Output Frequencies are Relative to the Data Input Frequency, fS) ______________________________________________________________________________________ 21 MAX5894 images at odd numbers of fS are filtered. At the output of the first filter, the images are at 2fS, 4fS, etc. This signal is then passed to the second interpolating filter, which is similar to the first filter and removes the images at 2fS, 6fS, MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs INPUT SPECTRUM AND FIRST FILTER RESPONSE SIGNAL IMAGE fS OUTPUT SPECTRUM OF THE FIRST FILTER 2fS SIGNAL SIGNAL 4fS 5fS 6fS 7fS 8fS 2x INTERPOLATION 3fS 4fS 2fS 5fS 6fS 7fS 8fS 5fS 6fS 7fS 8fS FILTER RESPONSE IMAGE 3fS 4fS SIGNAL 4x INTERPOLATION IMAGE fS OUTPUT SPECTRUM OF THE MODULATOR 3fS 2fS fS OUTPUT SPECTRUM OF THE SECOND FILTER NO INTERPOLATION IMAGE fS INPUT SPECTRUM AND SECOND FILTER RESPONSE FILTER RESPONSE LOWER SIDEBAND 2fS 3fS SIGNAL UPPER SIDEBAND 4fS 5fS 6fS fS 8fS 7fS 8fS IMAGE 2fS 3fS 4fS 5fS 6fS SIGNAL OUTPUT SPECTRUM OF THE THIRD FILTER 7fS FILTER RESPONSE SIGNAL fS 8fS IMAGE fS 2fS 3fS 4fS 5fS 6fS FOR COMPLEX MODULATION THE MODULATION SIGN (BIT 1, ADDRESS 01h) SELECTS UPPER OR LOWER SIDEBAND INPUT SPECTRUM AND THIRD FILTER RESPONSE 7fS 8x INTERPOLATION IMAGE 2fS 3fS 4fS 5fS 6fS 7fS 8fS Figure 11. Spectral Representation of 8x Interpolation Filter with fIM / 4 Modulation and Lowpass Mode Enabled (Output Frequencies are Relative to the Data Input Frequency, fS) 22 ______________________________________________________________________________________ 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs fS OUTPUT SPECTRUM OF THE FIRST FILTER 2fS SIGNAL 2fS SIGNAL 2fS 5fS 6fS 7fS 8fS 2x INTERPOLATION 3fS 4fS 5fS 6fS 7fS 8fS 6fS 7fS 8fS FILTER RESPONSE 3fS 4fS 5fS SIGNAL 4x INTERPOLATION IMAGE fS OUTPUT SPECTRUM OF THE MODULATOR 4fS IMAGE fS OUTPUT SPECTRUM OF THE SECOND FILTER 3fS NO INTERPOLATION IMAGE fS INPUT SPECTRUM AND SECOND FILTER RESPONSE FILTER RESPONSE IMAGE LOWER SIDEBAND 2fS 3fS SIGNAL UPPER SIDEBAND 4fS 5fS 6fS SIGNAL fS 8fS 7fS 8fS 7fS 8fS FILTER RESPONSE IMAGE 2fS 3fS 4fS 5fS SIGNAL OUTPUT SPECTRUM OF THE THIRD FILTER fS 7fS IMAGE fS 2fS 3fS 4fS 5fS 6fS FOR COMPLEX MODULATION THE MODULATION SIGN (BIT 1, ADDRESS 01h) SELECTS UPPER OR LOWER SIDEBAND INPUT SPECTRUM AND THIRD FILTER RESPONSE MAX5894 INPUT SPECTRUM AND FIRST FILTER RESPONSE SIGNAL 2fS 3fS 6fS 8x INTERPOLATION IMAGE 4fS 5fS 6fS 7fS 8fS Figure 12. Spectral Representation of 8x Interpolation Filter with fIM / 4 Modulation and Highpass Mode Enabled (Output Frequencies are Relative to the Data Input Frequency, fS) ______________________________________________________________________________________ 23 MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs Digital Modulator The MAX5894 features digital modulation at frequencies of fIM / 2 and fIM / 4, where fIM is the data rate at the input to the modulator. fIM equals fDAC in 1x, 2x, and 4x interpolation modes. In 8x interpolation mode, f IM equals fDAC / 2. The output rate of the modulator is always the same as the input data rate to the modulator. In complex modulation mode, data from the second interpolation filter is frequency mixed with the on-chip in-phase and quadrature (I/Q) local oscillator (LO). Complex modulation provides the benefit of image sideband rejection when combined with an external quadrature modulator commonly found in wireless communication systems. In the fLO = fIM / 4 mode, real or complex modulation can be used. The modulator multiplies successive input data samples by the sequence [1, 0, -1, 0] for a cos(t). The modulator modulates the input signal up to fIM / 4, creating upper and lower images around fIM / 4. The quadrature LO sin(t) is realized by delaying the cos(t) sequence by one clock cycle. Using complex modulation, complex IF is generated. The complex IF combined with an external quadrature modulator provides image rejection. The sign of the LO can be changed to allow the user to select whether the upper or the lower image should be rejected (bit 1 of register 01h). When fIM / 2 is chosen as the LO frequency, the input signal is multiplied by [-1, 1] on both channels. This produces images around fIM / 2. The complex image-reject modulation mode is not available for this LO frequency. I-CHANNEL INPUT DATA The outputs of the modulator can be expressed as: I (t) = A(t) x cos(t) - B(t) x sin(t) Q (t) = A(t) x sin(t) + B(t) x cos(t) in complex modulation, e+jwt I (t) = A(t) x cos(t) + B(t) x sin(t) Q (t) = A(t) x sin(t) + B(t) x cos(t) in complex modulation, e-jwt where = 2 x x fLO. For real modulation, the outputs of the modulator can be expressed as: I (t) = A(t) x cos(t) Q (t) = A(t) x cos(t) If more than one MAX5894 is used, their LO phases can be synchronized by simultaneously releasing RESET. This sets the MAX5894 to its predefined initial phase. Device Reset The MAX5894 can be reset by holding the RESET pin low for 10ns. This will program the control registers to their default values in Table 2. During power-on, RESET must be held low until all power supplies have stabilized. Alternately, programming bit 5 of address 00h to a logic-high also resets the MAX5894 after power-up. I-CHANNEL INPUT DATA cos(t) sin(t) I-CHANNEL OUTPUT DATA cos(t) TO FIR3 sin(t) sin(t) I-CHANNEL OUTPUT DATA TO FIR3 sin(t) Q-CHANNEL INPUT DATA Q-CHANNEL OUTPUT DATA Q-CHANNEL OUTPUT DATA Q-CHANNEL INPUT DATA cos(t) cos(t) (a) (b) Figure 13. (a) Modulator in Complex Modulation Mode; (b) Modulator in Real Modulation Mode 24 ______________________________________________________________________________________ 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs Data Clock The MAX5894 features synchronizers that allow for arbitrary phase alignment between DATACLK and CLKP/CLKN. The DATACLK causes internal switching in the MAX5894 and the phase between DATACLK (input mode) to CLKP/CLKN influences the images at DATACLK. Optimum image rejection is achieved when DATACLK transitions are aligned with the falling edge of CLKP. Figure 14 shows the image level near DATACLK as a function of the DATACLK (input mode) to CLKP/CLKN phase at 500Msps, 4x interpolation for a 10MHz, -6dBFS output signal. Frequency Planning System designers need to take the DAC into account during frequency-planning for high-performance applications. Proper frequency planning can ensure that optimal system performance is achieved. The MAX5894 is designed to deliver excellent dynamic performance across wide bandwidths, as required for communication systems. As with all DACs, some combinations of output frequency and update rate produce better performance than others. Harmonics are often folded down into the band of interest. Specifically, if the DAC outputs a frequency close to fS / N, the Mth harmonic of the output signal will be aliased down to: N - M f = fS - M x fOUT = fS N Thus, if N (M + 1), the Mth harmonic will be close to the output frequency. SFDR performance of a currentsteering DAC is often dominated by 3rd-order harmonic distortion. If this is a concern, placing the output signal at a different frequency other than fS / 4 should be considered. Common to interpolating DACs are images near the divided clocks. In a DAC configured for 4x interpolation, this applies to images around fS / 4 and fS / 2. In a DAC configured for 8x interpolation, this applies to images around fS / 8, fS / 4, and fS / 2. Most of these images are not part of the in-band (0 to fDATA / 2) SFDR specification, though they are a consideration for out-of-band (fDATA / 2 - fDAC / 2) SFDR and may depend on the relationship of the DATACLK to DAC update clock (see the Data Clock section). When specifying the output reconstruction filter for other than baseband signals, these images should not be ignored. Clock Interface The MAX5894 features a flexible differential clock input (CLKP, CLKN) with a separate supply (AV CLK ) to achieve optimum jitter performance. It uses an ultra-low jitter clock to achieve the required noise density. Clock jitter must be less than 0.5psRMS to meet the specified noise density. For that reason, the CLKP/CLKN input source must be designed carefully. The differential clock (CLKN and CLKP) input can be driven from a single-ended or a differential clock source. Differential clock drive is required to achieve the best dynamic performance from the DAC. For single-ended operation, drive CLKP with a low noise source and bypass CLKN to GND with a 0.1F capacitor. The CLKP and CLKN pins are internally biased to AV CLK / 2. This allows the user to AC-couple clock fS / 4 IMAGES vs. CLKP/CLKN to DATACLK DELAY fDATA = 125Mwps, 4x INTERPOLATION -50 -60 IMAGE LEVEL (dBc) Applications Information fS / 4 - fOUT -70 -80 -90 fS / 4 + fOUT -100 fOUT = 10MHz AOUT = -6dBFS -110 0 2 4 6 8 CLKP/CLKN DELAY (ns) Figure 14. Effect of CLKP/CLKN to DATACLK Phase on fS / 4 Images ______________________________________________________________________________________ 25 MAX5894 Power-Down Mode The MAX5894 features three power-saving modes. Each DAC can be individually powered down through bits 2 and 3 of address 00h. The interpolation filters can also be powered down through bit 4 of address 00h, preserving the output level of each DAC (the DACs remain powered). Powering down both DACs automatically puts the MAX5894 into full power-down, including the interpolation filters. MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs sources directly to the device without external resistors to define the DC level. The input resistance of CLKP and CLKN is 5k. A convenient way to apply a differential signal is with a balun transformer as shown in Figure 15. Alternatively, these inputs may be driven from a CMOS-compatible 100nF CLKP SINGLE-ENDED IINPUT MINI-CIRCUITS ADTL1-12 24.9 MAX5894 1:1 RATIO 24.9 100nF CLKN Figure 15. Single-Ended-to-Differential Clock Conversion Using a Balun Transformer clock source, however it is recommended to use sine-wave or AC-coupled differential ECL/PECL drive for best dynamic performance. Output Interface (OUTI, OUTQ) The MAX5894 outputs complementary currents (OUTIP, OUTIN, OUTQP, and OUTQN) that can be utilized in a differential configuration. Load resistors convert these two output currents into a differential output voltage. The differential output between OUTIP (OUTQP) and OUTIN (OUTQN) can be converted to a single-ended output using a transformer or a differential amplifier. Figure 16 shows a typical transformer-based application circuit for generation of IF output signals. In this configuration, the MAX5894 operates in differential mode, which reduces even-order harmonics, and increases the available output power. Pay close attention to the transformer core saturation characteristics when selecting a transformer. Transformer core saturation can introduce strong second harmonic distortion, especially at low output frequencies and high signal amplitudes. It is recommended to connect the transformer center tap to ground. 50 1:1 OUTIP IDAC VIOUT, SINGLE-ENDED 100 14 1:1 OUTIN 50 MAX5894 50 1:1 OUTQP QDAC VQOUT, SINGLE-ENDED 100 14 1:1 OUTQN 50 Figure 16. Differential-to-Single-Ended Conversion Using Wideband RF Transformers 26 ______________________________________________________________________________________ 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs The distortion performance of the DAC also depends on the load impedance. The MAX5894 is optimized for a 50 double termination. It can be used with a transformer output as shown in Figure 16 or just one 25 resistor from each output to ground and one 50 resistor between the outputs (Figure 17). Higher output termination resistors can be used, as long as each output voltage does not exceed +1V with respect to GND, but at the cost of degraded distortion performance and increased output noise voltage. Reference Input/Output The MAX5894 supports operation with the on-chip 1.2V bandgap reference or an external reference voltage source. REFIO serves as the input for an external, lowimpedance reference source, and as the output if the DAC is operating with the internal reference. For stable operation with the internal reference, REFIO should be decoupled to GND with a 1F capacitor. MAX5894 If a transformer is not used, the outputs must have a resistive termination to ground. Figure 17 shows the MAX5894 output configured for differential DC-coupled mode. The DC-coupled configuration can be used to eliminate waveform distortion due to highpass filter effects. Applications include communication systems employing analog quadrature upconverters and requiring a high-speed DAC for baseband I/Q synthesis. If a single-ended DC-coupled unipolar output is desirable, OUTIP (OUTQP) should be selected as the output, and connect OUTIN (OUTQN) to ground. Using the MAX5894 output single-ended is not recommended because it introduces additional noise and distortion. 25 OUTIP IDAC 50 14 OUTIN 25 MAX5894 25 OUTQP QDAC 50 14 OUTQN 25 Figure 17. The DC-Coupled Differential Output Configuration ______________________________________________________________________________________ 27 MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs REFIO must be buffered with an external amplifier, if heavy loading is required, due to its 10k output resistance. Alternatively, apply a temperature-stable external reference to REFIO (Figure 18). The internal reference is overdriven by the external reference. For improved accuracy and drift performance, choose a fixed output voltage reference such as the MAX6520 bandgap reference. The MAX5894's reference circuit (Figure 19) employs a control amplifier, designed to regulate the full-scale cur- rent IOUT for the differential current outputs of the DAC. The output current can be calculated as: IOUTFS = 32 x IREF x 16383 / 16384 where IREF is the reference output current (IREF = VREFIO / RSET). Located between FSADJ and DACREF, RSET is the reference resistor, which determines the amplifier's output current for the DAC. Use Table 5 for a matrix of different IOUTFS and RSET selections. 1.2V REFERENCE 1.2V REFERENCE MAX5894 MAX5894 10k EXTERNAL 1.25V REFERENCE 10k REFIO REFIO 1F 1F FSADJ FSADJ CURRENTSOURCE ARRAY DAC IREF RSET CURRENTSOURCE ARRAY DAC IREF RSET DACREF DACREF Figure 18. Typical External Reference Circuit Figure 19. MAX5894 Internal Reference Architecture Table 5. IOUTFS and RSET Selection Matrix Based on a Typical 1.20V Reference Voltage FULL-SCALE CURRENT REFERENCE CURRENT IOUTFS (mA) IREF (A) CALCULATED 1% EIA STD 2 62.50 19.2 19.1 100 5 156.26 7.68 7.5 250 10 312.50 3.84 3.83 500 15 468.75 2.56 2.55 750 20 625.00 1.92 1.91 1000 RSET (k) OUTPUT VOLTAGE VIOUTP/N* (mVP-P) *Terminated into a 50 load. 28 ______________________________________________________________________________________ 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs Grounding and power-supply decoupling strongly influence the MAX5894 performance. Unwanted digital crosstalk can couple through the input, reference, power-supply, and ground connections, which can affect dynamic specifications like signal-to-noise ratio or spurious-free dynamic range. In addition, electromagnetic interference (EMI) can either couple into or be generated by the MAX5894. Observe the grounding and power-supply decoupling guidelines for highspeed, high-frequency applications. Follow the powersupply and filter configuration guidelines to achieve optimum dynamic performance. Using a multilayer printed circuit (PC) board with separate ground and power-supply planes, run high-speed signals on lines directly above the ground plane. Since the MAX5894 has separate analog and digital sections, the PC board should include separate analog and digital ground sections with only one point connecting the three planes at the exposed paddle under the MAX5894. Run digital signals above the digital ground plane and analog/clock signals above the analog/clock ground plane. Keep digital signals as far away from sensitive analog inputs, reference lines, and clock inputs as practical. Use a symmetric design of clock input and the analog output lines to minimize 2nd-order harmonic distortion components, thus optimizing the dynamic performance of the DAC. Keep digital signal paths short and run lengths matched to avoid propagation delay and data skew mismatches. The MAX5894 requires five separate power-supply inputs for the analog (AVDD1.8 and AVDD3.3), digital (DVDD1.8 and DVDD3.3), and clock (AVCLK) circuitry. Decouple each voltage supply pin with a separate 0.1F capacitor as close to the device as possible and with the shortest possible connection to the appropriate ground plane. Minimize the analog and digital load capacitances for optimized operation. Decouple all power-supply voltages at the point they enter the PC board with tantalum or electrolytic capacitors. Ferrite beads with additional decoupling capacitors forming a pi-network could also improve performance. The exposed paddle MUST be soldered to the ground. Use multiple vias, an array of at least 4 x 4 vias, directly under the EP to provide a low thermal and electrical impedance path for the IC. Static Performance Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from either a best straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every individual step. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step height and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. Offset Error The offset error is the difference between the ideal and the actual offset current. For a DAC, the offset point is the average value at the output for the two midscale digital input codes with respect to the full-scale of the DAC. This error affects all codes by the same amount. Gain Error A gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. Dynamic Performance Parameter Definitions Settling Time The settling time is the amount of time required from the start of a transition until the DAC output settles its new output value to within the specified accuracy. Noise Spectral Density The DAC output noise is the sum of the quantization noise and thermal noise. Noise spectral density is the noise power in 1Hz bandwidth, specified in dBFS/Hz. Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog output (RMS value) to the RMS quantization error (residual error). The ideal, theoretical maximum SNR can be derived from the DAC's resolution (N bits): SNRdB = 6.02dB x N + 1.76dB ______________________________________________________________________________________ 29 MAX5894 Power Supplies, Bypassing, Decoupling, and Layout MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs However, noise sources such as thermal noise, reference noise, clock jitter, etc., affect the ideal reading. Therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four harmonics, and the DC offset. Two-/Four-Tone Intermodulation Distortion (IMD) The two-tone IMD is the ratio expressed in dBc (or dBFS) of the worst 3rd-order (or higher) IMD products to either output tone. Spurious-Free Dynamic Range (SFDR) Adjacent Channel Leakage Power Ratio (ACLR) SFDR is the ratio of the RMS amplitude of the carrier frequency (maximum signal components) to the RMS value of their next largest distortion component. SFDR is usually measured in dBc and with respect to the carrier frequency amplitude or in dBFS with respect to the DAC's full-scale range. Depending on its test condition, SFDR is observed within a predefined window or to Nyquist. Commonly used in combination with WCDMA (wideband code-division multiple-access), ACLR reflects the leakage power ratio in dB between the measured powers within a channel relative to its adjacent channel. ACLR provides a quantifiable method of determining out-of-band spectral energy and its influence on an adjacent channel when a bandwidth-limited RF signal passes through a nonlinear device. 30 ______________________________________________________________________________________ 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs 63 62 61 60 59 58 AVDD1.8 FSADJ GND AVDD3.3 GND OUTQN OUTQP GND AVDD3.3 GND OUTIN GND 67 66 65 64 OUTIP AVDD3.3 AVDD1.8 68 GND AVCLK TOP VIEW 57 56 55 54 53 52 EXPOSED PADDLE CLKP 1 CLKN 2 50 REFIO N.C. 3 49 RESET N.C. 4 48 CS N.C. 5 47 SCLK DVDD1.8 6 46 DIN A13 7 45 DOUT A12 8 A11 9 51 DACREF 44 DVDD3.3 MAX5894 43 N.C. A10 10 42 N.C. A9 11 41 B0 A8 12 DVDD3.3 13 40 B1 DATACLK 14 38 B3 39 B2 A7 15 37 DVDD1.8 A6 16 36 B4 A5 17 35 B5 B6 B7 B8 B9 DVDD1.8 B10 B11 DATACLK/B12 SELIQ/B13 N.C. N.C. A0 A1 DVDD1.8 A2 A3 A4 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 QFN ______________________________________________________________________________________ 31 MAX5894 Pin Configuration Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 68L QFN.EPS MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2 PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.