0
0.5
1
1.5
2
2.5
3
3.5
4
0 2 4 6 8 10 12
VGS - Gate-to- Source Voltage (V)
RDS(on) - On-State Resistance (mΩ)
TC = 25°C Id = 30A
TC = 125ºC Id = 30A
G001
0
2
4
6
8
10
0 10 20 30 40 50 60 70 80
Qg - Gate Charge (nC)
VGS - Gate-to-Source Voltage (V)
ID = 30A
VDS =15V
G001
1D
2D
3D
4
D
D
5
G
6S
7
S
8S
P0093-01
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CSD16556Q5B
SLPS432C –NOVEMBER 2012–REVISED JANUARY 2015
CSD16556Q5B 25-V N-Channel NexFET™ Power MOSFET
1 Features Product Summary
1• Extremely Low Resistance TA= 25°C TYPICAL VALUE UNIT
• Ultralow Qgand Qgd VDS Drain-to-Source Voltage 25 V
• Low Thermal Resistance QgGate Charge Total (4.5 V) 36 nC
Qgd Gate Charge Gate-to-Drain 12 nC
• Avalanche Rated VGS = 4.5 V 1.2 mΩ
• Pb Free Terminal Plating RDS(on) Drain-to-Source On-Resistance VGS = 10 V 0.9 mΩ
• RoHS Compliant VGS(th) Threshold Voltage 1.4 V
• Halogen Free
• SON 5-mm × 6-mm Plastic Package .
Ordering Information(1)
2 Applications Device Media Qty Package Ship
CSD16556Q5B 13-Inch Reel 2500
• Point-of-Load Synchronous Buck in Networking, SON 5 x 6 mm Tape and
Plastic Package Reel
CSD16556Q5BT 7-Inch Reel 250
Telecom, and Computing Systems
• Optimized for Synchronous FET Applications (1) For all available packages, see the orderable addendum at
the end of the data sheet.
3 Description Absolute Maximum Ratings
This 25 V, 0.9 mΩ, 5 × 6 mm SON NexFET™ power TA= 25°C VALUE UNIT
MOSFET is designed to minimize losses in VDS Drain-to-Source Voltage 25 V
synchronous rectification and other power conversion VGS Gate-to-Source Voltage ±20 V
applications. Continuous Drain Current (Package limited) 100 A
Top View Continuous Drain Current (Silicon limited),
ID263
TC= 25°C
Continuous Drain Current(1) 40 A
IDM Pulsed Drain Current(2) 400 A
Power Dissipation(1) 3.2
PDW
Power Dissipation, TC= 25°C 191
TJ, Operating Junction and –55 to 150 °C
Tstg Storage Temperature Range
Avalanche Energy, single pulse
EAS 530 mJ
ID= 103 A, L = 0.1 mH, RG= 25 Ω
(1) Typical RθJA = 40°C/W on 1-inch2(6.45-cm2), 2-oz. (0.071-
mm thick) Cu pad on a 0.06-inch (1.52-mm) thick FR4 PCB.
(2) Max RθJC = 1.3°C/W, Pulse duration ≤100 μs, duty cycle ≤1%
RDS(on) vs VGS Gate Charge
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD16556Q5B
SLPS432C –NOVEMBER 2012–REVISED JANUARY 2015
www.ti.com
Table of Contents
6.1 Trademarks............................................................... 7
1 Features.................................................................. 16.2 Electrostatic Discharge Caution................................ 7
2 Applications ........................................................... 16.3 Glossary.................................................................... 7
3 Description............................................................. 17 Mechanical, Packaging, and Orderable
4 Revision History..................................................... 2Information............................................................. 8
5 Specifications......................................................... 37.1 Q5B Package Dimensions........................................ 8
5.1 Electrical Characteristics........................................... 37.2 Recommended PCB Pattern..................................... 9
5.2 Thermal Information.................................................. 37.3 Recommended Stencil Pattern ................................. 9
5.3 Typical MOSFET Characteristics.............................. 47.4 Q5B Tape and Reel Information............................. 10
6 Device and Documentation Support.................... 7
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2013) to Revision C Page
• Added part number to title ..................................................................................................................................................... 1
• Added 7 inch reel in Ordering Information ............................................................................................................................ 1
• Increase max pulsed current to 400 A .................................................................................................................................. 1
• Added line for max power dissipation with case temperature held to 25ºC .......................................................................... 1
• Updated pulsed current conditions ........................................................................................................................................ 1
• Updated Figure 1 to a normalized RθJC curve ....................................................................................................................... 4
• Updated the SOA in Figure 10 .............................................................................................................................................. 6
• Updated the mechanical drawing and dimensions table ....................................................................................................... 8
Changes from Revision A (December 2012) to Revision B Page
• Changed gƒs, Transconductance TYP value From: 2 S To: 191 S ........................................................................................ 3
Changes from Original (November 2012) to Revision A Page
• Changed the device from product preview to: Production .................................................................................................... 1
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SLPS432C –NOVEMBER 2012–REVISED JANUARY 2015
5 Specifications
5.1 Electrical Characteristics
(TA= 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-Source Voltage VGS = 0 V, IDS = 250 μA 25 V
IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 24 V 1 μA
IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = 20 V 100 nA
VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, IDS = 250 μA 1.2 1.4 1.7 V
VGS = 4.5 V, IDS = 30 A 1.2 1.5 mΩ
RDS(on) Drain-to-Source On-Resistance VGS = 10 V, IDS = 30 A 0.9 1.07 mΩ
gƒs Transconductance VDS = 15 V, IDS = 30 A 191 S
DYNAMIC CHARACTERISTICS
Ciss Input Capacitance 4750 6180 pF
VGS = 0 V, VDS = 15 V,
Coss Output Capacitance 2270 2950 pF
ƒ = 1MHz
Crss Reverse Transfer Capacitance 220 280 pF
RGSeries Gate Resistance 0.7 1.4 Ω
QgGate Charge Total (4.5 V) 36 47 nC
Qgd Gate Charge Gate-to-Drain 12 nC
VDS = 15 V, IDS = 30 A
Qgs Gate Charge Gate-to-Source 11 nC
Qg(th) Gate Charge at Vth 7 nC
Qoss Output Charge VDS = 15 V, VGS = 0 V 45 nC
td(on) Turn On Delay Time 17 ns
trRise Time 34 ns
VDS = 15 V, VGS = 4.5 V,
IDS = 30 A,RG= 2 Ω
td(off) Turn Off Delay Time 25 ns
tƒFall Time 13 ns
DIODE CHARACTERISTICS
VSD Diode Forward Voltage ISD = 30 A, VGS = 0 V 0.8 1 V
Qrr Reverse Recovery Charge 84 nC
VDD= 15 V, IF= 30 A, di/dt = 300 A/μs
trr Reverse Recovery Time 41 ns
5.2 Thermal Information
(TA= 25°C unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJC Junction-to-Case Thermal Resistance(1) 1.3 °C/W
RθJA Junction-to-Ambient Thermal Resistance(1)(2) 50
(1) RθJC is determined with the device mounted on a 1-inch2(6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inches × 1.5-inches
(3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board
design.
(2) Device mounted on FR4 material with 1-inch2(6.45-cm2), 2-oz. (0.071-mm thick) Cu.
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GATE Source
DRAIN
N-Chan5x6QFNTTAMAXRev3
M0137-01
GATE Source
DRAIN
N-Chan5x6QFNTTAMINRev3
M0137-02
CSD16556Q5B
SLPS432C –NOVEMBER 2012–REVISED JANUARY 2015
www.ti.com
Max RθJA = 50°C/W Max RθJA = 125°C/W
when mounted on when mounted on a
1 inch2(6.45 cm2) of minimum pad area of
2-oz. (0.071-mm thick) 2-oz.
Cu. (0.071-mm thick) Cu.
5.3 Typical MOSFET Characteristics
(TA= 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
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SLPS432C –NOVEMBER 2012–REVISED JANUARY 2015
Typical MOSFET Characteristics (continued)
(TA= 25°C unless otherwise stated)
Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics
Figure 4. Gate Charge Figure 5. Capacitance
Figure 6. Threshold Voltage vs Temperature Figure 7. On-State Resistance vs Gate-to-Source Voltage
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SLPS432C –NOVEMBER 2012–REVISED JANUARY 2015
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Typical MOSFET Characteristics (continued)
(TA= 25°C unless otherwise stated)
Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage
Figure 10. Maximum Safe Operating Area (SOA) Figure 11. Single Pulse Unclamped Inductive Switching
Figure 12. Maximum Drain Current vs Temperature
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SLPS432C –NOVEMBER 2012–REVISED JANUARY 2015
6 Device and Documentation Support
6.1 Trademarks
NexFET is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
6.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.3 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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D1
Top View
E
c1
ө
E1
4
1 2 3
Side View Bottom View
Front View
14
b (8x)
3
2
e
L
K
H
D2
8
5 6 7
ө
8
5 6 7
D3
d1
d2
CSD16556Q5B
SLPS432C –NOVEMBER 2012–REVISED JANUARY 2015
www.ti.com
7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Q5B Package Dimensions
MILLIMETERS
DIM MIN NOM MAX
A 0.80 1.00 1.05
b 0.36 0.41 0.46
c 0.15 0.20 0.25
c1 0.15 0.20 0.25
c2 0.20 0.25 0.30
D1 4.90 5.00 5.10
D2 4.12 4.22 4.32
D3 3.90 4.00 4.10
d 0.20 0.25 0.30
d1 0.085 TYP
d2 0.319 0.369 0.419
E 4.90 5.00 5.10
E1 5.90 6.00 6.10
E2 3.48 3.58 3.68
e 1.27 TYP
H 0.36 0.46 0.56
L 0.46 0.56 0.66
L1 0.57 0.67 0.77
θ0° — —
K 1.40 TYP
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4.318 (0.170)
2.186
6.586
0.350
(0.014)
1.294
x 8
(0.051)
0.746 x 8
(0.029)
(0.259)
1.072
(0.042)
1.270
0.562 x 4
(0.022)
0.300
(0.012)
(0.086)
(0.050)
1.525
(0.060)
0.508
x4
(0.020)
1.270 (0.050)
0.286
(0.011)
0.766
(0.030)
C
L
C
L
SYM
0.590
(0.023)
4.440
(0.175)
1.100
(0.043)
85
14
4.520
(0.178)
3.456 0.984
(0.136) (0.039)
1.372
(0.054)
0.710 (0.028)
0.710
(0.028)
1.270 (0.028)
0.560 (0.022)
CSD16556Q5B
www.ti.com
SLPS432C –NOVEMBER 2012–REVISED JANUARY 2015
7.2 Recommended PCB Pattern
For recommended circuit layout for PCB designs, see application note SLPA005 –Reducing Ringing Through
PCB Layout Techniques.
7.3 Recommended Stencil Pattern
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Ø 1.50 +0.10
–0.00
4.00 ±0.10 (See Note 1)
1.75 ±0.10
R 0.30 TYP
Ø 1.50 MIN
A0
K0
0.30 ±0.05
R 0.30 MAX
A0 = 6.50 ±0.10
B0 = 5.30 ±0.10
K0 = 1.40 ±0.10
M0138-01
2.00 ±0.05
8.00 ±0.10
B0
12.00 ±0.30
5.50 ±0.05
CSD16556Q5B
SLPS432C –NOVEMBER 2012–REVISED JANUARY 2015
www.ti.com
7.4 Q5B Tape and Reel Information
Notes:
1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm (unless otherwise specified).
5. A0 and B0 measured on a plane 0.3 mm above the bottom of the pocket.
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PACKAGE OPTION ADDENDUM
www.ti.com 30-Dec-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CSD16556Q5B ACTIVE VSON-CLIP DNK 8 2500 Pb-Free (RoHS
Exempt) CU SN Level-1-260C-UNLIM -55 to 150 CSD16556
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 30-Dec-2014
Addendum-Page 2
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