LTC2335ILX-18#PBF - LINEAR TECHNOLOGY

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

Typical applicaTion

FeaTures DescripTion

18-Bit, 1Msps 8-Channel

Differential ±10.24V Input SoftSpan ADC

with Wide Input Common Mode Range

The LT C

2335-18 is an 18-bit, low noise 8-channel multi-

plexed successive approximation register (SAR) ADC with

differential, wide common mode range inputs. Operating

from a 5V low voltage supply, flexible high voltage supplies,

and using the internal reference and buffer, this SoftSpan

ADC can be configured on a conversion-by-conversion

basis to accept ±10.24V, 0V to 10.24V, ±5.12V, or 0V to

5.12V signals on any channel. Alternately, the ADC may

be programmed to cycle through a sequence of channels

and ranges without further user intervention.

The wide input common mode range and 118dB CMRR of

the LTC2335-18 analog inputs allow the ADC to directly

digitize a variety of signals, simplifying signal chain de-

sign. This input signal flexibility, combined with ±3LSB

INL, no missing codes at 18 bits, and 96.7dB SNR, makes

the LTC2335-18 an ideal choice for many high voltage

applications requiring wide dynamic range.

The LTC2335-18 supports pin-selectable SPI CMOS (1.8V

to 5V) and LVDS serial interfaces.

L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners. Protected by U.S. Patents, including 7705765, 7961132, 8319673.

Other Patents pending.

applicaTions

n 1Msps Throughput

n ±3LSB INL (Maximum, ±10.24V Range)

n Guaranteed 18-Bit, No Missing Codes

n Differential, Wide Common Mode Range Inputs

n 8-Channel Multiplexer with SoftSpan Input Ranges:

±10.24V, 0V to 10.24V, ±5.12V, 0V to 5.12V

±12.5V, 0V to 12.5V, ±6.25V, 0V to 6.25V

n 96.7dB Single-Conversion SNR (Typical)

n −109dB THD (Typical) at fIN = 2kHz

n 118dB CMRR, 125dB Active Crosstalk (Typical)

n Rail-to-Rail Input Overdrive Tolerance

n Programmable Sequencer with No-Latency Control

n Guaranteed Operation to 125°C

n Integrated Reference and Buffer (4.096V)

n SPI CMOS (1.8V to 5V) and LVDS Serial I/O

n No Pipeline Delay, No Cycle Latency

n 180mW Power Dissipation (Typical)

n 48-Lead (7mm × 7mm) LQFP Package

n Programmable Logic Controllers

n Industrial Process Control

n Power Line Monitoring

n Test and Measurement

Integral Nonlinearity vs

Output Code and Channel

0.1µF2.2µF0.1µF0.1µF

1.8V TO 5V5V15V

–15V

SAMPLE

CLOCK

233518 TA01a

MUX

VCC VDD VDDLBYP OVDD

DIFFERENTIAL INPUTS IN+/IN– WITH

WIDE INPUT COMMON MODE RANGE

+10V

–10V

TRUE BIPOLAR

+10V

–10V

ARBITRARY

+10V

–10V

UNIPOLAR

SDO

SCKO

SCKI

SDI

BUSY

CNV

• • •

LVDS/CMOS

IN0+

IN0–

IN7+

IN7–

18-BIT

SAMPLING

ADC

CMOS OR LVDS

I/O INTERFACE

0.1µF

REFIN

47µF

0.1µF

GNDREFBUFVEE

LTC2335-18

+5V

–5V

FULLY

DIFFERENTIAL

±10.24V RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

ALL CHANNELS

OUTPUT CODE

–131072

–65536

65536

131072

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

INL ERROR (LSB)

233518 TA01b

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

pin conFiguraTionabsoluTe MaxiMuM raTings

Supply Voltage (VCC) .....................–0.3V to (VEE + 40V)

Supply Voltage (VEE) ................................ –17.4V to 0.3V

Supply Voltage Difference (VCC – VEE) ......................40V

Supply Voltage (VDD) ..................................................6V

Supply Voltage (OVDD) ................................................6V

Internal Regulated Supply Bypass (VDDLBYP) ... (Note 3)

Analog Input Voltage

IN0+ to IN7+,

IN0– to IN7– (Note 4) ......... (VEE – 0.3V) to (VCC + 0.3V)

REFIN .................................................... –0.3V to 2.8V

REFBUF, CNV (Note 5) ............. –0.3V to (VDD + 0.3V)

Digital Input Voltage (Note 5) ..... –0.3V to (OVDD + 0.3V)

Digital Output Voltage (Note 5) .. –0.3V to (OVDD + 0.3V)

Power Dissipation .............................................. 500mW

Operating Temperature Range

LTC2335C ................................................ 0°C to 70°C

LTC2335I .............................................–40°C to 85°C

LTC2335H .......................................... –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

(Notes 1, 2)

IN6–

IN6+

IN5–

IN5+

IN4–

IN4+

IN3–

IN3+

IN2–

IN2+

IN1–

IN1+

IN0–

IN0+

GND

VCC

VEE

GND

REFIN

GND

REFBUF

LVDS/CMOS

CNV

IN7+

IN7–

GND

VEE

GND

VDD

GND

VDDLBYP

BUSY

SDI

SCKO+/SCKO

OVDD

GND

SCKI–/SCKI

SCKI+

SDI–

SDI+

GND

SDO–

SDO+

SCKO–/SDO

TOP VIEW

LX PACKAGE

48-LEAD (7mm × 7mm) PLASTIC LQFP

TJMAX = 150°C, θJA = 53°C/W

orDer inForMaTion

LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2335CLX-18#PBF LTC2335CLX-18#PBF LTC2335LX-18 48-Lead (7mm × 7mm) Plastic LQFP 0°C to 70°C

LTC2335ILX-18#PBF LTC2335ILX-18#PBF LTC2335LX-18 48-Lead (7mm × 7mm) Plastic LQFP –40°C to 85°C

LTC2335HLX-18#PBF LTC2335HLX-18#PBF LTC2335LX-18 48-Lead (7mm × 7mm) Plastic LQFP –40°C to 125°C

Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

elecTrical characTerisTics

converTer characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN+ Absolute Input Range

(IN0+ to IN7+)

(Note 7) lVEE VCC – 4 V

VIN– Absolute Input Range

(IN0– to IN7–)

(Note 7) lVEE VCC – 4 V

VIN+ – VIN– Input Differential Voltage

Range

SoftSpan 7: ±2.5 • VREFBUF Range (Note 7)

SoftSpan 6: ±2.5 • VREFBUF/1.024 Range (Note 7)

SoftSpan 5: 0V to 2.5 • VREFBUF Range (Note 7)

SoftSpan 4: 0V to 2.5 • VREFBUF/1.024 Range (Note 7)

SoftSpan 3: ±1.25 • VREFBUF Range (Note 7)

SoftSpan 2: ±1.25 • VREFBUF/1.024 Range (Note 7)

SoftSpan 1: 0V to 1.25 • VREFBUF Range (Note 7)

SoftSpan 0: 0V to 1.25 • VREFBUF/1.024 Range (Note 7)

–2.5 • VREFBUF

–2.5 • VREFBUF/1.024

–1.25 • VREFBUF

–1.25 • VREFBUF/1.024

2.5 • VREFBUF

2.5 • VREFBUF/1.024

2.5 • VREFBUF

2.5 • VREFBUF/1.024

1.25 • VREFBUF

1.25 • VREFBUF/1.024

1.25 • VREFBUF

1.25 • VREFBUF/1.024

VCM Input Common Mode Voltage

Range

(Note 7) lVEE VCC – 4 V

VIN+ – VIN– Input Differential Overdrive

Tolerance

(Note 8) l−(VCC − VEE) (VCC − VEE) V

IIN Analog Input Leakage Current l–1 1 µA

CIN Analog Input Capacitance Sample Mode

Hold Mode

CMRR Input Common Mode

Rejection Ratio

VIN+ = VIN− = 18VP-P 200Hz Sine l100 118 dB

VIHCNV CNV High Level Input Voltage l1.3 V

VILCNV CNV Low Level Input Voltage l0.5 V

IINCNV CNV Input Current VIN = 0V to VDD l–10 10 μA

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution l18 Bits

No Missing Codes l18 Bits

Transition Noise SoftSpans 7 and 6: ±10.24V and ±10V Ranges

SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges

SoftSpans 3 and 2: ±5.12V and ±5V Ranges

SoftSpans 1 and 0: 0V to 5.12V and 0V to 5V Ranges

1.3

2.6

2.0

4.0

LSBRMS

INL Integral Linearity Error SoftSpans 7 and 6: ±10.24V and ±10V Ranges (Note 10)

SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges (Note 10)

SoftSpans 3 and 2: ±5.12V and ±5V Ranges (Note 10)

SoftSpans 1 and 0: 0V to 5.12V and 0V to 5V Ranges (Note 10)

–3

–4

–2.5

±1

±1.5

±0.75

2.5

LSB

DNL Differential Linearity Error (Note 11) l−0.9 ±0.2 0.9 LSB

ZSE Zero-Scale Error (Note 12) l−550 ±80 550 μV

Zero-Scale Error Drift ±2 μV/°C

FSE Full-Scale Error (Note 12) l−0.1 ±0.025 0.1 %FS

Full-Scale Error Drift ±2.5 ppm/°C

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 6)

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 9)

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

DynaMic accuracy

inTernal reFerence characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SINAD Signal-to-(Noise +

Distortion) Ratio

SoftSpans 7 and 6: ±10.24V and ±10V Ranges, fIN = 2kHz

SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz

SoftSpans 3 and 2: ±5.12V and ±5V Ranges, fIN = 2kHz

SoftSpans 1 and 0: 0V to 5.12V and 0V to 5V Ranges, fIN = 2kHz

93.0

87.6

90.0

84.2

96.5

90.6

93.2

87.3

SNR Signal-to-Noise Ratio SoftSpans 7 and 6: ±10.24V and ±10V Ranges, fIN = 2kHz

SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz

SoftSpans 3 and 2: ±5.12V and ±5V Ranges, fIN = 2kHz

SoftSpans 1 and 0: 0V to 5.12V and 0V to 5V Ranges, fIN = 2kHz

93.7

87.7

90.2

84.3

96.7

90.7

93.2

87.3

THD Total Harmonic Distortion SoftSpans 7 and 6: ±10.24V and ±10V Ranges, fIN = 2kHz

SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz

SoftSpans 3 and 2: ±5.12V and ±5V Ranges, fIN = 2kHz

SoftSpans 1 and 0: 0V to 5.12V and 0V to 5V Ranges, fIN = 2kHz

–109

–111

–113

–114

–101

–99

–104

–103

SFDR Spurious Free Dynamic

Range

SoftSpans 7 and 6: ±10.24V and ±10V Ranges, fIN = 2kHz

SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz

SoftSpans 3 and 2: ±5.12V and ±5V Ranges, fIN = 2kHz

SoftSpans 1 and 0: 0V to 5.12V and 0V to 5V Ranges, fIN = 2kHz

101

105

110

112

114

115

Channel-to-Channel

Active Crosstalk

Alternating Conversions with 18VP-P 200Hz Sine in ±10.24V

Range, Crosstalk to Any Other Channel

–125 dB

–3dB Input Bandwidth 7 MHz

Aperture Delay 1 ns

Aperture Delay Matching 150 ps

Aperture Jitter 3 psRMS

Transient Response Full-Scale Step, 0.005% Settling 360 ns

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VREFIN Internal Reference Output Voltage 2.043 2.048 2.053 V

Internal Reference Temperature Coefficient (Note 14) l5 20 ppm/°C

Internal Reference Line Regulation VDD = 4.75V to 5.25V 0.1 mV/V

Internal Reference Output Impedance 20 kΩ

VREFIN REFIN Voltage Range REFIN Overdriven (Note 7) 1.25 2.2 V

The l denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Notes 9, 13)

The l denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at TA = 25°C. (Note 9)

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

reFerence buFFer characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VREFBUF Reference Buffer Output Voltage REFIN Overdriven, VREFIN = 2.048V l4.091 4.096 4.101 V

REFBUF Voltage Range REFBUF Overdriven (Notes 7, 15) l2.5 5 V

REFBUF Input Impedance VREFIN = 0V, Buffer Disabled 13 kΩ

IREFBUF REFBUF Load Current VREFBUF = 5V, (Notes 15, 16)

VREFBUF = 5V, Acquisition or Nap Mode (Note 15)

l1.1

0.39

1.4 mA

The l denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at TA = 25°C. (Note 9)

DigiTal inpuTs anD DigiTal ouTpuTs

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

CMOS Digital Inputs and Outputs

VIH High Level Input Voltage l0.8•OVDD V

VIL Low Level Input Voltage l0.2•OVDD V

IIN Digital Input Current VIN = 0V to OVDD l–10 10 μA

CIN Digital Input Capacitance 5 pF

VOH High Level Output Voltage IOUT = –500μA lOVDD–0.2 V

VOL Low Level Output Voltage IOUT = 500μA l0.2 V

IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l–10 10 μA

ISOURCE Output Source Current VOUT = 0V –50 mA

ISINK Output Sink Current VOUT = OVDD 50 mA

LVDS Digital Inputs and Outputs

VID Differential Input Voltage l200 350 600 mV

RID On-Chip Input Termination

Resistance

CS = 0V, VICM = 1.2V

CS = OVDD

l90 106

125 Ω

MΩ

VICM Common-Mode Input Voltage l0.3 1.2 2.2 V

IICM Common-Mode Input Current VIN+ = VIN– = 0V to OVDD l–10 10 μA

VOD Differential Output Voltage RL = 100Ω Differential Termination l275 350 425 mV

VOCM Common-Mode Output Voltage RL = 100Ω Differential Termination l1.1 1.2 1.3 V

IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l–10 10 μA

The l denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9)

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

power requireMenTs

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VCC Supply Voltage l0 38 V

VEE Supply Voltage l–16.5 0 V

VCC − VEE Supply Voltage Difference l10 38 V

VDD Supply Voltage l4.75 5.00 5.25 V

IVCC Supply Current 1Msps Sample Rate

Acquisition Mode

Nap Mode

Power Down Mode

3.5

3.8

0.7

4.3

4.5

0.9

μA

IVEE Supply Current 1Msps Sample Rate

Acquisition Mode

Nap Mode

Power Down Mode

–5.1

–4.9

–1.1

–15

–4.0

–0.8

–1

μA

CMOS I/O Mode

OVDD Supply Voltage l1.71 5.25 V

IVDD Supply Current 1Msps Sample Rate

1Msps Sample Rate, VREFBUF = 5V (Note 15)

Acquisition Mode

Nap Mode

Power Down Mode (C-Grade and I-Grade)

Power Down Mode (H-Grade)

12.6

11.3

1.6

1.4

14.5

13.0

2.1

1.9

175

450

μA

µA

IOVDD Supply Current 1Msps Sample Rate (CL = 25pF)

Acquisition or Nap Mode

Power Down Mode

2.6

4.2

μA

PDPower Dissipation 1Msps Sample Rate

Acquisition Mode

Nap Mode

Power Down Mode (C-Grade and I-Grade)

Power Down Mode (H-Grade)

182

125

0.36

224

152

1.4

2.8

LVDS I/O Mode

OVDD Supply Voltage l2.375 5.25 V

IVDD Supply Current 1Msps Sample Rate

1Msps Sample Rate, VREFBUF = 5V (Note 15)

Acquisition Mode

Nap Mode

Power Down Mode (C-Grade and I-Grade)

Power Down Mode (H-Grade)

14.8

13.8

3.2

3.0

17.1

15.9

3.8

3.7

175

450

μA

µA

IOVDD Supply Current 1Msps Sample Rate, (RL = 100Ω)

Acquisition or Nap Mode (RL = 100Ω)

Power Down Mode

8.5

8.0

μA

PDPower Dissipation 1Msps Sample Rate

Acquisition Mode

Nap Mode

Power Down Mode (C-Grade and I-Grade)

Power Down Mode (H-Grade)

204

151

0.36

248

180

1.4

2.8

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. (Note 9)

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

aDc TiMing characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fSMPL Maximum Sampling Frequency l1 Msps

tCYC Time Between Conversions l1 μs

tCONV Conversion Time l450 500 550 ns

tACQ Acquisition Time (tACQ = tCYC – tCONV – tBUSYLH)l420 480 ns

tCNVH CNV High Time l40 ns

tCNVL CNV Low Time l420 ns

tBUSYLH CNV↑ to BUSY Delay CL = 25pF l30 ns

tQUIET Digital I/O Quiet Time from CNV↑l20 ns

tPDH PD High Time l40 ns

tPDL PD Low Time l40 ns

tWAKE REFBUF Wake-Up Time CREFBUF = 47μF, CREFIN = 0.1μF 200 ms

CMOS I/O Mode

tSCKI SCKI Period (Notes 17, 18) l10 ns

tSCKIH SCKI High Time l4 ns

tSCKIL SCKI Low Time l4 ns

tSSDISCKI SDI Setup Time from SCKI↑(Note 17) l2 ns

tHSDISCKI SDI Hold Time from SCKI↑(Note 17) l1 ns

tDSDOSCKI SDO Data Valid Delay from SCKI↑CL = 25pF (Note 17) l7.5 ns

tHSDOSCKI SDO Remains Valid Delay from SCKI↑CL = 25pF (Note 17) l1.5 ns

tSKEW SDO to SCKO Skew (Note 17) l–1 0 1 ns

tDSDOBUSYL SDO Data Valid Delay from BUSY↓CL = 25pF (Note 17) l0 ns

tEN Bus Enable Time After CS↓(Note 17) l15 ns

tDIS Bus Relinquish Time After CS↑(Note 17) l15 ns

LVDS I/O Mode

tSCKI SCKI Period (Note 19) l4 ns

tSCKIH SCKI High Time (Note 19) l1.5 ns

tSCKIL SCKI Low Time (Note 19) l1.5 ns

tSSDISCKI SDI Setup Time from SCKI (Notes 11, 19) l1.2 ns

tHSDISCKI SDI Hold Time from SCKI (Notes 11, 19) l–0.2 ns

tDSDOSCKI SDO Data Valid Delay from SCKI (Notes 11, 19) l6 ns

tHSDOSCKI SDO Remains Valid Delay from SCKI (Notes 11, 19) l1 ns

tSKEW SDO to SCKO Skew (Note 11) l–0.4 0 0.4 ns

tDSDOBUSYL SDO Data Valid Delay from BUSY↓(Note 11) l0 ns

tEN Bus Enable Time After CS↓l50 ns

tDIS Bus Relinquish Time After CS↑l15 ns

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 9)

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

CMOS Timings

LVDS Timings (Differential)

Figure 1. Voltage Levels for Timing Specifications

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to ground.

Note 3: VDDLBYP is the output of an internal voltage regulator, and should

only be connected to a 2.2μF ceramic capacitor to bypass the pin to GND,

as described in the Pin Functions section. Do not connect this pin to any

external circuitry.

Note 4: When these pin voltages are taken below VEE or above VCC, they

will be clamped by internal diodes. This product can handle input currents

of up to 100mA below VEE or above VCC without latch-up.

Note 5: When these pin voltages are taken below ground or above VDD or

OVDD, they will be clamped by internal diodes. This product can handle

currents of up to 100mA below ground or above VDD or OVDD without

latch-up.

Note 6: –16.5V ≤ VEE ≤ 0V, 0V ≤ VCC ≤ 38V, 10V ≤ (VCC – VEE) ≤ 38V,

VDD=5V, unless otherwise specified.

Note 7: Recommended operating conditions.

Note 8: Refer to Absolute Maximum Ratings section for pin voltage limits

related to device reliability.

Note 9: VCC = 15V, VEE = –15V, VDD = 5V, OVDD=2.5V, fSMPL = 1Msps,

internal reference and buffer, true bipolar input signal drive in bipolar

SoftSpan ranges, unipolar signal drive in unipolar SoftSpan ranges, unless

otherwise specified.

Note 10: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 11: Guaranteed by design, not subject to test.

Note 12: For bipolar SoftSpan ranges 7, 6, 3, and 2, zero-scale error is

the offset voltage measured from –0.5LSB when the output code flickers

between 00 0000 0000 0000 0000 and 11 1111 1111 1111 1111. Full-

scale error for these SoftSpan ranges is the worst-case deviation of the

first and last code transitions from ideal and includes the effect of offset

error. For unipolar SoftSpan ranges 5, 4, 1, and 0, zero-scale error is

the offset voltage measured from 0.5LSB when the output code flickers

between 00 0000 0000 0000 0000 and 00 0000 0000 0000 0001. Full-

scale error for these SoftSpan ranges is the worst-case deviation of the

last code transition from ideal and includes the effect of offset error.

Note 13: All specifications in dB are referred to a full-scale input in the

relevant SoftSpan input range, except for crosstalk, which is referred to

the crosstalk injection signal amplitude.

Note 14: Temperature coefficient is calculated by dividing the maximum

change in output voltage by the specified temperature range.

Note 15: When REFBUF is overdriven, the internal reference buffer must

be disabled by setting REFIN = 0V.

Note 16: IREFBUF varies proportionally with sample rate.

Note 17: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V,

and OVDD = 5.25V.

Note 18: A tSCKI period of 10ns minimum allows a shift clock frequency of

up to 100MHz for rising edge capture.

Note 19: VICM = 1.2V, VID = 350mV for LVDS differential input pairs.

aDc TiMing characTerisTics

0.8 • OVDD

0.2 • OVDD

50% 50%

233518 F01a

0.2 • OVDD

0.8 • OVDD

0.2 • OVDD

0.8 • OVDD

tDELAY

tWIDTH

tDELAY

+200mV

–200mV

0V 0V

233518 F01b

–200mV

+200mV

–200mV

+200mV

tDELAY

tWIDTH

tDELAY

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

Typical perForMance characTerisTics

Integral Nonlinearity

vs Output Code and Range

Integral Nonlinearity

vs Output Code and Range

Integral Nonlinearity

vs Output Code and Range

Integral Nonlinearity

vs Output Code DC Histogram (Zero-Scale) DC Histogram (Near Full-Scale)

Integral Nonlinearity

vs Output Code and Channel

Integral Nonlinearity

vs Output Code and Channel

Differential Nonlinearity

vs Output Code and Range

TA = 25°C, VCC=+15V, VEE=–15V, VDD=5V,

OVDD=2.5V, Internal Reference and Buffer (VREFBUF =4.096V), fSMPL = 1Msps, unless otherwise noted.

±10.24V RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

ALL CHANNELS

OUTPUT CODE

–131072

–65536

65536

131072

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

INL ERROR (LSB)

233518 G01

±10.24V RANGE

FULLY DIFFERENTIAL DRIVE (IN

–

= –IN

)

ALL CHANNELS

OUTPUT CODE

–131072

–65536

65536

131072

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

INL ERROR (LSB)

233518 G02

ALL RANGES

ALL CHANNELS

OUTPUT CODE

65536

131072

196608

262144

–0.5

–0.4

–0.3

–0.2

–0.1

0.0

0.1

0.2

0.3

0.4

0.5

DNL ERROR (LSB)

233518 G03

TRUE BIPOLAR DRIVE (IN

–

= 0V)

ONE CHANNEL

±10.24V AND ±10V

RANGES

±5.12V AND ±5V

RANGES

OUTPUT CODE

–131072

–65536

65536

131072

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

INL ERROR (LSB)

233518 G04

FULLY DIFFERENTIAL DRIVE (IN

–

= –IN

)

ONE CHANNEL

±10.24V, ±10V,

±5.12V, AND ±5V

RANGES

OUTPUT CODE

–131072

–65536

65536

131072

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

INL ERROR (LSB)

233518 G05

UNIPOLAR DRIVE (IN

–

= 0V)

ONE CHANNEL

0V to 5.12V AND

0V to 5V RANGES

0V to 10.24V AND

0V to 10V RANGES

OUTPUT CODE

65536

131072

196608

262144

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

INL ERROR (LSB)

233518 G06

±10.24V RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

ARBITRARY DRIVE

/IN

–

COMMON MODE

SWEPT –10.24V to 10.24V

OUTPUT CODE

–131072

–65536

65536

131072

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

INL ERROR (LSB)

233518 G07

±10.24V RANGE

σ = 1.3

CODE

–6

–4

–2

10000

20000

30000

40000

50000

60000

70000

80000

90000

COUNTS

233518 G08

±10.24V RANGE

σ = 1.4

CODE

130971

130974

130977

130980

130983

10000

20000

30000

40000

50000

60000

70000

80000

90000

COUNTS

233518 G09

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

Typical perForMance characTerisTics

32k Point FFT fSMPL = 1Msps,

fIN=2kHz

SNR, SINAD vs VREFBUF,

fIN=2kHz

THD, Harmonics vs VREFBUF,

fIN=2kHz

SNR, SINAD

vs Input Frequency

THD, Harmonics

vs Input Frequency

THD, Harmonics vs Input

Common Mode, fIN = 2kHz

32k Point FFT fSMPL=1Msps,

fIN=2kHz

32k Point FFT fSMPL=1Msps,

fIN=2kHz

32k Point Arbitrary Tw o -Tone FFT

fSMPL=1Msps, IN+=–7dBFS 2kHz

Sine, IN–=–7dBFS 3.1kHz Sine

TA = 25°C, VCC=+15V, VEE=–15V, VDD=5V,

OVDD=2.5V, Internal Reference and Buffer (VREFBUF =4.096V), fSMPL = 1Msps, unless otherwise noted.

±10.24V RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

SNR = 96.9dB

THD = –109dB

SINAD = 96.7dB

SFDR = 111dB

FREQUENCY (kHz)

100

200

300

400

500

–180

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

233518 G10

±10.24V RANGE

FULLY DIFFERENTIAL DRIVE (IN

–

= –IN

)

SNR = 96.7dB

THD = –124dB

SINAD = 96.7dB

SFDR = 119dB

FREQUENCY (kHz)

100

200

300

400

500

–180

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

233518 G11

±10.24V RANGE

ARBITRARY DRIVE

SFDR = 119dB

SNR = 96.7dB

FREQUENCY (kHz)

100

200

300

400

500

–180

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

233518 G12

±5.12V RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

SNR = 93.4dB

THD = –118dB

SINAD = 93.4dB

SFDR = 120dB

FREQUENCY (kHz)

100

200

300

400

500

–180

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

233518 G13

SNR

SINAD

±2.5 • V

REFBUF

RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

REFBUF VOLTAGE (V)

2.5

3.5

4.5

90.0

92.0

94.0

96.0

98.0

100.0

SNR, SINAD (dBFS)

233518 G14

THD

2ND

3RD

±2.5 • V

REFBUF

RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

REFBUF VOLTAGE (V)

2.5

3.5

4.5

–130

–125

–120

–115

–110

–105

–100

THD, HARMONICS (dBFS)

233518 G15

SNR

SINAD

±10.24V RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

FREQUENCY (Hz)

100

10k

100k

76.0

80.0

84.0

88.0

92.0

96.0

100.0

SNR, SINAD (dBFS)

233518 G16

THD

2ND

3RD

±10.24V RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

FREQUENCY (Hz)

100

10k

100k

–130

–120

–110

–100

–90

–80

–70

THD, HARMONICS (dBFS)

233518 G17

THD

2ND

3RD

±10.24V RANGE

P-P

FULLY DIFFERENTIAL DRIVE

INPUT COMMON MODE (V)

–15

–10

–5

–160

–140

–120

–100

–80

–60

–40

–20

THD, HARMONICS (dBFS)

233518 G18

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

Typical perForMance characTerisTics

SNR, SINAD vs Temperature,

fIN=2kHz

THD, Harmonics vs Temperature,

fIN = 2kHz INL, DNL vs Temperature

Positive Full-Scale Error vs

Temperature and Channel

Negative Full-Scale Error vs

Temperature and Channel

Zero-Scale Error vs

Temperature and Channel

SNR, SINAD vs Input Level,

fIN=2kHz

CMRR vs Input Frequency

and Channel

Crosstalk vs Input Frequency

and Conversion Sequence

TA = 25°C, VCC=+15V, VEE=–15V, VDD=5V,

OVDD=2.5V, Internal Reference and Buffer (VREFBUF =4.096V), fSMPL = 1Msps, unless otherwise noted.

SNR

SINAD

±10.24V RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

INPUT LEVEL (dBFS)

–40

–30

–20

–10

96.0

96.5

97.0

97.5

98.0

SNR, SINAD (dBFS)

233518 G19

±10.24V RANGE

= IN

–

= 18V

P-P

SINE

ALL CHANNELS

FREQUENCY (Hz)

100

10k

100k

100

110

120

130

140

CMRR (dB)

233518 G20

±10.24V RANGE

IN0

= 0V

IN0

–

= 18V

P-P

SINE

IN1

, IN1

–

, IN2

–

= 0V

CH0, CH1, CH0, CH1...

CH0, CH2, CH0, CH2...

CH1, CH1, CH1, CH1...

FREQUENCY (Hz)

100

10k

100k

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

CROSSTALK (dB)

233518 G21

SNR

SINAD

±10.24V RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

TEMPERATURE (°C)

–55

–35

–15

105

125

SNR, SINAD (dBFS)

233518 G22

THD

2ND

3RD

±10.24V RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

TEMPERATURE (°C)

–55

–35

–15

105

125

–125

–120

–115

–110

–105

–100

–95

THD, HARMONICS (dBFS)

233518 G23

MAX INL

MIN INL

MAX DNL

MIN DNL

±10.24V RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

TEMPERATURE (°C)

–55

–35

–15

105

125

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

INL, DNL ERROR (LSB)

233518 G24

±10.24V RANGE

ALL CHANNELS

TEMPERATURE (°C)

–55

–35

–15

105

125

–0.100

–0.075

–0.050

–0.025

0.000

0.025

0.050

0.075

0.100

FULL-SCALE ERROR (%)

233518 G25

±10.24V RANGE

ALL CHANNELS

TEMPERATURE (°C)

–55

–35

–15

105

125

–0.100

–0.075

–0.050

–0.025

0.000

0.025

0.050

0.075

0.100

FULL-SCALE ERROR (%)

233518 G26

±10.24 V RANGE

ALL CHANNELS

TEMPERATURE (°C)

–55

–35

–15

105

125

–5

–4

–3

–2

–1

ZERO-SCALE ERROR (LSB)

233518 G27

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

Typical perForMance characTerisTics

Internal Reference Output

vs Temperature Supply Current vs Sampling Rate

Step Response

(Large-Signal Settling)

Step Response

(Fine Settling)

Supply Current vs Temperature

Power-Down Current

vs Temperature

Offset Error

vs Input Common Mode

PSRR vs Frequency

TA = 25°C, VCC=+15V, VEE=–15V, VDD=5V,

OVDD=2.5V, Internal Reference and Buffer (VREFBUF =4.096V), fSMPL = 1Msps, unless otherwise noted.

OVDD

VDD

VEE

VCC

TEMPERATURE (°C)

–55

–35

–15

105

125

–6

–4

–2

SUPPLY CURRENT (mA)

233518 G28

OVDD

VDD

–I

VEE

VCC

TEMPERATURE (°C)

–55

–35

–15

105

125

0.01

0.1

100

1000

POWER-DOWN CURRENT (µA)

233518 G29

= IN

–

= 0V

FREQUENCY (Hz)

100

10k

100k

100

110

120

130

140

150

PSRR (dB)

233518 G30

= 38V, V

= 0V

= 0V to 34V

±10.24V RANGE

= 21.5V, V

= –16.5V

= –16.5V to 17.5V

INPUT COMMON MODE (V)

–17

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

OFFSET ERROR (LSB)

233518 G31

15 UNITS

TEMPERATURE (°C)

–55

–35

–15

105

125

2.045

2.046

2.047

2.048

2.049

2.050

2.051

INTERNAL REFERENCE OUTPUT (V)

233518 G32

OVDD

VDD

VEE

VCC

WITH NAP MODE

CNVL

= 500ns

SAMPLING FREQUENCY (kHz)

200

400

600

800

1000

–6

–4

–2

SUPPLY CURRENT (mA)

233518 G33

±10.24V RANGE

= 249.99984kHz SQUARE WAVE

–

= 0V

SETTLING TIME (ns)

–100

100

200

300

400

500

600

700

800

900

–131072

–98304

–65536

–32768

32768

65536

98304

131072

OUTPUT CODE (LSB)

233518 G34

±10.24V RANGE

= 249.99984kHz

SQUARE WAVE

–

= 0V

SETTLING TIME (ns)

–100

100

200

300

400

500

600

700

800

900

–250

–200

–150

–100

–50

100

150

200

250

DEVIATION FROM FINAL VALUE (LSB)

233518 G35

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

pin FuncTions

Pins that are the Same for All Digital I/O Modes

IN0+ to IN7+, IN0− to IN7− (Pins 1, 2, 3, 4, 5, 6, 7, 8, 9,

10, 11, 12, 13, 14, 47, and 48): Positive and Negative

Analog Inputs, Channels 0 to 7. The converter samples

(VIN+ – VIN–) and digitizes the selected channel. Wide

input common mode range (VEE ≤ VCM ≤ VCC – 4V) and

high common mode rejection allow the inputs to accept

a wide variety of signal swings. Full-scale input range is

determined by the selected SoftSpan configuration.

GND (Pins 15, 18, 20, 25, 30, 36, 41, 44, 46): Ground.

Solder all GND pins to a solid ground plane.

VCC (Pin 16): Positive High Voltage Power Supply. The

range of VCC is 0V to 38V with respect to GND and 10V to

38V with respect to VEE. Bypass VCC to GND close to the

pin with a 0.1μF ceramic capacitor. In applications where

VCC is shorted to GND this capacitor may be omitted.

VEE (Pins 17, 45): Negative High Voltage Power Supply.

The range of VEE is 0V to –16.5V with respect to GND and

–10V to –38V with respect to VCC. Connect Pins 17 and 45

together and bypass the VEE network to GND close to Pin

17 with a 0.1μF ceramic capacitor. In applications where

VEE is shorted to GND this capacitor may be omitted.

REFIN (Pin 19): Bandgap Reference Output/Reference

Buffer Input. An internal bandgap reference nominally

outputs 2.048V on this pin. An internal reference buffer

amplifies VREFIN to create the converter master reference

voltage VREFBUF = 2•VREFIN on the REFBUF pin. When

using the internal reference, bypass REFIN to GND (Pin

20) close to the pin with a 0.1μF ceramic capacitor to filter

the bandgap output noise. If more accuracy is desired,

overdrive REFIN with an external reference in the range

of 1.25V to 2.2V.

REFBUF (Pin 21): Internal Reference Buffer Output. An

internal reference buffer amplifies VREFIN to create the

converter master reference voltage VREFBUF = 2•VREFIN on

this pin, nominally 4.096V when using the internal bandgap

reference. Bypass REFBUF to GND (Pin 20) close to the

pin with a 47μF ceramic capacitor. The internal reference

buffer may be disabled by grounding its input at REFIN.

With the buffer disabled, overdrive REFBUF with an ex-

ternal reference voltage in the range of 2.5V to 5V. When

using the internal reference buffer, limit the loading of any

external circuitry connected to REFBUF to less than 10µA.

Using a high input impedance amplifier to buffer VREFBUF

to any external circuits is recommended.

PD (Pin 22): Power Down Input. When this pin is brought

high, the LTC2335-18 is powered down and subsequent

conversion requests are ignored. If this occurs during a

conversion, the device powers down once the conversion

completes. If this pin is brought high twice without an

intervening conversion, an internal global reset is initi-

ated, equivalent to a power-on-reset event. Logic levels

are determined by OVDD.

LVDS/CMOS (Pin 23): I/O Mode Select. Tie this pin to OVDD

to select LVDS I/O mode, or to ground to select CMOS I/O

mode. Logic levels are determined by OVDD.

CNV (Pin 24): Conversion Start Input. A rising edge on

this pin puts the internal sample-and-holds into the hold

mode and initiates a new conversion. CNV is not gated

by CS, allowing conversions to be initiated independent

of the state of the serial I/O bus.

BUSY (Pin 38): Busy Output. The BUSY signal indicates

that a conversion is in progress. This pin transitions low-

to-high at the start of each conversion and stays high until

the conversion is complete. Logic levels are determined

by OVDD.

VDDLBYP (Pin 40): Internal 2.5V Regulator Bypass Pin. The

voltage on this pin is generated via an internal regulator

operating off of VDD. This pin must be bypassed to GND

close to the pin with a 2.2μF ceramic capacitor. Do not

connect this pin to any external circuitry.

VDD (Pins 42, 43): 5V Power Supply. The range of VDD

is 4.75V to 5.25V. Connect Pins 42 and 43 together and

bypass the VDD network to GND with a shared 0.1μF

ceramic capacitor close to the pins.

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

pin FuncTions

CMOS I/O Mode

SDI+, SDI–, SCKI+, SDO+, SDO– (Pins 26, 27, 28, 34,

and 35): LVDS Inputs and Outputs. In CMOS I/O mode

these pins are Hi-Z.

SCKI (Pin 29): CMOS Serial Clock Input. Drive SCKI with

the serial I/O clock. SCKI rising edges latch serial data in

on SDI and clock serial data out on SDO. For standard

SPI bus operation, capture output data at the receiver on

rising edges of SCKI. SCKI is allowed to idle either high

or low. Logic levels are determined by OVDD.

OVDD (Pin 31): I/O Interface Power Supply. In CMOS I/O

mode, the range of OVDD is 1.71V to 5.25V. Bypass OVDD

to GND (Pin 30) close to the pin with a 0.1μF ceramic

capacitor.

SCKO (Pin 32): CMOS Serial Clock Output. SCKI rising

edges trigger transitions on SCKO that are skew-matched to

the serial output data stream on SDO. The resulting SCKO

frequency is half that of SCKI. Rising and falling edges of

SCKO may be used to capture SDO data at the receiver

(FPGA) in double data rate (DDR) fashion. For standard

SPI bus operation, SCKO is not used and should be left

unconnected. SCKO is forced low at the falling edge of

BUSY. Logic levels are determined by OVDD.

SDO (Pin 33): CMOS Serial Data Output. The most recent

conversion result along with channel configuration informa-

tion is clocked out onto the SDO pin on each rising edge

of SCKI. Output data formatting is described in the Digital

Interface section. Logic levels are determined by OVDD.

SDI (Pin 37): CMOS Serial Data Input. Drive this pin with

the desired MUX control words (see Table1a), latched

on the rising edges of SCKI. Hold SDI low while clock-

ing SCKI to configure the next conversion according to

the previously programmed sequence. Logic levels are

determined by OVDD.

CS (Pin 39): Chip Select Input. The serial data I/O bus is

enabled when CS is low and is disabled and Hi-Z when

CS is high. CS also gates the external shift clock, SCKI.

Logic levels are determined by OVDD.

LVDS I/O Mode

SDI+, SDI– (Pins 26 and 27): LVDS Positive and Nega-

tive Serial Data Input. Differentially drive SDI+/SDI– with

the desired MUX control words (see Table 1a), latched

on both the rising and falling edges of SCKI+/SCKI–. The

SDI+/SDI– input pair is internally terminated with a 100Ω

differential resistor when CS is low.

SCKI+, SCKI– (Pins 28 and 29): LVDS Positive and Negative

Serial Clock Input. Differentially drive SCKI+/SCKI– with

the serial I/O clock. SCKI+/SCKI– rising and falling edges

latch serial data in on SDI+/SDI– and clock serial data out

on SDO+/SDO–. Idle SCKI+/SCKI– low, including when

transitioning CS. The SCKI+/SCKI– input pair is internally

terminated with a 100Ω differential resistor when CS is low.

OVDD (Pin 31): I/O Interface Power Supply. In LVDS I/O

mode, the range of OVDD is 2.375V to 5.25V. Bypass OVDD

to GND (Pin 30) close to the pin with a 0.1μF ceramic

capacitor.

SCKO+, SCKO– (Pins 32 and 33): LVDS Positive and

Negative Serial Clock Output. SCKO+/SCKO– outputs a

copy of the input serial I/O clock received on SCKI+/SCKI–,

skew-matched with the serial output data stream on SDO+/

SDO–. Use the rising and falling edges of SCKO+/SCKO–

to capture SDO+/SDO– data at the receiver (FPGA). The

SCKO+/SCKO– output pair must be differentially terminated

with a 100Ω resistor at the receiver (FPGA).

SDO+, SDO– (Pins 34 and 35): LVDS Positive and Nega-

tive Serial Data Output. The most recent conversion result

along with channel configuration information is clocked out

onto SDO+/SDO– on both rising and falling edges of SCKI+/

SCKI–. The SDO+/SDO– output pair must be differentially

terminated with a 100Ω resistor at the receiver (FPGA).

SDI (Pin 37): CMOS Serial Data Input. In LVDS I/O mode

this pin is Hi-Z.

CS (Pin 39): Chip Select Input. The serial data I/O bus is

enabled when CS is low, and is disabled and Hi-Z when

CS is high. CS also gates the external shift clock, SCKI+/

SCKI–. The internal 100Ω differential termination resistors

on the SCKI+/SCKI– and SDI+/SDI– input pairs are disabled

when CS is high. Logic levels are determined by OVDD.

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

conFiguraTion Tables

Table 1a. SoftSpan Configuration Table. Use This Table with Table 1b to Choose Binary SoftSpan Codes SS[2:0] Based on Desired

Analog Input Range. Combine MUX Word Header (10) with Binary Channel Number and SoftSpan Code to Form MUX Control Word

C[7:0]. Use Serial Interface to Program LTC2335-18 Sequencer as Shown in Figures 17 to 20

BINARY SoftSpan CODE

SS[2:0] ANALOG INPUT RANGE FULL SCALE RANGE BINARY FORMAT OF

CONVERSION RESULT

111 ±2.5 • VREFBUF 5 • VREFBUF Tw o ’s Complement

110 ±2.5 • VREFBUF/1.024 5 • VREFBUF/1.024 Tw o ’s Complement

101 0V to 2.5 • VREFBUF 2.5 • VREFBUF Straight Binary

100 0V to 2.5 • VREFBUF/1.024 2.5 • VREFBUF/1.024 Straight Binary

011 ±1.25 • VREFBUF 2.5 • VREFBUF Tw o ’s Complement

010 ±1.25 • VREFBUF/1.024 2.5 • VREFBUF/1.024 Tw o ’s Complement

001 0V to 1.25 • VREFBUF 1.25 • VREFBUF Straight Binary

000 0V to 1.25 • VREFBUF/1.024 1.25 • VREFBUF/1.024 Straight Binary

Table 1b. Reference Configuration Table. The LTC2335-18 Supports Three Reference Configurations. Analog Input Range Scales with

the Converter Master Reference Voltage, VREFBUF

REFERENCE CONFIGURATION VREFIN VREFBUF BINARY SoftSpan CODE

SS[2:0] ANALOG INPUT RANGE

Internal Reference with

Internal Buffer 2.048V 4.096V

111 ±10.24V

110 ±10V

101 0V to 10.24V

100 0V to 10V

011 ±5.12V

010 ±5V

001 0V to 5.12V

000 0V to 5V

External Reference with

Internal Buffer

(REFIN Pin Externally

Overdriven)

1.25V

(Min Value) 2.5V

111 ±6.25V

110 ±6.104V

101 0V to 6.25V

100 0V to 6.104V

011 ±3.125V

010 ±3.052V

001 0V to 3.125V

000 0V to 3.052V

2.2V

(Max Value) 4.4V

111 ±11V

110 ±10.742V

101 0V to 11V

100 0V to 10.742V

011 ±5.5V

010 ±5.371V

001 0V to 5.5V

000 0V to 5.371V

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

REFERENCE CONFIGURATION VREFIN VREFBUF BINARY SoftSpan CODE

SS[2:0] ANALOG INPUT RANGE

External Reference

Unbuffered

(REFBUF Pin

Externally Overdriven,

REFIN Pin Grounded)

0V 2.5V

(Min Value)

111 ±6.25V

110 ±6.104V

101 0V to 6.25V

100 0V to 6.104V

011 ±3.125V

010 ±3.052V

001 0V to 3.125V

000 0V to 3.052V

0V 5V

(Max Value)

111 ±12.5V

110 ±12.207V

101 0V to 12.5V

100 0V to 12.207V

011 ±6.25V

010 ±6.104V

001 0V to 6.25V

000 0V to 6.104V

conFiguraTion Tables

Table 1b. Reference Configuration Table (Continued). The LTC2335-18 Supports Three Reference Configurations. Analog Input Range

Scales with the Converter Master Reference Voltage, VREFBUF

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

FuncTional block DiagraM

LVDS I/O Mode

CMOS I/O Mode

IN0+

IN0–

BUSY

18-BIT

SAMPLING

ADC

CMOS

SERIAL

I/O

INTERFACE

233518 BD01

18 BITS

REFERENCE

BUFFER

REFBUFREFINGND

VCC

VEE

VDDLBYP

VDD OVDD

LTC2335-18

CONTROL

LOGIC

2.048V

REFERENCE

SEQUENCER

LVDS/CMOSPDCNV

IN1+

IN1–

IN2+

IN2–

IN3+

IN3–

IN4+

IN4–

IN5+

IN5–

IN6+

IN6–

IN7+

IN7–

8-CHANNEL MULTIPLEXER

20k

2×

SDO

SCKO

SDI

SCKI

2.5V

REGULATOR

SDO+

SDO–

SCKO+

SCKO–

SDI+

SDI–

SCKI+

SCKI–

IN0+

IN0–

BUSY

18-BIT

SAMPLING

ADC

LVDS

SERIAL

I/O

INTERFACE

233518 BD02

18 BITS

REFERENCE

BUFFER

REFBUFREFINGND

VCC

VEE

VDDLBYP

VDD OVDD

LTC2335-18

CONTROL

LOGIC

2.048V

REFERENCE

2.5V

REGULATOR

LVDS/CMOSPDCNV

IN1+

IN1–

IN2+

IN2–

IN3+

IN3–

IN4+

IN4–

IN5+

IN5–

IN6+

IN6–

IN7+

IN7–

8-CHANNEL MULTIPLEXER

20k

2×

SEQUENCER

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

TiMing DiagraM

CMOS I/O Mode

LVDS I/O Mode

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

C6 C5 C4 C3 C2 C1 C0 C7 C6 C5 C4 C3 C2 C1 C0

D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SS1SS2 SS0 D17

CNV

CS = PD = 0

CONVERT

DON’T CARE

ACQUIREBUSY

SCKO

SDO

SCKI

SDI

DON’T CARE

SAMPLE N SAMPLE N + 1

CONTROL WORD FOR

CONVERSION N + 1

CONTROL WORD FOR

CONVERSION N + 2

CONVERSION N 233518 TD01

CONVERSION RESULT CHANNEL ID SoftSpan CONVERSION RESULT

(REPETITION)

CH2 CH1 CH0

C7 C6 C5 C4 C3 C2 C1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SS1SS2 SS0 D17

CNV

(CMOS)

CS = PD = 0

CONVERT

DON’T CARE

ACQUIRE

BUSY

(CMOS)

SCKO

(LVDS)

SDO

(LVDS)

SCKI

(LVDS)

SDI

(LVDS)

DON’T CARE

SAMPLE N SAMPLE N + 1

CONTROL WORD FOR

CONVERSION N + 1

CONTROL WORD FOR

CONVERSION N + 2

CONVERSION N

233518 TD02

CONVERSION RESULT CHANNEL ID SoftSpan CONVERSION RESULT

(REPETITION)

CH2 CH1 CH0

C0 C7 C6 C5 C4 C3 C2 C1 C0

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

applicaTions inForMaTion

OVERVIEW

The LTC2335-18 is an 18-bit, low noise 8-channel multi-

plexed successive approximation register (SAR) ADC with

differential, wide common mode range inputs. The ADC

operates from a 5V low voltage supply and flexible high

voltage supplies, nominally ±15V. Using the integrated

low-drift reference and buffer (VREFBUF

=4.096V nominal),

this SoftSpan ADC can be configured on a conversion-by-

conversion basis to accept ±10.24V, 0V to 10.24V, ±5.12V,

or 0V to 5.12V signals on any channel. Alternately, the

ADC may be programmed to cycle through a sequence of

channels and ranges without further user intervention. The

input signal range may be expanded up to ±12.5V using

an external 5V reference.

The wide input common mode range and high CMRR

(118dB typical, VIN+ = VIN– = 18VP-P 200Hz Sine) of the

LTC2335-18 analog inputs allow the ADC to directly digitize

a variety of signals, simplifying signal chain design. The

absolute common mode input range is determined by

the choice of high voltage supplies, which may be biased

asymmetrically around ground and include the ability for

either the positive or negative supply to be tied directly to

ground. This input signal flexibility, combined with ±3LSB

INL, no missing codes at 18-bits, and 96.7dB SNR, makes

the LTC2335-18 an ideal choice for many high voltage

applications requiring wide dynamic range.

The LTC2335-18 supports pin-selectable SPI CMOS (1.8V

to 5V) and LVDS serial interfaces, enabling it to communi-

cate equally well with legacy microcontrollers and modern

FPGAs. The LTC2335-18 typically dissipates 180mW when

converting at 1Msps throughput. Optional nap and power

down modes may be employed to further reduce power

consumption during inactive periods.

CONVERTER OPERATION

The LTC2335-18 operates in two phases. During the ac-

quisition phase, the sampling capacitors in each channel

connect to their respective analog input pins and track

the differential analog input voltage (VIN+ – VIN–). A ris-

ing edge on the CNV pin transitions the S/H circuits from

track mode to hold mode, sampling the input signals and

initiating a conversion. During the conversion phase, the

selected channel's sampling capacitors are connected to

an 18-bit charge redistribution capacitor D/A converter

(CDAC). The CDAC is sequenced through a successive ap-

proximation algorithm, effectively comparing the sampled

input voltage with binary-weighted fractions of the chan-

nel’s SoftSpan full-scale range (e.g., VFSR/2, VFSR/4 …

VFSR/262144) using a differential comparator. At the end

of this process, the CDAC output approximates the chan-

nel’s sampled analog input. The ADC control logic then

prepares the 18-bit digital output code for serial transfer.

TRANSFER FUNCTION

The LTC2335-18 digitizes the full-scale voltage range into

218 levels. In conjunction with the ADC master reference

voltage, VREFBUF, the selected SoftSpan configuration

determines its input voltage range, full-scale range, LSB

size, and the binary format of its conversion result, as

shown in Tables 1a and 1b. For example, employing the

internal reference and buffer (VREFBUF = 4.096V nominal),

SoftSpan 7 configures a channel to accept a ±10.24V

bipolar analog input voltage range, which corresponds

to a 20.48V full-scale range with a 78.125μV LSB. Other

SoftSpan configurations and reference voltages may be

employed to convert both larger and smaller bipolar and

unipolar input ranges. Conversion results are output in

two’s complement binary format for all bipolar SoftSpan

ranges, and in straight binary format for all unipolar

SoftSpan ranges. The ideal two’s complement transfer

function is shown in Figure 2, while the ideal straight

binary transfer function is shown in Figure 3.

Figure 2. LTC2335-18 Tw o ’s Complement Transfer Function

INPUT VOLTAGE (V)

OUTPUT CODE (TWO’S COMPLEMENT)

–1

LSB

233518 F02

011...111

011...110

000...001

000...000

100...000

100...001

111...110

LSB

BIPOLAR

ZERO

111...111

FSR/2 – 1LSB–FSR/2

FSR = +FS – –FS

1LSB = FSR/262144

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

ANALOG INPUTS

The LTC2335-18 samples the voltage difference (VIN+ –

VIN–) between its analog input pins over a wide common

mode input range while attenuating unwanted signals

common to both input pins by the common-mode rejec-

tion ratio (CMRR) of the ADC. Wide common mode input

range coupled with high CMRR allows the IN+/IN– analog

inputs to swing with an arbitrary relationship to each

other, provided each pin remains between (VCC – 4V)

and VEE. This unique feature of the LTC2335-18 enables

it to accept a wide variety of signal swings, including

traditional classes of analog input signals such as pseudo-

differential unipolar, pseudo-differential true bipolar, and

fully differential, simplifying signal chain design.

The wide operating range of the high voltage supplies

offers further input common mode flexibility. As long as

the voltage difference limits of 10V ≤ VCC – VEE ≤ 38V

are observed, VCC and VEE may be independently biased

anywhere within their own individual allowed operating

ranges, including the ability for either of the supplies to be

tied directly to ground. This feature enables the common

mode input range of the LTC2335-18 to be tailored to the

specific application’s requirements.

In all SoftSpan ranges, each channel’s analog inputs can

be modeled by the equivalent circuit shown in Figure 4.

At the start of acquisition, the 40pF sampling capacitors

(CIN) connect to the analog input pins IN+/IN– through

applicaTions inForMaTion

the sampling switches, each of which has approximately

600Ω (RIN) of on-resistance. This behavior occurs on all

channels, so that the LTC2335-18 may respond instantly

to user-requested changes in multiplexer configuration

with no additional settling time required.

Figure 4. Equivalent Circuit for Differential Analog Inputs,

Single Channel Shown

RIN

600Ω

RIN

600Ω

CIN

40pF

CIN

40pF

VCC

VEE

BIAS

VOLTAGE

–233518 F04

Figure 3. LTC2335-18 Straight Binary Transfer Function

INPUT VOLTAGE (V)

OUTPUT CODE (STRAIGHT BINARY)

233518 F03

111...111

111...110

100...001

100...000

000...000

000...001

011...110

UNIPOLAR

ZERO

011...111

FSR – 1LSB0V

FSR = +FS

1LSB = FSR/262144

The initial voltage on both capacitors of the just-converted

channel will be approximately the sampled common mode

voltage (VIN+ + VIN–)/2 from the previous conversion.

Other channels’ capacitors will retain approximately the

voltage of their respective IN+/IN– pin at the beginning of

the previous conversion. The external circuitry connected

to IN+ and IN– must source or sink the charge that flows

through RIN as the sampling capacitors settle from their

initial voltages to the new input pin voltages over the

course of the acquisition interval. During conversion, nap,

and power down modes, the analog inputs draw only a

small leakage current. The diodes at the inputs provide

ESD protection.

Bipolar SoftSpan Input Ranges

For conversions configured in SoftSpan ranges 7, 6, 3,

or 2, the LTC2335-18 digitizes the differential analog

input voltage (VIN+ – VIN–) over a bipolar span of

±2.5•VREFBUF, ±2.5•VREFBUF/1.024, ±1.25•VREFBUF, or

±1.25•VREFBUF/1.024, respectively, as shown in Table

1a. These SoftSpan ranges are useful for digitizing input

signals where IN+ and IN– swing above and below each

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

applicaTions inForMaTion

24ns implies an 18-bit settling time to a full-scale step of

approximately 13•(RIN• CIN)=312ns. The impedance and

self-settling of external circuitry connected to the analog

input pins will increase the overall settling time required.

Low impedance sources can directly drive the inputs of

the LTC2335-18 without gain error, but high impedance

sources should be buffered to ensure sufficient settling

during acquisition and to optimize the linearity and distor-

tion performance of the ADC. Settling time is an important

consideration even for DC input signals, as the voltages on

the sampling capacitors will differ from the analog input

pin voltages at the start of acquisition.

Most applications should use a buffer amplifier to drive the

analog inputs of the LTC2335-18. The amplifier provides

low output impedance, enabling fast settling of the analog

signal during the acquisition phase. It also provides isola-

tion between the signal source and the charge flow at the

analog inputs when entering acquisition.

Input Filtering

The noise and distortion of an input buffer amplifier and

other supporting circuitry must be considered since they

add to the ADC noise and distortion. Noisy input signals

should be filtered prior to the buffer amplifier with a low-

bandwidth filter to minimize noise. The simple one-pole

RC lowpass filter shown in Figure 5 is sufficient for many

applications.

At the output of the buffer, a lowpass RC filter network

formed by the 600Ω sampling switch on-resistance (RIN)

and the 40pF sampling capacitance (CIN) limits the input

bandwidth on each channel to 7MHz, which is fast enough

to allow for sufficient transient settling during acquisition

while simultaneously filtering driver wideband noise.

A buffer amplifier with low noise density should be se-

lected to minimize SNR degradation over this bandwidth.

An additional filter network may be placed between the

buffer output and ADC input to further minimize the noise

other. Traditional examples include fully differential input

signals, where IN+ and IN– are driven 180 degrees out-of-

phase with respect to each other centered around a common

mode voltage (VIN++VIN–)/2, and pseudo-differential true

bipolar input signals, where IN+ swings above and below

a ground reference level, driven on IN–. Regardless of the

chosen SoftSpan range, the wide common mode input

range and high CMRR of the IN+/IN– analog inputs allow

them to swing with an arbitrary relationship to each other,

provided each pin remains between (VCC – 4V) and VEE.

The output data format for all bipolar SoftSpan ranges is

two’s complement.

Unipolar SoftSpan Input Ranges

For conversions configured in SoftSpan ranges 5, 4, 1,

or 0, the LTC2335-18 digitizes the differential analog

input voltage (VIN+ – VIN–) over a unipolar span of 0V

to 2.5•VREFBUF, 0V to 2.5•VREFBUF/1.024, 0V to 1.25 •

VREFBUF, or 0V to 1.25•VREFBUF/1.024, respectively, as

shown in Table 1a. These SoftSpan ranges are useful for

digitizing input signals where IN+ remains above IN–. A

traditional example includes pseudo-differential unipolar

input signals, where IN+ swings above a ground reference

level, driven on IN–. Regardless of the chosen SoftSpan

range, the wide common mode input range and high

CMRR of the IN+/IN– analog inputs allow them to swing

with an arbitrary relationship to each other, provided each

pin remains between (VCC – 4V) and VEE. The output data

format for all unipolar SoftSpan ranges is straight binary.

INPUT DRIVE CIRCUITS

The initial voltage on each channel’s sampling capacitors

at the start of acquisition must settle to the new input

pin voltages during the acquisition interval. The external

circuitry connected to IN+ and IN– must source or sink

the charge that flows through RIN as this settling occurs.

The LTC2335-18 sampling network RC time constant of

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

contribution of the buffer. A simple one-pole lowpass RC

filter is sufficient for many applications.

This filter interacts with the buffer amplifier and slows

input settling. It is important that the inputs settle to

18-bit resolution within the ADC acquisition time (tACQ),

as insufficient settling can limit INL and THD performance.

High quality capacitors and resistors should be used in

the RC filters since these components can add distortion.

NPO/COG and silver mica type dielectric capacitors have

excellent linearity. Carbon surface mount resistors can

generate distortion from self-heating and from damage

that may occur during soldering. Metal film surface mount

resistors are much less susceptible to both problems.

Buffering Arbitrary and Fully Differential Analog Input

Signals

The wide common mode input range and high CMRR of

the LTC2335-18 allow each channel’s IN+ and IN– pins

to swing with an arbitrary relationship to each other,

provided each pin remains between (VCC – 4V) and VEE.

This unique feature of the LTC2335-18 enables it to accept

applicaTions inForMaTion

a wide variety of signal swings, simplifying signal chain

design. In many applications, connecting a channel’s IN+

and IN– pins directly to the existing signal chain circuitry

will not allow the channel’s sampling network to settle to

18-bit resolution within the ADC acquisition time (tACQ). In

these cases, it is recommended that two unity-gain buffers

be inserted between the signal source and the ADC input

pins, as shown in Figure 6a. Table 2 lists several amplifier

and lowpass filter combinations recommended for use in

this circuit.

The LT1358 combines fast settling, high linearity, and low

input-referred noise density, allowing it to approach the full

ADC data sheet SNR and THD specifications when used

with a lowpass filter, as shown in the FFT plots in Figures6b

to 6e. It may be used without a filter at a loss of 0.3dB

SNR due to wideband noise. The LT1469 achieves the full

ADC specifications for DC precision, THD, and linearity,

at a cost of 0.8dB in SNR. Finally, the LT1355 provides a

good general-purpose combination of THD and SNR at a

lower power. Neither the LT1469 nor LT1355 can afford

the slowing effect of a lowpass filter if they are to be used

at the minimum tACQ of 420ns.

Table 2. Recommended Amplifier and Filter Combinations for the Buffer Circuits in Figures 6a and 9. AC Performance Measured

Using Circuit in Figure 6a, ±10.24V Range

AMPLIFIER RFILT

(Ω)

CFILT

(pF) INPUT SIGNAL DRIVE SNR

(dB)

THD

(dB)

SINAD

(dB)

SFDR

(dB)

½ LT1358 100 270 FULLY DIFFERENTIAL 96.8 −120 96.8 120

½ LT1469 0 0 FULLY DIFFERENTIAL 96.0 −124 96.0 120

½ LT1358 100 270 TRUE BIPOLAR 96.8 −107 96.4 108

½ LT1358 0 0 TRUE BIPOLAR 96.5 −108 96.2 110

½ LT1469 0 0 TRUE BIPOLAR 96.0 −109 95.8 110

½ LT1355 0 0 TRUE BIPOLAR 96.2 −106 95.9 109

Figure 5. True Bipolar Signal Chain with Input Filtering

–

LTC2335-18

233518 F05

ONLY CHANNEL 0 SHOWN FOR CLARITY

TRUE BIPOLAR

INPUT SIGNAL

IN0+

IN0–

BUFFER

AMPLIFIER

LOWPASS

SIGNAL FILTER

10nF

160Ω

BW = 100kHz

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

applicaTions inForMaTion

Figure 6a. Buffering Arbitrary, Fully Differential, True Bipolar, and Unipolar Signals.

See Table 2 for Recommended Amplifier and Filter Combinations

Figure 6b. Tw o -Tone Test. IN+ = –7dBFS 2kHz Sine, IN– = –7dBFS

3.1kHz Sine, 32k Point FFT, fSMPL = 1Msps. Circuit Shown in

Figure 6a with LT1358 Amplifiers, RFILT = 100Ω, CFILT = 270pF

Figure 6d. IN+ = –1dBFS 2kHz True Bipolar Sine, IN– = 0V, 32k

Point FFT, fSMPL = 1Msps. Circuit Shown in Figure 6a with LT1358

Amplifiers, RFILT = 100Ω, CFILT = 270pF

Figure 6c. IN+/IN– = –1dBFS 2kHz Fully Differential Sine, VCM = 0V,

32k Point FFT, fSMPL = 1Msps. Circuit Shown in Figure 6a with

LT1358 Amplifiers, RFILT = 100Ω, CFILT = 270pF

Arbitrary Drive

True Bipolar Drive

Fully Differential Drive

Unipolar Drive

Figure 6e. IN+ = –1dBFS 2kHz Unipolar Sine, IN– = 0V, 32k Point

FFT, fSMPL = 1Msps. Circuit Shown in Figure 6a with LT1358

Amplifiers, RFILT = 100Ω, CFILT = 270pF

–15V

15V

LTC2335-18

233518 F06a

ONLY CHANNEL 0 SHOWN FOR CLARITY

+10V

–10V

TRUE BIPOLAR

+10V

–10V

ARBITRARY

+10V

–10V

UNIPOLAR

–

0.1µF

47µF

IN0+

IN0–

AMPLIFIER

VCC

REFINREFBUFVEE

OPTIONAL

LOWPASS FILTERS

CFILT

RFILT

IN+

IN–

+5V

–5V

FULLY

DIFFERENTIAL

±10.24V RANGE

SFDR = 118dB

SNR = 97.0dB

FREQUENCY (kHz)

100

200

300

400

500

–180

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

233518 F06b

±10.24V RANGE

SNR = 96.8dB

THD = –120dB

SINAD = 96.8dB

SFDR = 120dB

FREQUENCY (kHz)

100

200

300

400

500

–180

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

233518 F06c

±10.24V RANGE

SNR = 96.8dB

THD = –107dB

SINAD = 96.4dB

SFDR = 108dB

FREQUENCY (kHz)

100

200

300

400

500

–180

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

233518 F06d

0V to 10.24V RANGE

SNR = 91.0dB

THD = –111dB

SINAD = 91.0dB

SFDR = 111dB

FREQUENCY (kHz)

100

200

300

400

500

–180

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

233518 F06e

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

The two-tone test shown in Figure 6b demonstrates the

arbitrary input drive capability of the LTC2335-18. This test

simultaneously drives IN+ with a −7dBFS 2kHz single-ended

sine wave and IN− with a −7dBFS 3.1kHz single-ended sine

wave. Together, these signals sweep the analog inputs

across a wide range of common mode and differential

mode voltage combinations, similar to the more general

arbitrary input signal case. They also have a simple spec-

tral representation. An ideal differential converter with no

common-mode sensitivity will digitize this signal as two

−7dBFS spectral tones, one at each sine wave frequency.

The FFT plot in Figure 6b demonstrates the LTC2335-18

response, which approaches this ideal with 118dB of

SFDR limited by the converter's second harmonic distor-

tion response to the 3.1kHz sine wave on IN–.

The ability of the LTC2335-18 to accept arbitrary signal

swings over a wide input common mode range with high

CMRR can simplify application solutions. In practice,

many sensors produce a differential sensor voltage riding

on top of a large common mode signal. Figure 7a depicts

one way of using the LTC2335-18 to digitize signals of

this type. The amplifier stage provides a differential gain

of approximately 10V/V to the desired sensor signal while

the unwanted common mode signal is attenuated by the

ADC CMRR. The circuit employs the ±5V SoftSpan range of

the ADC. Figure7b shows measured CMRR performance

of this solution, which is competitive with the best com-

mercially available instrumentation amplifiers. Figure7c

shows measured AC performance of this solution.

In Figure 8, another application circuit is shown which

uses two channels of the LTC2335-18 to sense the volt-

age on and bidirectional current through a sense resistor

over a wide common mode range. In many applications

of this type, the impedance of the external circuitry is low

enough that the ADC sampling network can fully settle

without buffering.

Figure 7a. Digitize Differential Signals Over a Wide Common Mode Range

applicaTions inForMaTion

–5V

31V

LTC2335-18

233518 F07a

ONLY CHANNEL 0 SHOWN FOR CLARITY

24V

ARBITRARY +

–

0.1µF

47µF

IN0+

IN0–

½ LT1124

VCC

REFINREFBUFVEE

LOWPASS FILTERS

BW ~ 500kHz

6.6nF

49.9Ω

549Ω

18pF

IN+

IN–

2.49k

COMMON MODE

INPUT RANGE

DIFFERENTIAL MODE

INPUT RANGE: ±500mV

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

Buffering Single-Ended Analog Input Signals

While the circuit shown in Figure 6a is capable of buffering

single-ended input signals, the circuit shown in Figure 9 is

preferable when the single-ended signal reference level is

inherently low impedance and doesn't require buffering.

This circuit eliminates one driver and lowpass filter, reduc-

ing part count, power dissipation, and SNR degradation

due to driver noise. Using the recommended driver and

filter combinations in Table 2, the performance of this

circuit with single-ended input signals is on par with the

performance of the circuit in Figure 6a.

applicaTions inForMaTion

Figure 8. Sense Voltage (CH0) and Current (CH1)

Over a Wide Common Mode Range

Figure 7c. IN+/IN–=450mV 2kHz Fully Differential Sine,

0V≤VCM≤24V, 32k Point FFT, fSMPL = 200ksps. Circuit

Shown in Figure 7a

Figure 7b. CMRR vs Input Frequency. Circuit Shown in Figure 7a

Figure 9. Buffering Single-Ended Input Signals. See Table 2 For Recommended Amplifier and Filter Combinations

–15V

15V

LTC2335-18

233518

F08

ONLY CHANNELS 0 AND 1 SHOWN FOR CLARITY

0.1µF

47µF

–10.24V ≤ VS1 ≤ 10.24V

–10.24V ≤ VS2 ≤ 10.24V

VS1 – VS2

RSENSE

ISENSE =

IN0+

IN0–

IN1+

IN1–

VCC

REFINREFBUFVEE

ISENSE

SENSE

VS2

VS1

–15V

15V

LTC2335-18

233518 F09

ONLY CHANNEL 0 SHOWN FOR CLARITY

TRUE BIPOLAR

+10V

–10V

+10V

–10V

UNIPOLAR

–

0.1µF

47µF

IN0+

IN0–

AMPLIFIER

VCC

REFINREFBUFVEE

OPTIONAL

LOWPASS FILTER

CFILT

RFILT

IN+

IN–

±5V RANGE

= IN

–

= 1V

P-P

SINE

= IN

–

= 24V

P-P

SINE

OP AMPS SLEW f

> 30kHz

FREQUENCY (Hz)

100

10k

100k

100

110

120

CMRR (dB)

233518 F07b

±5V RANGE

FULLY DIFFERENTIAL DRIVE (IN– = +IN+)

SNR = 90.0dB

THD = –113dB

SINAD = 90.0dB

SFDR = 117dB

FREQUENCY (kHz)

100

–180

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

233518 F07c

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

ADC REFERENCE

As shown previously in Table 1b, the LTC2335-18 supports

three reference configurations. The first uses both the in-

ternal bandgap reference and reference buffer. The second

externally overdrives the internal reference but retains the

internal buffer, which isolates the external reference from

ADC conversion transients. This configuration is ideal

for sharing a single precision external reference across

multiple ADCs. The third disables the internal buffer and

overdrives the REFBUF pin externally.

Internal Reference with Internal Buffer

The LTC2335-18 has an on-chip, low noise, low drift

(20ppm/°C maximum), temperature compensated band-

gap reference that is factory trimmed to 2.048V. The

reference output connects through a 20kΩ resistor to

the REFIN pin, which serves as the input to the on-chip

reference buffer, as shown in Figure 10a. When employing

the internal bandgap reference, the REFIN pin should be

bypassed to GND (Pin 20) close to the pin with a 0.1μF

ceramic capacitor to filter wideband noise. The reference

buffer amplifies VREFIN to create the converter master

reference voltage VREFBUF = 2•VREFIN on the REFBUF pin,

nominally 4.096V when using the internal bandgap refer-

ence. Bypass REFBUF to GND (Pin 20) close to the pin with

at least a 47μF ceramic capacitor (X7R, 10V, 1210 size or

X5R, 10V, 0805 size) to compensate the reference buffer,

absorb transient conversion currents, and minimize noise.

External Reference with Internal Buffer

If more accuracy and/or lower drift is desired, REFIN can

be easily overdriven by an external reference since 20kΩ

of resistance separates the internal bandgap reference

output from the REFIN pin, as shown in Figure 10b. The

valid range of external reference voltage overdrive on the

REFIN pin is 1.25V to 2.2V, resulting in converter mas-

ter reference voltages VREFBUF between 2.5V and 4.4V,

respectively. Linear Technology offers a portfolio of high

performance references designed to meet the needs of

many applications. With its small size, low power, and high

accuracy, the LTC6655-2.048 is well suited for use with the

LTC2335-18 when overdriving the internal reference. The

LTC6655-2.048 offers 0.025% (maximum) initial accuracy

applicaTions inForMaTion

Figure 10b. External Reference with Internal Buffer Configuration

Figure 10a. Internal Reference with Internal Buffer Configuration

233518 F10a

47µF

6.5k

20k

LTC2335-18

REFERENCE

BUFFER

REFBUF

REFIN

GND

BANDGAP

REFERENCE

6.5k

0.1µF

233518 F10b

47µF

6.5k

20k

LTC2335-18

REFERENCE

BUFFER

REFBUF

REFIN

GND

BANDGAP

REFERENCE

6.5k

2.7µF

LTC6655-2.048

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

and 2ppm/°C (maximum) temperature coefficient for high

precision applications. The LTC6655-2.048 is fully speci-

fied over the H-grade temperature range, complementing

the extended temperature range of the LTC2335-18 up to

125°C. Bypassing the LTC6655-2.048 with a 2.7µF to 100µF

ceramic capacitor close to the REFIN pin is recommended.

External Reference with Disabled Internal Buffer

The internal reference buffer supports VREFBUF = 4.4V

maximum. Grounding REFIN disables the internal buffer,

allowing REFBUF to be overdriven with an external refer-

ence voltage between 2.5V and 5V, as shown in Figure

10c. Maximum input signal swing and SNR are achieved

by overdriving REFBUF using an external 5V reference. The

buffer feedback resistors load the REFBUF pin with 13kΩ

even when the reference buffer is disabled. The LTC6655-5

offers the same small size, accuracy, drift, and extended

temperature range as the LTC6655-2.048, and achieves

a typical SNR of 98.3dB when paired with the LTC2335-

18. Bypass the LTC6655-5 to GND (Pin 20) close to the

REFBUF pin with at least a 47μF ceramic capacitor (X7R,

10V, 1210 size or X5R, 10V, 0805 size) to absorb transient

conversion currents and minimize noise.

The LTC2335-18 converter draws a charge (QCONV) from

the REFBUF pin during each conversion cycle. On short

time scales most of this charge is supplied by the external

REFBUF bypass capacitor, but on longer time scales all of

the charge is supplied by either the reference buffer, or

when the internal reference buffer is disabled, the external

reference. This charge draw corresponds to a DC current

equivalent of IREFBUF = QCONV• fSMPL, which is proportional

to sample rate. In applications where a burst of samples

is taken after idling for long periods of time, as shown in

Figure 11, IREFBUF quickly transitions from approximately

0.4mA to 1.1mA (VREFBUF = 5V, fSMPL = 1Msps). This

current step triggers a transient response in the external

reference that must be considered, since any deviation in

VREFBUF affects converter accuracy. If an external reference

is used to overdrive REFBUF, the fast settling LTC6655

family of references is recommended.

Internal Reference Buffer Transient Response

For optimum performance in applications employing burst

sampling, the external reference with internal reference

buffer configuration should be used. The internal reference

buffer incorporates a proprietary design that minimizes

movements in VREFBUF when responding to a burst of

applicaTions inForMaTion

Figure 11. CNV Waveform Showing Burst Sampling

Figure 10c. External Reference with Disabled Internal

Buffer Configuration

CNV

IDLE

PERIOD

IDLE

PERIOD

233518

F11

233518

F10c

47µF

6.5k

20k

LTC2335-18

REFERENCE

BUFFER

REFBUF

REFIN

GND

BANDGAP

REFERENCE

6.5k

LTC6655-5

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

conversions following an idle period. Figure 12 compares

the burst conversion response of the LTC2335-18 with an

input near full scale for two reference configurations. The

first configuration employs the internal reference buffer

with REFIN externally overdriven by an LTC6655-2.048,

while the second configuration disables the internal ref-

erence buffer and overdrives REFBUF with an external

LTC6655-4.096. In both cases REFBUF is bypassed to

GND with a 47µF ceramic capacitor.

Signal-to-Noise Ratio (SNR)

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the first five harmonics and DC. Figure 13 shows

that the LTC2335-18 achieves a typical SNR of 96.9dB in

the ±10.24V range at a 1Msps sampling rate with a true

bipolar 2kHz input signal.

Total Harmonic Distortion (THD)

Total harmonic distortion (THD) is the ratio of the RMS sum

of all harmonics of the input signal to the fundamental itself.

The out-of-band harmonics alias into the frequency band

between DC and half the sampling frequency (fSMPL/2).

THD is expressed as:

THD =20log V2

2+V3

2+V4

2...V

where V1 is the RMS amplitude of the fundamental fre-

quency and V2 through VN are the amplitudes of the second

through Nth harmonics, respectively. Figure 13 shows that

the LTC2335-18 achieves a typical THD of –109dB (N=6)

in the ±10.24V range at a 1Msps sampling rate with a true

bipolar 2kHz input signal.

applicaTions inForMaTion

Figure 13. 32k Point FFT fSMPL = 1Msps, fIN = 2kHz

Figure 12. Burst Conversion Response of the

LTC2335-18, fSMPL= 1Msps

DYNAMIC PERFORMANCE

Fast Fourier transform (FFT) techniques are used to test

the ADC’s frequency response, distortion, and noise at the

rated throughput. By applying a low distortion sine wave

and analyzing the digital output using an FFT algorithm,

the ADC’s spectral content can be examined for frequen-

cies outside the fundamental. The LTC2335-18 provides

guaranteed tested limits for both AC distortion and noise

measurements.

Signal-to-Noise and Distortion Ratio (SINAD)

The signal-to-noise and distortion ratio (SINAD) is the

ratio between the RMS amplitude of the fundamental input

frequency and the RMS amplitude of all other frequency

components at the A/D output. The output is band-limited

to frequencies below half the sampling frequency, exclud-

ing DC. Figure 13 shows that the LTC2335-18 achieves a

typical SINAD of 96.7dB in the ±10.24V range at a 1Msps

sampling rate with a true bipolar 2kHz input signal.

EXTERNAL REFERENCE ON REFBUF

INTERNAL REFERENCE BUFFER

±10.24V RANGE

IN+ = 10V

IN– = 0V

TIME (µs)

100

200

300

400

500

–5

DEVIATION FROM FINAL VALUE (LSB)

233518 F12

±10.24V RANGE

TRUE BIPOLAR DRIVE (IN– = 0V)

SNR = 96.9dB

THD = –109dB

SINAD = 96.7dB

SFDR = 111dB

FREQUENCY (kHz)

100

200

300

400

500

–180

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

233518 F13

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

POWER CONSIDERATIONS

The LTC2335-18 provides four power supply pins: the

positive and negative high voltage power supplies (VCC

and VEE), the 5V core power supply (VDD) and the digital

input/output (I/O) interface power supply (OVDD). As long

as the voltage difference limits of 10V ≤ VCC – VEE ≤ 38V

are observed, VCC and VEE may be independently biased

anywhere within their own individual allowed operating

ranges, including the ability for either of the supplies to be

tied directly to ground. This feature enables the common

mode input range of the LTC2335-18 to be tailored to the

specific application’s requirements. The flexible OVDD sup-

ply allows the LTC2335-18 to communicate with CMOS

logic operating between 1.8V and 5V, including 2.5V and

3.3V systems. When using LVDS I/O mode, the range of

OVDD is 2.375V to 5.25V.

Power Supply Sequencing

The LTC2335-18 does not have any specific power supply

sequencing requirements. Care should be taken to adhere

to the maximum voltage relationships described in the

Absolute Maximum Ratings section. The LTC2335-18 has

an internal power-on-reset (POR) circuit which resets the

converter on initial power-up and whenever VDD drops

below 2V. Once the supply voltage re-enters the nominal

supply voltage range, the POR reinitializes the ADC. No

conversions should be initiated until at least 10ms after

a POR event to ensure the initialization period has ended.

When employing the internal reference buffer, allow 200ms

for the buffer to power up and recharge the REFBUF bypass

capacitor. Any conversion initiated before these times will

produce invalid results.

TIMING AND CONTROL

CNV Timing

The LTC2335-18 sampling and conversion is controlled

by CNV. A rising edge on CNV transitions the S/H circuits

from track mode to hold mode, sampling the input signals

and initiating a conversion. Once a conversion has been

started, it cannot be terminated early except by resetting

the ADC, as discussed in the Reset Timing section. For

optimum performance, drive CNV with a clean, low jitter

signal and avoid transitions on data I/O lines leading up

to the rising edge of CNV. Additionally, for best crosstalk

performance, avoid high slew rates on the analog inputs for

100ns before and after the rising edge of CNV. Converter

status is indicated by the BUSY output, which transitions

low-to-high at the start of each conversion and stays high

until the conversion is complete. Once CNV is brought high

to begin a conversion, it should be returned low between

40ns and 60ns later or after the falling edge of BUSY to

minimize external disturbances during the internal conver-

sion process. The CNV timing required to take advantage

of the reduced power nap mode of operation is described

in the Nap Mode section.

Internal Conversion Clock

The LTC2335-18 has an internal clock that is trimmed

to achieve a maximum conversion time of 550ns. With

a minimum acquisition time of 420ns, throughput per-

formance of 1Msps is guaranteed without any external

adjustments. The LTC2335-18 is a multiplexed ADC and

converts one channel per CNV edge, taking a minimum

of 1μs per conversion. Thus, while scanning N channels

(N = 1 to 8), a complete scan takes at least N μs and the

maximum per-channel throughput is 1/N Msps/ch.

Nap Mode

The LTC2335-18 can be placed into nap mode after a con-

version has been completed to reduce power consumption

between conversions. In this mode a portion of the device

applicaTions inForMaTion

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

circuitry is turned off, including circuits associated with

sampling the analog input signals. Nap mode is enabled

by keeping CNV high between conversions, as shown in

Figure 14. To initiate a new conversion after entering nap

mode, bring CNV low and hold for at least 420ns before

bringing it high again. The converter acquisition time (tACQ)

is set by the CNV low time (tCNVL) when using nap mode.

Power Down Mode

When PD is brought high, the LTC2335-18 is powered

down and subsequent conversion requests are ignored. If

this occurs during a conversion, the device powers down

once the conversion completes. In this mode, the device

draws only a small regulator standby current resulting in a

typical power dissipation of 0.36mW. To exit power down

mode, bring the PD pin low and wait at least 10ms before

initiating a conversion. When employing the internal refer-

ence buffer, allow 200ms for the buffer to power up and

recharge the REFBUF bypass capacitor. Any conversion

initiated before these times will produce invalid results.

applicaTions inForMaTion

Reset Timing

A global reset of the LTC2335-18, equivalent to a power-

on-reset event, may be executed without needing to cycle

the supplies. This feature is useful when recovering from

system-level events that require the state of the entire sys-

tem to be reset to a known synchronized value. To initiate

a global reset, bring PD high twice without an intervening

conversion, as shown in Figure 15. The reset event is trig-

gered on the second rising edge of PD, and asynchronously

ends based on an internal timer. Reset clears all serial data

output registers and restores the internal sequencer default

state of converting channels 0 through 7 sequentially, all

in SoftSpan 7. If reset is triggered during a conversion, the

conversion is immediately halted. The normal power down

behavior associated with PD going high is not affected by

reset. Once PD is brought low, wait at least 10ms before

initiating a conversion. When employing the internal refer-

ence buffer, allow 200ms for the buffer to power up and

recharge the REFBUF bypass capacitor. Any conversion

initiated before these times will produce invalid results.

Figure 15. Reset Timing for the LTC2335-18

CNV

tCONV

tCNVH

PDH

tPDL

BUSY

RESET

RESET TIME

SET INTERNALLY

SECOND RISING EDGE OF

PD TRIGGERS RESET

PD tWAKE

233518 F15

Figure 14. Nap Mode Timing for the LTC2335-18

CNV

tCONV

tACQ

BUSY

NAP NAP MODE

CNVL

233518 F14

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

Figure 16. Power Dissipation of the LTC2335-18

Decreases with Decreasing Sampling Frequency

applicaTions inForMaTion

Power Dissipation vs Sampling Frequency

When nap mode is employed, the power dissipation of

the LTC2335-18 decreases as the sampling frequency is

reduced, as shown in Figure 16. This decrease in aver-

age power dissipation occurs because a portion of the

LTC2335-18 circuitry is turned off during nap mode, and

the fraction of the conversion cycle (tCYC) spent napping

increases as the sampling frequency (fSMPL) is decreased.

DIGITAL INTERFACE

The LTC2335-18 features CMOS and LVDS serial interfaces,

selectable using the LVDS/CMOS pin. The flexible OVDD

supply allows the LTC2335-18 to communicate with any

CMOS logic operating between 1.8V and 5V, including 2.5V

and 3.3V systems, while the LVDS interface supports low

noise digital designs. Together, these I/O interface options

enable the LTC2335-18 to communicate equally well with

legacy microcontrollers and modern FPGAs.

Serial CMOS I/O Mode

As shown in Figure 17, in CMOS I/O mode the serial data

bus consists of a serial clock input, SCKI, serial data input,

SDI, serial clock output, SCKO, and serial data output,

SDO. Communication with the LTC2335-18 across this

bus occurs during predefined data transaction windows.

Within a window, the device accepts control words on SDI

to configure the SoftSpan range and channel for the next

conversion and program the sequencer, and outputs 24-bit

packets containing the conversion result and configuration

information from the previous conversion on SDO.

Figure 17. Serial CMOS I/O Mode, Direct Per-Conversion Configuration

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

C6 C5 C4 C3 C2 C1 C0

D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D17

CNV

CS = PD = 0

DON’T CARE

tACQ

BUSY

SCKO

SDO

SCKI

SDI

DON’T CARE

SAMPLE N

RECOMMENDED DATA TRANSACTION WINDOW

SAMPLE N + 1

CONTROL WORD FOR CONVERSION N + 1

24-BIT PACKET CONVERSION N 24-BIT PACKET CONVERSION N

(REPETITION)

CONVERSION RESULT CHANNEL ID SoftSpan CONVERSION RESULT

CH2 CH1 CH0D0 SS1SS2 SS0

tSSDISCKI

tHSDOSCKI

tDSDOSCKI

tBUSYLH

tHSDISCKI

tSCKIH

tQUIET

tSCKIL

tDSDOBUSYL

tCNVH

tSKEW

tCONV

tCNVL

tCYC

233518 F17

tSCKI

OVDD

VDD

VEE

VCC

WITH NAP MODE

CNVL

= 500ns

SAMPLING FREQUENCY (kHz)

200

400

600

800

1000

–6

–4

–2

SUPPLY CURRENT (mA)

233518 F16

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

applicaTions inForMaTion

New data transaction windows open 10ms after power-

ing up or resetting the LTC2335-18, and at the end of

each conversion on the falling edge of BUSY. The data

transaction should be completed with a minimum tQUIET

time of 20ns prior to the start of the next conversion, as

shown in Figure 17. New control words are only accepted

within this recommended data transaction window, but

configuration changes take effect immediately with no ad-

ditional analog input settling time required before starting

the next conversion.

Just prior to the falling edge of BUSY and the opening of

a new data transaction window, SCKO is forced low and

SDO is updated with the latest conversion result from the

just-completed conversion. Rising edges on SCKI serially

clock the conversion result and analog input channel con-

figuration information out on SDO and trigger transitions

on SCKO that are skew-matched to the data on SDO. The

resulting SCKO frequency is half that of SCKI.

SCKI rising edges also latch control words provided on

SDI, which are used to set the SoftSpan range and chan-

nel for the next conversion, and program the sequencer.

See the section Configuring the Multiplexer and SoftSpan

Range for further details. SCKI is allowed to idle either

high or low in CMOS I/O mode. As shown in Figure 18,

the CMOS bus is enabled when CS is low and is disabled

and Hi-Z when CS is high, allowing the bus to be shared

across multiple devices.

The data on SDO are formatted as a 24-bit packet consisting

of an 18-bit conversion result, 3-bit analog channel ID, and

3-bit SoftSpan code, all presented MSB first. As suggested

in Figures 17 and 18, if more than 24 SCKI clocks are

applied, the 24-bit packet is repeated indefinitely on SDO.

When interfacing the LTC2335-18 with a standard SPI

bus, capture output data at the receiver on rising edges

of SCKI. SCKO is not used in this case. In other applica-

tions, such as interfacing the LTC2335-18 with an FPGA

or CPLD, rising and falling edges of SCKO may be used

to capture serial output data on SDO in double data rate

(DDR) fashion. Capturing data using SCKO adds robust-

ness to delay variations over temperature and supply.

The LTC2335-18 guarantees a minimum data transfer

window (tACQ – tQUIET) of 400ns while converting at 1Msps.

Thus, if an application needs to read the full 24-bit packet

of conversion result plus channel ID and SoftSpan, the

minimum usable SCKI frequency is 60MHz. Applications

needing to read only the conversion result may send only

18 SCKI pulses and thus have a minimum SCKI frequency

of 45MHz. The LTC2335-18 supports CMOS SCKI frequen-

cies up to 100MHz.

Configuring the Multiplexer and SoftSpan Range in

CMOS I/O Mode

On power-up and after a reset, the LTC2335-18 defaults

to converting channels 0 through 7 sequentially, all in

SoftSpan 7. If this configuration does not need to be

changed, simply hold SDI low.

The LTC2335-18 multiplexer and SoftSpan range may

be controlled in two ways, depending on the needs of

the application. If the desired sequence of channels and

SoftSpan ranges are known ahead of time, the LTC2335-

18’s internal sequencer may be programmed with a se-

quence of up to 16 configurations, and will cycle through

those configurations on subsequent conversions without

further user intervention. Alternately, if ultimate flexibility

is desired, the LTC2335-18 may be directly controlled by

overwriting the sequencer each conversion with the chan-

nel and SoftSpan range for the following conversion. This

reconfiguration has no latency and requires no additional

settling time or digital I/O overhead.

Using the Sequencer

To use the internal sequencer of the LTC2335-18, first

program it as described below with the desired sequence

of up to 16 configurations. Each of these configurations

specifies the desired channel number and SoftSpan range

for one conversion. The LTC2335-18 will then apply the

first configuration to the first conversion, the second

configuration to the second conversion, and so on until

the end of the programmed sequence is reached, at which

point the cycle will start again from the beginning.

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

Figure 18. Programming the Sequencer for a 10-Conversion Sequence, Serial CMOS Bus Response to CS

PD = 0

DON’T CARE

BUSY

SCKO

SDO

SCKI

SDI

DON’T CARE

Hi-Z

24-BIT RESULT PACKET 24-BIT RESULT PACKET 24-BIT RESULT PACKET RESULT PACKET

(PARTIAL)

Hi-Z

CONTROL WORD

FOR CONV N + 2

CONTROL WORD

FOR CONV N + 1

CONTROL WORD

FOR CONV N + 3

CONTROL WORD

FOR CONV N + 4

CONTROL WORD

FOR CONV N + 5

CONTROL WORD

FOR CONV N + 6

CONTROL WORD

FOR CONV N + 7

CONTROL WORD

FOR CONV N + 8

CONTROL WORD

FOR CONV N + 9

CONTROL WORD

FOR CONV N + 10

PARTIAL WORD

(IGNORED)

tEN tDIS

233518 F18

applicaTions inForMaTion

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

applicaTions inForMaTion

Each data transaction window is an opportunity to program

the sequencer by clocking in a series of 8-bit control words

on SDI, each specifying a channel number and SoftSpan

range, as shown in Figures 17 and 18. To program the

sequencer with a series of up to 16 conversion configu-

rations, write in the corresponding control words in the

desired conversion order during a single data transaction.

Words beyond the 16th valid word will be ignored.

The control word format is as follows:

C[7] C[6] C[5] C[4] C[3] C[2] C[1] C[0]

V 0 CH[2] CH[1] CH[0] SS[2] SS[1] SS[0]

The V bit (C[7]) controls whether the LTC2335-18 should

consider this a valid word. Any words which have V =

0 are considered invalid and are ignored (though valid

words will still be accepted after an invalid word). Words

which have V = 1 will be added to the sequencer in the

order provided. The C[6] bit is reserved for future use and

should be set to 0. The CH[2:0] (C[5:3]) bits are a binary

value 0 to 7 controlling the channel to be converted. The

SS[2:0] (C[2:0]) bits specify the desired SoftSpan range

for the conversion, as described in Table 1.

Sequencer programming is completed when the next

conversion is started. At this time, any incomplete words

are considered invalid and discarded. If one or more

valid words were provided, the sequencer is completely

overwritten with the new sequence, and the just-initiated

conversion employs the first provided configuration.

If no valid words were provided during the data transac-

tion window, the sequencer program is unchanged, and

the pointer advances to the next entry in the previously

programmed cycle to configure the next conversion.

Thus, once the sequencer has been programmed, simply

hold SDI low during subsequent data transactions to

cycle continually through the programmed sequence of

configurations.

Direct Per-Conversion Configuration

As a special case of the sequencer, the LTC2335-18

multiplexer and SoftSpan range can be directly controlled

every conversion with no latency and no additional set-

tling time or digital I/O overhead. To use the part in this

direct fashion, simply supply one control word on SDI

during a data transaction to specify the desired channel

number and SoftSpan range for the following conversion,

as shown in Figure 17.

If the desired channel and SoftSpan range for conversion

N+1 are known before seeing the result of conversion N,

specify the configuration by clocking in the corresponding

control word on SDI while clocking out the first 8 bits,

then hold SDI low. This particular use case is illustrated in

Figure 17. If the desired configuration is not known until

after the conversion data has been read, clock in 24 zeros

on SDI while the 24 bits of data are being read out; since

the V bits of those words are then 0, they are ignored.

Once the configuration has been determined, clock in 8

more bits on SDI which specify the desired configuration

for conversion N+1.

Serial LVDS I/O Mode

In LVDS I/O mode, information is transmitted using

positive and negative signal pairs (LVDS+/LVDS−) with bits

differentially encoded as (LVDS+ − LVDS−). These signals

are typically routed using differential transmission lines

with 100Ω characteristic impedance. Logical 1s and 0s

are nominally represented by differential +350mV and

−350mV, respectively. For clarity, all LVDS timing diagrams

and interface discussions adopt the logical rather than

physical convention.

As shown in Figure 19, in LVDS I/O mode the serial data

bus consists of a serial clock differential input, SCKI, serial

data differential input, SDI, serial clock differential output,

SCKO, and serial data differential output, SDO. Communi-

cation with the LTC2335-18 across this bus occurs during

predefined data transaction windows. Within a window,

the device accepts control words on SDI to configure the

SoftSpan range and channel for the next conversion and

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

applicaTions inForMaTion

Figure 19. Serial LVDS I/O Mode, Direct Per-Conversion Configuration

C7 C6 C5 C4 C3 C2 C1 C0

D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D17

CNV

(CMOS)

CS = PD = 0

DON’T CARE

tACQ

BUSY

(CMOS)

SCKO

(LVDS)

SDO

(LVDS)

SCKI

(LVDS)

SDI

(LVDS)

DON’T CARE

SAMPLE N

RECOMMENDED DATA TRANSACTION WINDOW

SAMPLE N + 1

CONTROL WORD FOR CONVERSION N + 1

24-BIT PACKET CONVERSION N 24-BIT PACKET CONVERSION N

(REPETITION)

CONVERSION RESULT CHANNEL ID SoftSpan CONVERSION RESULT

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

CH2 CH1 CH0D0 SS1SS2 SS0

tHSDOSCKI

tDSDOSCKI

tBUSYLH

tHSDISCKI

tSCKIH

tQUIET

tDSDOBUSYL

tCNVH

tSKEW

tCONV

tCNVL

tCYC

233518

F19

tSSDISCKI

tSCKIL

tSCKI

program the sequencer, and outputs 24-bit packets con-

taining the conversion result and configuration information

from the previous conversion on SDO.

New data transaction windows open 10ms after power-

ing up or resetting the LTC2335-18, and at the end of

each conversion on the falling edge of BUSY. The data

transaction should be completed with a minimum tQUIET

time of 20ns prior to the start of the next conversion, as

shown in Figure 19. New control words are only accepted

within this recommended data transaction window, but

configuration changes take effect immediately with no ad-

ditional analog input settling time required before starting

the next conversion.

Just prior to the falling edge of BUSY and the opening of

a new data transaction window, SDO is updated with the

latest conversion result from the just-completed conver-

sion. Both rising and falling edges on SCKI serially clock the

conversion result and analog input channel configuration

information out on SDO. SCKI is also echoed on SCKO,

skew-matched to the data on SDO. Whenever possible,

it is recommend that rising and falling edges of SCKO be

used to capture DDR serial output data on SDO, as this will

yield the best robustness to delay variations over supply

and temperature.

SCKI rising and falling edges also latch control words

provided on SDI, which are used to set the SoftSpan range

and channel for the next conversion, and program the

sequencer. See the section Configuring the Multiplexer

and SoftSpan Range in LVDS I/O Mode for further details.

As shown in Figure 20, the LVDS bus is enabled when CS

is low and is disabled and Hi-Z when CS is high, allow-

ing the bus to be shared across multiple devices. Due to

the high speeds often involved in LVDS signaling, LVDS

bus sharing must be carefully considered. Transmission

line limitations imposed by the shared bus may limit the

maximum achievable bus clock speed. LVDS inputs are

internally terminated with a 100Ω differential resistor when

CS is low, while outputs must be differentially terminated

with a 100Ω resistor at the receiver (FPGA). SCKI must

idle in the low state in LVDS I/O mode, including when

transitioning CS.

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

applicaTions inForMaTion

Figure 20. Programming the Sequencer with a 10-Conversion Sequence, Serial LVDS Bus Response to CS

(CMOS)

PD = 0

DON’T CARE

BUSY

(CMOS)

SCKO

(LVDS)

SDO

(LVDS)

SCKI

(LVDS)

SDI

(LVDS)

DON’T CARE

Hi-Z

24-BIT RESULT PACKET 24-BIT RESULT PACKET 24-BIT RESULT PACKET RESULT PACKET

(PARTIAL)

Hi-Z

CONTROL WORD

FOR CONV N + 2

CONTROL WORD

FOR CONV N + 1

CONTROL WORD

FOR CONV N + 3

CONTROL WORD

FOR CONV N + 4

CONTROL WORD

FOR CONV N + 5

CONTROL WORD

FOR CONV N + 6

CONTROL WORD

FOR CONV N + 7

CONTROL WORD

FOR CONV N + 8

CONTROL WORD

FOR CONV N + 9

CONTROL WORD

FOR CONV N + 10

PARTIAL WORD

(IGNORED)

tEN tDIS 233518 F20

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

applicaTions inForMaTion

The data on SDO are formatted as a 24-bit packet consisting

of an 18-bit conversion result, 3-bit analog channel ID, and

3-bit SoftSpan code, all presented MSB first. As suggested

in Figures 19 and 20, if more than 24 SCKI clocks are

applied, the 24-bit packet is repeated indefinitely on SDO.

The LTC2335-18 guarantees a minimum data transfer

window (tACQ – tQUIET) of 400ns while converting at 1Msps.

Thus, if an application needs to read the full 24-bit packet

of conversion result plus channel ID and SoftSpan, the

minimum usable SCKI frequency is 30MHz (60Mbps).

Applications needing to read only the conversion result

may send only 18 SCKI edges and thus have a minimum

SCKI frequency of 22.5MHz (45Mbps). The LTC2335-18

supports LVDS SCKI frequencies up to 250MHz (500Mbps).

Configuring the Multiplexer and SoftSpan Range in

LVDS I/O Mode

On power-up and after a reset, the LTC2335-18 defaults

to converting channels 0 through 7 sequentially, all in

SoftSpan 7. If this configuration does not need to be

changed, simply hold SDI at an LVDS low level.

The LTC2335-18 multiplexer and SoftSpan range may be

controlled in two ways, depending on the needs of the ap-

plication. If the desired sequence of channels and SoftSpan

ranges are known ahead of time, the LTC2335-18’s internal

sequencer may be programmed with a sequence of up to

16 configurations, and will cycle through those configu-

rations on subsequent conversions without further user

intervention. Alternately if ultimate flexibility is desired, the

LTC2335-18 may be directly controlled by overwriting the

sequencer each conversion with the channel and SoftSpan

range for the following conversion. This reconfiguration

has no latency and requires no additional settling time or

digital I/O overhead.

Using the Sequencer

To use the internal sequencer of the LTC2335-18, first

program it as described below with the desired sequence

of up to 16 configurations. Each of these configurations

specifies the desired channel number and SoftSpan range

for one conversion. The LTC2335-18 will then apply the

first configuration to the first conversion, the second

configuration to the second conversion, and so on until

the end of the programmed sequence is reached, at which

point the cycle will start again from the beginning.

Each data transaction window is an opportunity to program

the sequencer by clocking in a series of 8-bit control words

on SDI, each specifying a channel number and SoftSpan

range, as shown in Figures 19 and 20. To program the

sequencer with a series of up to 16 conversion configu-

rations, write in the corresponding control words in the

desired conversion order during a single data transaction.

Words beyond the 16th valid word will be ignored.

The control word format is as follows:

C[7] C[6] C[5] C[4] C[3] C[2] C[1] C[0]

V 0 CH[2] CH[1] CH[0] SS[2] SS[1] SS[0]

The V bit (C[7]) controls whether the LTC2335-18 should

consider this a valid word. Any words which have V =

0 are considered invalid and are ignored (though valid

words will still be accepted after an invalid word). Words

which have V = 1 will be added to the sequencer in the

order provided. The C[6] bit is reserved for future use and

should be set to 0. The CH[2:0] (C[5:3]) bits are a binary

value 0 to 7 controlling the channel to be converted. The

SS[2:0] (C[2:0]) bits specify the desired SoftSpan range

for the conversion, as described in Table 1.

Sequencer programming is completed when the next

conversion is started. At this time, any incomplete words

are considered invalid and discarded. If one or more

valid words were provided, the sequencer is completely

overwritten with the new sequence, and the just-initiated

conversion employs the first provided configuration.

If no valid words were provided during the data transac-

tion window, the sequencer program is unchanged, and

the pointer advances to the next entry in the previously

programmed cycle to configure the next conversion.

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

Thus, once the sequencer has been programmed, simply

hold SDI at an LVDS low level during subsequent data

transactions to cycle continually through the programmed

sequence of configurations.

Direct Per-Conversion Configuration

As a special case of the sequencer, the LTC2335-18

multiplexer and SoftSpan range can be directly controlled

every conversion with no latency and no additional set-

tling time or digital I/O overhead. To use the part in this

direct fashion, simply supply one control word on SDI

during a data transaction to specify the desired channel

number and SoftSpan range for the following conversion,

as shown in Figure 19.

If the desired channel and SoftSpan range for conversion

N+1 are known before seeing the result of conversion N,

specify the configuration by clocking in the corresponding

control word on SDI while clocking out the first 8 bits,

then hold SDI at an LVDS low level. This particular use

case is illustrated in Figure 19. If the desired configura-

tion is not known until after the conversion data has been

read, clock in 24 zeros on SDI while the 24 bits of data

are being read out; since the V bits of those words are

then 0, they are ignored. Once the configuration has been

determined, clock in 8 more bits on SDI which specify the

desired configuration for conversion N+1.

applicaTions inForMaTion

To obtain the best performance from the LTC2335-18, a

four-layer printed circuit board (PCB) is recommended.

Layout for the PCB should ensure the digital and analog

signal lines are separated as much as possible. In particu-

lar, care should be taken not to run any digital clocks or

signals alongside analog signals or underneath the ADC.

Also minimize the length of the REFBUF to GND (Pin 20)

bypass capacitor return loop, and avoid routing CNV near

signals which could potentially disturb its rising edge.

Supply bypass capacitors should be placed as close as

possible to the supply pins. Low impedance common re-

turns for these bypass capacitors are essential to the low

noise operation of the ADC. A single solid ground plane

is recommended for this purpose. When possible, screen

the analog input traces using ground.

Reference Design

For a detailed look at the reference design for this con-

verter, including schematics and PCB layout, please refer

to DC2412A, the evaluation kit for the LTC2335-18.

boarD layouT

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

package DescripTion

Please refer to http://www.linear.com/product/LTC2335-18#packaging for the most recent package drawings.

LX48 LQFP 0113 REV A

0° – 7°

11° – 13°

0.45 – 0.75

1.00 REF

11° – 13°

9.00 BSC

A A

7.00 BSC

9.00 BSC

1.60

MAX

1.35 – 1.45

0.05 – 0.150.09 – 0.20 0.50

BSC 0.17 – 0.27

GAUGE PLANE

0.25

NOTE:

1. PACKAGE DIMENSIONS CONFORM TO JEDEC #MS-026 PACKAGE OUTLINE

2. DIMENSIONS ARE IN MILLIMETERS

3. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT

4. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER

5. DRAWING IS NOT TO SCALE

SEE NOTE: 4

C0.30 – 0.50

R0.08 – 0.20

7.15 – 7.25

5.50 REF

7.15 – 7.25

PACKAGE OUTLINE

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

SECTION A – A

0.50 BSC

0.20 – 0.30

1.30 MIN

LX Package

48-Lead Plastic LQFP (7mm × 7mm)

(Reference LTC DWG # 05-08-1760 Rev A)

LTCXXXX

LX-ES

Q_ _ _ _ _ _

XXYY

TRAY PIN 1

BEVEL PACKAGE IN TRAY LOADING ORIENTATION

COMPONENT

PIN “A1”

LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

 LINEAR TECHNOLOGY CORPORATION 2016

LT 0116 • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2335-18

relaTeD parTs

Typical applicaTion

PART NUMBER DESCRIPTION COMMENTS

ADCs

LTC2348-18/LTC2348-16 18-/16-Bit, 200ksps, 8-Channel Simultaneous

Sampling, ±3/±1LSB INL, Serial ADC

±10.24V SoftSpan Inputs with Wide Common Mode Range, 97/94dB SNR,

Serial CMOS and LVDS I/O, 7mm × 7mm LQFP-48 Package

LTC2378-20/LTC2377-20/

LTC2376-20

20-Bit, 1Msps/500ksps/250ksps,

±0.5ppm INL Serial, Low Power ADC

2.5V Supply, ±5V Fully Differential Input, 104dB SNR, MSOP-16 and

4mm × 3mm DFN-16 Packages

LTC2338-18/LTC2337-18/

LTC2336-18

18-Bit, 1Msps/500ksps/250ksps, Serial,

Low Power ADC

5V Supply, ±10.24V Fully Differential Input, 100dB SNR, MSOP-16 Package

LTC2328-18/LTC2327-18/

LTC2326-18

18-Bit, 1Msps/500ksps/250ksps, Serial,

Low Power ADC

5V Supply, ±10.24V Pseudo-Differential Input, 95dB SNR,

MSOP-16 Package

LTC2373-18/LTC2372-18 18-Bit, 1Msps/500ksps, 8-Channel, Serial ADC 5V Supply, 8 Channel Multiplexed, Configurable Input Range, 100dB SNR,

DGC, 5mm × 5mm QFN-32 Package

LTC2379-18/LTC2378-18/

LTC2377-18/LTC2376-18

18-Bit,1.6Msps/1Msps/500ksps/250ksps, Serial,

Low Power ADC

2.5V Supply, Differential Input, 101.2dB SNR, ±5V Input Range, DGC, Pin

Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages

LTC2380-16/LTC2378-16/

LTC2377-16/LTC2376-16

16-Bit, 2Msps/1Msps/500ksps/250ksps, Serial,

Low Power ADC

2.5V Supply, Differential Input, 96.2dB SNR, ±5V Input Range, DGC, Pin

Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages

LTC2387-18 18-Bit, 15Msps, ±3LSB INL, Serial SAR ADC ±4.096V Fully Differential Input, 96dB SNR, Serial LVDS I/O, 5mm × 5mm

QFN-32 Package

LTC1859/LTC1858/

LTC1857

16-/14-/12-Bit, 8-Channel, 100ksps, Serial ADC ±10V, SoftSpan, Single-Ended or Differential Inputs, Single 5V Supply,

SSOP-28 Package

LTC1609 16-Bit, 200ksps Serial ADC ±10V, Configurable Unipolar/Bipolar Input, Single 5V Supply, SSOP-28 and

SO-20 Packages

LTC1606/LTC1605 16-Bit, 250ksps/100ksps, Parallel ADC ±10V Input, 5V Supply, 75mW/55mW, SSOP-28 and SO-28 Packages

DACs

LTC2756/LTC2757 18-Bit, Serial/Parallel IOUT SoftSpan DAC ±1LSB INL/DNL, Software-Selectable Ranges,

SSOP-28/7mm × 7mm LQFP-48 Package

LTC2668 16-Channel 16-/12-Bit ±10V VOUT SoftSpan DACs ±4LSB INL, Precision Reference 10ppm/°C Max, 6mm × 6mm QFN-40 Package

References

LTC6655 Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.25V, 2ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package

LTC6652 Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.25V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package

Amplifiers

LT1468/LT1469 Single/Dual 90MHz, 22V/µs, 16-Bit Accurate Op Amp Low Input Offset: 75µV/125µV

LT1354/LT1355/LT1356 Single/Dual/Quad 1mA, 12MHz, 400V/µs Op Amp Good DC Precision, Stable with All Capacitive Loads

LT1357/LT1358/LT1359 Single/Dual/Quad 2mA, 25MHz, 800V/µs Op Amp Good DC Precision, Stable with All Capacitive Loads

–5V

31V

LTC2335-18

233518 TA02

ONLY CHANNEL 0 SHOWN FOR CLARITY

24V

ARBITRARY

–

0.1µF

47µF

IN0+

IN0–

½ LT1124

VCC

REFINREFBUFVEE

LOWPASS FILTERS

BW ~ 500kHz

6.6nF

49.9Ω

549Ω

18pF

IN+

IN–

2.49k

COMMON MODE

INPUT RANGE

DIFFERENTIAL MODE

INPUT RANGE: ±500mV

Digitize Differential Signals Over a Wide Common Mode Range