PCI ExpressTM Jitter Attenuator ICS874003-05 DATASHEET General Description Features The ICS874003-05 is a high performance Differential-to-LVDS Jitter Attenuator designed for use in PCI Express systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874003-05 has a bandwidth of 6.2MHz with <1dB peaking, easily meeting PCI Express Gen2 PLL requirements. * * * Three differential LVDS output pairs * * * * * * * * * Input frequency range: 98MHz to 128MHz The ICS874003-05 uses IDT's 3rd Generation FemtoClockTM PLL technology to achieve the lowest possible phase noise. The device is packaged in a 20-Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. Inputs Outputs QA[0:1], nQA[0:1] QB0, nQB0 0 (default) /2 /2 0 0 /5 /2 0 1 0 /4 /2 1 1 0 /2 /4 0 0 1 /2 /5 1 0 1 /5 /4 0 1 1 /4 /5 1 1 1 /4 /4 F_SEL1 F_SEL0 0 (default) 0 (default) 1 CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL Output frequency range: 98MHz to 320MHz VCO range: 490MHz - 640MHz Supports PCI-Express Spread-Spectrum Clocking High PLL bandwidth allows for better input tracking PCI Express (2.5 Gb/s) and Gen 2 (5 Gb/S) jitter compliant 0C to 70C ambient operating temperature Full 3.3V operating supply Available in lead-free (RoHS 6) packages Pin Assignment F_SEL[2:0] Function Table F_SEL2 One differential clock input ICS874003BG-05 REVISION B MARCH 21, 2014 QA1 VDDO QA0 nQA0 MR F_SEL0 nc VDDA F_SEL1 VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nQA1 VDDO QB0 nQB0 F_SEL2 OEB GND nCLK CLK OEA ICS874003-05 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View 1 (c)2014 Integrated Device Technology, Inc. ICS874003-05 Data Sheet PCI EXPRESSTMJITTER ATTENUATOR Block Diagram OEA Pullup F_SEL2:0 Pulldown 3 QA0 /5 /4 /2 (default) nQA0 QA1 CLK Pulldown nCLK Pullup Phase Detector VCO nQA1 490 - 640MHz 3 /5 /4 /2 (default) M = /5 (fixed) QB0 nQB0 MR Pulldown OEB Pullup ICS874003BG-05 REVISION B MARCH 21, 2014 2 (c)2014 Integrated Device Technology, Inc. ICS874003-05 Data Sheet PCI EXPRESSTMJITTER ATTENUATOR Pin Descriptions and Characteristics Table 1. Pin Descriptions Number Name Type Description 1, 20 QA1, nQA1 Output Bank A differential output pair. LVDS interface levels. 2, 19 VDDO Power Output supply pins. 3, 4 QA0, nQA0 Output Bank A differential output pair. LVDS interface levels. 5 MR Input Pulldown Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (nQx) to go low and the inverted outputs (Qx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 6, 9, 16 F_SEL0, F_SEL1, F_SEL2 Input Pulldown Frequency select pin for QAx/nQAx and QB0/nQB0 outputs. LVCMOS/LVTTL interface levels. 7 nc Unused 8 VDDA Power Analog supply pin. 10 VDD Power Core supply pin. 11 OEA Input Pullup 12 CLK Input Pulldown 13 nCLK Input Pullup 14 GND Power 15 OEB Input 17, 18 nQB0, QB0 Output No connect. Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are active. When LOW, the QAx/nQAx outputs are in a high-impedance state. LVCMOS/LVTTL interface levels. Non-inverting differential clock input. Inverting differential clock input. Power supply ground. Pullup Output enable pin for QB0 pins. When HIGH, the QB0/nQB0 outputs are active. When LOW, the QB0/nQB0 outputs are in a high-impedance state. LVCMOS/LVTTL interface levels. Bank B differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k Table 3. Output Enable Function Table Inputs Outputs OEA OEB QA[0:1], nQA[0:1] QB0, nQB0 0 0 High Impedance High Impedance 1 (default) 1 (default) Enabled Enabled ICS874003BG-05 REVISION B MARCH 21, 2014 3 (c)2014 Integrated Device Technology, Inc. ICS874003-05 Data Sheet PCI EXPRESSTMJITTER ATTENUATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVDS) Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, JA 86.7C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. LVDS Power Supply DC Characteristics, VDD = VDDO = 3.3V 5%, TA = 0C to 70C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Positive Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD - 0.16 3.3 VDD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 75 mA IDDA Analog Supply Current 16 mA IDDO Output Supply Current 75 mA Maximum Units Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V 5%, TA = 0C to 70C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current IIL Input Low Current OEA, OEB VDD = VIN = 3.465V 5 A F_SEL0, F_SEL1, F_SEL2, MR VDD = VIN = 3.465V 150 A OEA, OEB VDD = 3.465V, VIN = 0V -150 A F_SEL0, F_SEL1, F_SEL2, MR VDD = 3.465V, VIN = 0V -5 A ICS874003BG-05 REVISION B MARCH 21, 2014 4 (c)2014 Integrated Device Technology, Inc. ICS874003-05 Data Sheet PCI EXPRESSTMJITTER ATTENUATOR Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V 5%, TA = 0C to 70C Symbol Parameter Test Conditions Input High Current CLK IIH IIL Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 Minimum Typical Maximum Units VDD = VIN = 3.465V 150 A nCLK VDD = VIN = 3.465V 5 A CLK VDD = 3.465V, VIN = 0V -5 A nCLK VDD = 3.465V, VIN = 0V -150 A 0.15 1.3 V GND + 0.5 VDD - 0.85 V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 4D. LVDS DC Characteristics, VDD = VDDO = = 3.3V 5%, TA = 0C to 70C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change ICS874003BG-05 REVISION B MARCH 21, 2014 Test Conditions Minimum Typical Maximum Units 275 375 485 mV 50 mV 1.50 V 50 mV 1.20 5 1.35 (c)2014 Integrated Device Technology, Inc. ICS874003-05 Data Sheet PCI EXPRESSTMJITTER ATTENUATOR Table 5. AC Characteristics, VDD = VDDO = 3.3V 5%, TA = 0C to 70C Symbol Parameter Test Conditions Minimum Typical Units fMAX Output Frequency 320 MHz tjit(cc) Cycle-to-Cycle Jitter; NOTE 4 35 ps tsk(o) Output Skew; NOTE 4, 5 145 ps tsk(b) Bank Skew; NOTE 4, 6 55 ps 200 600 ps 47 53 % tR / tF Output Rise/Fall Time odc Output Duty Cycle tj tREFCLK_HF_RMS tREFCLK_LF_RMS Phase Jitter Peak-to-Peak; NOTE 1, 3 Phase Jitter RMS; NOTE 2, 3 Phase Jitter RMS; NOTE 2, 3 98 Maximum Bank A 20% to 80% 100MHz output, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 13.54 ps 125MHz output, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 13.13 ps 250MHz output, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 12.87 ps 100MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) 1.22 ps 125MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) 1.17 ps 250MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) 1.11 ps 100MHz output, Low Band: 10kHz - 1.5MHz 0.25 ps 125MHz output, Low Band: 10kHz - 1.5MHz 0.22 ps 250MHz output, Low Band: 10kHz - 1.5MHz 0.22 ps NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Peak-to-peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86ps peak-to-peak for a sample size of 106 clock periods. See IDT Application Note PCI Express Reference Clock Requirements, and also the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function. NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps rms for tREFCLK_HF_RMS (High Band) and 3.0 ps RMS for tREFCLK_LF_RMS (Low Band). See IDT Application Note PCI Express Reference Clock Requirements and also the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function. NOTE 3: Guaranteed only when input clock source is PCI Express Gen 2 compliant. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 6: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. ICS874003BG-05 REVISION B MARCH 21, 2014 6 (c)2014 Integrated Device Technology, Inc. ICS874003-05 Data Sheet PCI EXPRESSTMJITTER ATTENUATOR Parameter Measurement Information VDD 3.3V 5% VDD, VDDO VDDA nCLK V V Cross Points PP CMR CLK GND Differential Input Level 3.3V LVDS Output Load AC Test Circuit nQA0 nQAx, nQB0 QA0 QAx, QB0 nQA1 tcycle n tcycle n+1 tjit(cc) = |tcycle n - tcycle n+1| 1000 Cycles QA1 tsk(b) Cycle-to-Cycle Jitter Bank Skew nQAx, nQB0 nQx QAx, QB0 Qx nQy Qy Output Duty Cycle/Pulse Width/Period Output Skew ICS874003BG-05 REVISION B MARCH 21, 2014 7 (c)2014 Integrated Device Technology, Inc. ICS874003-05 Data Sheet PCI EXPRESSTMJITTER ATTENUATOR Parameter Measurement Information, continued nQAx, nQB0 80% 80% VOD 20% 20% QAx, QB0 tR tF Output Rise/Fall Time Offset Voltage Setup Differential Output Voltage Setup ICS874003BG-05 REVISION B MARCH 21, 2014 8 (c)2014 Integrated Device Technology, Inc. ICS874003-05 Data Sheet PCI EXPRESSTMJITTER ATTENUATOR Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perform- ance, power supply isolation is required. The ICS874003-05 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin. 3.3V VDD .01F 10 .01F 10F VDDA Figure 1. Power Supply Filtering Wiring the Differential Input to Accept Single-Ended Levels Figure 2 shows how a differential input can be wired to accept single ended levels. The reference voltage V1= VCC/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted to set V1 at 1.25V. The values below are for when both the single ended swing and VCC are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ICS874003BG-05 REVISION B MARCH 21, 2014 9 (c)2014 Integrated Device Technology, Inc. ICS874003-05 Data Sheet PCI EXPRESSTMJITTER ATTENUATOR Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Zo = 50 CLK CLK Zo = 50 Zo = 50 nCLK nCLK Differential Input LVHSTL IDT LVHSTL Driver R1 50 Differential Input LVPECL R2 50 R1 50 R2 50 R2 50 Figure 3A. CLK/nCLK Input Driven by an IDT Open Emitter LVHSTL Driver Figure 3B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V 3.3V 3.3V 3.3V Zo = 50 CLK CLK R1 100 nCLK Differential Input LVPECL nCLK Zo = 50 Receiver LVDS Figure 3C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver 3.3V 2.5V 3.3V 3.3V 2.5V R3 120 *R3 R4 120 Zo = 60 CLK CLK Zo = 60 nCLK nCLK HCSL *R4 Differential Input SSTL R1 120 Figure 3E. CLK/nCLK Input Driven by a 3.3V HCSL Driver ICS874003BG-05 REVISION B MARCH 21, 2014 R2 120 Differential Input Figure 3F. CLK/nCLK Input Driven by a 2.5V SSTL Driver 10 (c)2014 Integrated Device Technology, Inc. ICS874003-05 Data Sheet PCI EXPRESSTMJITTER ATTENUATOR Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins LVDS Outputs All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached. LVDS Driver Termination For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 and 132. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100 parallel resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmissionline reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The standard LVDS Driver termination schematic as shown in Figure 4A can be used with either type of output structure. Figure 4B, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver's amplitude and common-mode input range should be verified for compatibility with the output. ZO ZT ZT LVDS Receiver Figure 4A. Standard Termination LVDS Driver ZO ZT C ZT 2 LVDS ZT Receiver 2 Figure 4B. Optional Termination LVDS Termination ICS874003BG-05 REVISION B MARCH 21, 2014 11 (c)2014 Integrated Device Technology, Inc. ICS874003-05 Data Sheet PCI EXPRESSTMJITTER ATTENUATOR Schematic Example Figure 5 shows an example of ICS874003-05 application schematic. In this example, the device is operated at VDD = 3.3V. The decoupling capacitors should be located as close as possible to the power pin. Two examples of LVDS terminations are shown in this schematic. The input is driven either by a 3.3V LVPECL driver or a 3.3V LVCMOS. ICS874003-05 Figure 5. ICS874003-05 Schematic Example ICS874003BG-05 REVISION B MARCH 21, 2014 12 (c)2014 Integrated Device Technology, Inc. ICS874003-05 Data Sheet PCI EXPRESSTMJITTER ATTENUATOR PCI Express Application Note PCI Express jitter analysis methodology models the system response to reference clock jitter. The block diagram below shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link. In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is: Ht s = H3 s H1 s - H2 s The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: Y s = X s H3 s H1 s - H2 s In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)]. PCIe Gen 2A Magnitude of Transfer Function PCI Express Common Clock Architecture For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz - 50MHz) and the jitter result is reported in peak-peak. PCIe Gen 2B Magnitude of Transfer Function For PCI Express Gen 3, one transfer function is defined and the evaluation is performed over the entire spectrum. The transfer function parameters are different from Gen 1 and the jitter result is reported in RMS. PCIe Gen 1 Magnitude of Transfer Function For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz - 1.5MHz (Low Band) and 1.5MHz - Nyquist (High Band). The plots show the individual transfer functions as well as the overall transfer function Ht. ICS874003BG-05 REVISION B MARCH 21, 2014 PCIe Gen 3 Magnitude of Transfer Function For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock Requirements. 13 (c)2014 Integrated Device Technology, Inc. ICS874003-05 Data Sheet PCI EXPRESSTMJITTER ATTENUATOR Power Considerations This section provides information on power dissipation and junction temperature for the ICS874003-05. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS74003-05 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. * Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (75mA + 16mA) = 315.315mW * Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 75mA = 259.875mW Total Power_MAX = 315.3mW + 259.9mW = 575.2mW * 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 86.7C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.575W * 86.7C/W = 119.9C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board. Table 6. Thermal Resistance JA for 20-Lead TSSOP, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS874003BG-05 REVISION B MARCH 21, 2014 0 1 2.5 86.7C/W 82.4C/W 80.2C/W 14 (c)2014 Integrated Device Technology, Inc. ICS874003-05 Data Sheet PCI EXPRESSTMJITTER ATTENUATOR Reliability Information Table 7. JA vs. Air Flow Table for a 20-Lead TSSOP JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 86.7C/W 82.4C/W 80.2C/W Transistor Count The transistor count for ICS874003-05 is: 1418 Package Outline and Package Dimensions Package Outline - G Suffix for 20-Lead TSSOP Table 8. Package Dimensions Symbol N A A1 A2 b c D E E1 e L aaa All Dimensions in Millimeters Minimum Maximum 20 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 6.40 6.60 6.40 Basic 4.30 4.50 0.65 Basic 0.45 0.75 0 8 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS874003BG-05 REVISION B MARCH 21, 2014 15 (c)2014 Integrated Device Technology, Inc. ICS874003-05 Data Sheet PCI EXPRESSTMJITTER ATTENUATOR Ordering Information Table 9. Ordering Information Part/Order Number 874003BG-05LF 874003BG-05LFT Marking ICS74003B05L ICS74003B05L ICS874003BG-05 REVISION B MARCH 21, 2014 Package "Lead-Free" 20-Lead TSSOP "Lead-Free" 20-Lead TSSOP 16 Shipping Packaging Tube Tape & Reel Temperature 0C to 70C 0C to 70C (c)2014 Integrated Device Technology, Inc. ICS874003-05 Data Sheet PCI EXPRESSTMJITTER ATTENUATOR Revision History Sheet Rev Table Page B T9 17 Corrected marking information in ordering table to accurately match the ABS document 11/09/11 Updated the `Wiring the Differential Input to Accept Single-Ended Levels' Note. Updated the `LVDS Driver Termination" Note. Updated the `PCI Express Application" Note. Added ICS prefix to marking information in the Ordering Table. Deleted quantity from Tape and Reel. 3/21/14 T9 9 11 13 16 B Description of Change ICS874003BG-05 REVISION B MARCH 21, 2014 Date 17 (c)2014 Integrated Device Technology, Inc. ICS874003-05 Data Sheet PCI EXPRESSTMJITTER ATTENUATOR We've Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support Sales netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT's sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. 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