2 A es oe __(MARCOM)DC4042 DOCUMENT CONTROL MASTER i A ZiLAS GENERAL DESCRIPTION The CMOS Super8? offers new flexibility and sophistica- tion in 86-bit microcontrollers. The Super8 offers all the features necessary for industrial, consumer, and automo- tive applications with an enhanced feature set in CMOS technology. At the same time, the CMOS Super8 retains full pin-for-pin compatibility with the NMOS Super8. Avail- able in 48-pin DIP, and 44-, 68-pin PLCC, the CMOS Super is the jast word in general purpose controllers. CUSTOMER PROCUREMENT SPECIFICATION 288C00/01 CMOS SUPER8 ROMLESS MCU The Super& features a full-duplex, Universal Asynchro- nous Receiver/Transmitter (UART) with on-chip baud rate generator, on-chip oscillator, and a Direct Memory Access controller (DMA). Notes: All Signals with a preceding front slash, /, are active Low, e.g.: B/AV (WORD is active Low); /BAV (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power Vos Vop Ground GND Vv 3s DC-4042-04 = (5-17-93)a =iLOS Z88Coo/01 CPS DC-4042-04 GENERAL DESCRIPTION (Continued) * Low Address or Bit Programmable I/O XTAL /AS /OS RA/W /RESET Wi) Le R . _ Port 4 Machine Timing and K ] l yy Instruction Control ry Reset / WDT Counter/ ALU Timers (2) Flags UART K Register Pointers Interrupt i Program Control Register File > Counter 272 x 8-Bit Port 3 Port 2 Port 0 i > Port 1 Ni HA 4 High Address or Mux'ed Address/Data vO Bit Programmable |/O or Data oniy (Bit Programmable} * Only when used as demuxed external memory bus. Functional Block Diagram. Zeacoatt A SiLas CPS DC-4842-04 GENERAL DESCRIPTION (Continued) SEE SEEEESFEEEEEEE / 9 8 7 6 5 4 3 2 1 #68 67 6&6 65 64 63 62 61 \ we 10 60 NG yoo ah} oO 59 NwC Ce-MUX 12 58 oC Pig 13 57 POG P17 14 56 Pov P24 46 55 P34 P25 16 54 Pas VOC | i7 Zsscoo 53 AS GND | 18 (Top View) 52] 0s veo 1 51 Pag XTAL2 20 50 Pai XTALI 21 49 GNG Pea | 22 48 GNG Pas 7 23 47 Pa2 Pag | 24 46 7 pag Pa? 25 a5 Ru NC 26 44 NG N27 28 29 30 31 32:33 34 95 36 37 38 39 40 41-42 43 OA SLELELE VE SER LEESS a 68-Lead PLCC Pin Identification 68-Lead PLCC Pin Assignments Pin # Symbol = Function Direction Pin # Symbol Function Direction | NIC Not Connected 37 P30 Part 3, Pin O InfOutput 2-7 P15-10 Port 1, Pins 0,1,2,3,4.5 in/Qutput 38-39 P2?7-26 Pert 2, Pins 6,7 InfOutput 8-10 NiC Not Connected 40-41 P37-36 Port 3, Pins 7,6 InfOutput 14 Voc Power Supply Input 42 /RESET RESET Input 12 De-Mux De-multiptex Pin Input 43-44 NC Not Connected 13-14 Pt7-16 Port 1, Pins 6,7 InfOutput 45 RIW READ/WRITE Output 15-16 P25-24 Port 2, Pins 4,5 in/Output 46-47 P43-42 Port 4, Pins 3,2 InfOutput 17 Vow Power Supply Input 48-49 GND Ground Input 18 GND Ground Input 50-51 P41-40 Port 4, Pins 1,0 infOutput 49 Veo Power Supply Input 52 DS Data Strobe Outout 20 XTAL2 Crystal Oscillator Output 53 [AS Address Strobe Output 21 XTAL1 Crystal Oscillator Input 54-55 P35-34 Port 3, Pins 4.6 InfOutput 22-25 P47-44 Port 4, Pins 4,5,6,7 InfOutput 56-57 PO7-06 Port 0, Pins 7,6 InfOutput 26-27 NIC Not Connected 58 Vee Power Supply input 28 P22 Port 2, Pin 2 InfOutput 59-61 NC Not Connected 29 NIC Not Connected 62-67 PO5-00 Port 0, Pins 5,4,.3,2.1,0 In/Output 30-31 P33-32 Port 3, Pins 2,3 infOutput 68 GND Ground Input 32-34 P23-21 Port 2, Pins 3.0.1 infOutput 35 P31 Port 3, Pin 1 InfOutout 36 N/C Not ConnectedA ZILGS Ps Doane o4 P10 Ff 1 \ 48b Poo P11 7] 2 47) Pot P12 qj 3 467) Po2 P13 Cy] 4 45[] Pos Pid fy] 5 447] Pod PIS (| 6 43. P05 P16 oO 7 425 Po6 P17 Cc 8 ayy PO? P24 7 9 4015 P34 P25 [ 10 3915 P35 +5V O11 385 iAS XTAL2 [] 12 segep9 6997) DS XTAL1 oO 13 DIP 36 P40 P44 fp] 14 35 P41 Pas [] 15 3419 GND P46 [] 16 33) P42 P47 ] 17 32) P43 P22 [] 18 31) RW P32 (] 19 30] /RESET P33 fF] 20 2977 P36 P23 (] 21 28) P37 P20 ql 22 277) P27 P21] 23 26>] P26 P31 [J 24 25) 730 48-Lead DIP Pin identification 48-Lead DIP Pin Assignments Pin# Symbol Function Direction Pin# Symbol Function Direction 1-8 P17-10 Port 1, Pins 0,1,2,3.4,5,6.7 In/Output 28-29 =F37-36 Part 3. Pins 7,6 InfOutput 9-10 P25-24 Port 2, Pins 4,5 infOutput 30 /RESET RESET Input | Vee Power Supply Input 31 RiW READ/WRITE Output 12 XTAL2 = Crystal Oscillator Output 32-33 P43-42 Port 4, Pins 3.2 InfOutput : 34 GND Ground Input 13 XTAL1 = Crystai Oscillator Input 14-17 P47-44 Port 4, Pins 4,5,6,7 infOutout 35-36 P41-40 Port 4, Pins 1,0 InfOutput 18 P22 Port 2, Pin 2 in/Output 37 /DS Data Strobe Output - 38 {AS Address Strobe Qutput 19-20 P33-32 Port 3, Pins 2.3 InfOutput 39-40 36-34 Port 3, Pins 5.4 In/Outout e123 P2a21 Part 2, Pins 3.0.1 InfOutput 44-48 PO7-00 Port 0, Pins 7.6.5,4,3,2,1,0 In/Outout 24-25 P31-30 Port 3, Pins 1,0 InfOutput 26-27 P27-26 Port 2, Pins 6,7 InfOutputA SILAS ABSOLUTE MAXIMUM RATINGS Symbol Description Min Max Units Voc Supply Voltage (*) O03 +70 V Tose Storage Temp 65 +150 C T, Oper Ambient Temp t C Notes: * Yoltage on all pins with respect to GND. t See Ordering Information. ZBBCOWO CPS D442 Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sec- tions of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended pe- riod may affect device reliability. STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to V,.. Positive current flows into the referenced pin (Standard Test Load}. Standard conditions are: M@ 45V<V, <5.5V m GND-OV m 40C <T, < +105C +5V 1kQ From Output Under Test 150 pF 400 1A Standard Test Load ADDITIONAL FEATURE Weak Latches Ail input pins on the Super8? will be provided with weak latches. Weak latches on inputs prevent them from floating and reduces unnecessary current flow. Weak latches on inputs are automatically disabled when the corresponding output is configured as open-drain.. Z88CO0/01 A SILAS CPS DC-4042-04 eR RRR ER ERE Oona ooo 465 43 2 1 44 43 42 41 40 nc (7 39 [7 POs Pi 18 oO 38 [FJ vec Pi7 (9 37 (7) Pde P24 (] 10 36 [7 Po? P25 (J 11 35 (77) P34 vec (J 12 Z88C01 34 {_) P35 GND (13 33 [7] AS XTAL2 ([] 14 32 [] 0S XTAL1 ([] 15 31 7 GNO P47 (1) 16 30 (7 RAW P22 ([]17 29 (7) RESET 18 19 20 21 22 23 24 25 26 27 28 UUUUUGUU UO SESS SELES 44-Lead PLCC Pin Identification 44-Lead PLCC Pin Identification Pin # Symbol Function Direction Pin # Symbol Function Direction 1-6 P15-10 Port 1, Pins 0,1,2.3,4,5 !n/Output 23-24 P31-30 Port 3, Pins 1,0 InfOutput 7 NIC Not Connected 25-26 P27-26 Port 2, Pins 8,7 InfOutput 8-9 P417-16 Port 1, Pins 6,7 InfOutput 27-28 P37-36 Port 3, Pins 7,8 InfOuteut 10-14 P25-24 Port 2, Pins 4,5 InfOutput 29 /RESET Reset Input 12 Vow Power Supply Input 30 RAW ReadMrite Output 13 GND Ground Input 31 GND Ground Input 14 XTAL2 Crystal Oscillator Output 32 DS Data Strobe Output 15 XTAL1 Crystal Oscillator Input 33 IAS Address Strobe Output 16 P47 Port 4, Pin 7 InfOutput 34-35 P35-34 Port 3, Pins 5,4 InfOutput 17 P22 Port 2, Pin 2 InfOutput 36-37 PO?7-06 Port 0, Pins 7,6 InfOutput 18-19 P33-32 Port 3, Pins 2,3 InfOutput 38 Voe Power Supply Input 20-22 P23-21 Port 2, Fins 3.0,1 InfOutput 39-44 PO5-00 Port 0, Pins 5,4,3,2,1,0 In/OutputA ZILA ops De4r424 AC ELECTRICAL CHARACTERISTICS External I/O or Memory Read and Write Timing Normai Extended Number Symbol Parameter Min Max Min Max 1 TdA(AS) Address valid to /AS Rise Detay 25 50 2 ThHAS(A) /AS Rise to Address Vatid Hold Time 35 85 3 TdAS(DI} /AS Rise to Data In Required Valid Delay 150 335 4 TwAS /AS Low Width 35 85 5 TdAZ (DSR) Address Float to /DS (Read) 0 G 6 TwDSR /DS (Read) Low Width 125 275 7 TwDSW /DS (Write) Low Width 65 165 8 TdDSR (DI {DS (Read) to Data in Required Valid Delay 80 225 9 ThDSR(DI} /DS Rise (Read) to Data tn Hald Time 0 0 10 TdDS (A) /DS Rise to Address Active Delay 20 70 11 TdDA {AS} /DS Rise to /AS Delay 30 80 12 TdRMW (AS) RAW to AS Rise Delay 20 70 13 TdDS (RAV) DS Rise to RW Valid Delay 40 90 14 TdbDo (DSW) Data Out to /DS (Write} Delay 10 50 15 THDSW (DO) {DS Rise (Write) to Data Out Hold Time 20 85 16 TdA (DF Address to Data In Required Valid Delay 205 385 17 TdAS (DSR) /AS Rise to D/S (Read) Delay 50 95 19 TdDM (AS) /DM to /AS Rise Delay 28 70 20 TdDS (DM) /DS Rise to /DM Valid Delay 33 85 21 ThHDS (A) /DS Rise to Address Valid Hold Time 36 90 22 TwWw Wait Width (One Wait) Window [13 [1] 23 TdAS (W3 AS Rise to Wait Delay 90 335 Notes: [1] Not characterized function, guaranteed by design. The value of TsDI (DSR) has been measured for the NMOS part as mentioned below as TsD1 (DSR) cid. This cld" value needs to be relaxed as to the value described as TsDI (DSR) new. This nw value will allow the customer to use external memories with slower access times that immediately transiates in tower cost.: ZBscoont A SILAS CPS DC-4042-04 DC CHARACTERISTICS Symbol Parameter Min Max Unit Condition Vou Clock Input High Voltage 3.8 Vee Vv Driven by External Clock Generator Vox Clock Input Low Voltage 0.3 0.8 Vv Driven by External Clock Generator Vin Input High Voltage 0.7 Vig Veo Vv Vi Input Low Voltage 0.3 0.15 V,.. V Vou Reset Input High Voltage 3.8 Vee Vv Vee Reset Input Low Voltage 0.3 0.8 V Vou Output High Voltage 2.4 Vv loy=400 pA Vor Output Low Voltage 0.4 V Ij=+4.G mA Vie Input Leakage 10 10 pA low Output Leakage -10 10 pA lia Reset input Current -50 pA lee Vo Standby Current 90 mA [1] Notes: Estimated Valuas [1] tn this case all outputs and I/O pins are floating.A SILAS ZB8C00/01 CPS DC-40:42.04 INTERLOCKED MODE HANDSHAKE TIMING Data In Data In Valid Next Data in Valid f ee it y (Day Delayed DAV Npu f _-.~_/ RADY N\ Delayed DY 7 {Output} K__ _~ eee / Input Handshake Timing Fully Interlocked Mode Data Out (DAY (Output) RADY (Input) pawn ao -nna nae. Data Out Valid Next Data Out Valid { { wane eee. A 3 / ee ROY + Re ---/ Output Handshake Timing Fully Interlocked Mode AC ELECTRICAL CHARACTERISTICS Interiocked Mode Handshake Timing No. Symbol Parameter Notes (Data Direction) 1 TsD! (DAV) Data in Setup Time to /DAV In 2 TARDY (DI) RDY to Data in Hold Time In 3 TwDAV /DAV Width In 4 TdDAY (RDY) /DAV to RDY Delay In 5 TwDAV (RDY} DAV to RDY Wait Time In 6 TdRDY (DAV} RDY* to /DAV Delay In 7 TdDO (DAV) Data Out to /DAV Delay Out 8 TdDAVd (RDY) DAV to RDY Delay Out ) TaRDY (DAV) RDY ta /DAV Delay Out 10 TwRDY RDY Width Out 14 TwRDY (DAV) RDY4 to /DAV Wait Time Out 10A ZiLo OPS Bou nt 20 MHZ NORMAL TIMING RAW, OM Qe) Port 0 Port 1 AQ -A7 Ngee {x (ay ~ Y__ AO -A7 > _________{ DO - D7 IN 7 Ca) ( (9) (2) ( /AS \ | /DS (Read) ie Port 1 x Aot Do - 07 OUT AQ-A7 K. (DS (Write) (33) -~ 2 WAIT Ve External Memory Read And Write& 2iLGS Z88C00 ERRATA 1. Handshake Port 4 Input handshake (strobe and fully interiocked mode) with DMA is not functional. 2. UART Receive Upon receiving a character, the RCA (receive charac- ter available) interrupt is serviced twice. The time be- tween two consecutive interrupts at 14 MHz is 53 ps. Although the UIO is read, which normaily should clear the interrupt source, the ACA interrupt is asserted twice. 3. TTL Levels Vi ;, do not meet the TTL specification when the port is used as control inputs for the counter/timers, UART, handshake, external wait and interrupts. Instead V,, = 0.7 V., and V, = 0.15 Vo. 2Pacnon1 CPS DC-4042-04 4. DMA Usage Ne DMA can be performed to external memories if the wait feature (hardware wait and software wait) is used. 5. Reset Software Sequence After a hardware reset, program the POM register before the PM register. 6. Counter/Timers To obtain a 2.5 MHz signal from the counter/timers, ioad the Counter/Timer registers with FFFFH and count up. The equivalent operations for the NMOS part to obtain the 2.5 MHz signal is to foad the counter/timers with QGOOH and count down. Low Margin: Customer is advised that this product does not meet Zilog's internal guardbanded test policies for the specifi- cation requested anc is supplied on an exception basis. Customer is cautioned that delivery may be uncertain and that, in addition to all other limitations on Zilog liability stated on the front and back of the acknowiedgement, Zilog makes no claim as to quaiity and reliability under the CPS. The product remains subject to standard warranty for replacement due to defects in materials and workman- ship, 1993 by Zilog, Inc. Ali rights reserved. No part of this document may Oe copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold oy Zilog, Inc, are covered by warranty and patent indemnitication provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, exoress, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty ot mer- chantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this documert. Zilog, Inc. makes no commitment ta update or Keep current the information contained in this document. Zilog's products are not authorized for use as critical compo- nents in life support devices or systems unless a specific written agreement pertaining te sucn intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to resuit in significant injury to the user. Zilog, inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 12. z 1 BLOG os STROBE MODE HANDSHAKE TIMING DATA IN IDAV IN (2) 3) / LR Input Handshake Timing Strobed Mode DATA OUT {DA OUT Output Handshake Timing Strobed Mode AC ELECTRICAL CHARACTERISTICS Strobe Mode Handshake Timing No. Symbol Parameter Netes (Data Direction) 1 TsDK DAV} Data In to Setup Time /DAV In 2 TADAV(DI Data in Hold Time In 3 TwDAV IDAV Width In 4 TdDO(DAV} Data Out to /DAV Delay Out TwDAV Data Available Width Out 11