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FEATURES
10 years minimu m data r et ent io n in the
absence o f exter na l po w er
Dat a is automatically pro tect ed d uring power
loss
Rep laces 512k x 8 vo lat ile static RAM,
EEPROM or Flash memory
Unlim ited write c ycles
Low-po wer CMOS
Read and wr it e access times of 70ns
Lit h iu m energy so u r ce is elect ricall y
d iscon nect ed to retain fres hness unt il power is
applied for the first time
Full ±10% VCC o per ating range (DS1250Y)
Optional ±5% VCC o p er ating range
(DS1250AB)
Optional indust r ial t e mperat ure r ange of
-40°C to +85°C, des ig nat ed I N D
JEDEC standard 32-pin DIP package
Power Cap Modu le (PCM) packag e
- D ir ect ly sur face-mountable mo dule
- Rep laceab le snap-on Po werCap provides
lit hiu m backup bat ter y
- Standardized pino ut for all non volatile
SRAM products
- Det ach ment featur e o n PCM allows eas y
remo val us ing a regular scr ewd river
PIN ASSIGNMENT
PIN DESCRIPTION
A0 - A18 - Address Inputs
DQ0 - DQ7 - Data I n/Dat a Out
CE
- Chip Enable
WE
- Wr ite E nable
OE
- Output Enable
VCC - Po w er (+5V)
GND - Ground
NC - No Connect
DS1250Y/AB
4096k Nonvolatile SRAM
www.maxim-ic.com
13
1
2
3
4
5
6
7
8
9
10
11
12
14
31
740-mil EXTENDED
A14
A7
A5
A4
A3
A2
A1
A0
DQ1
DQ0
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ5
DQ6
32
30
29
28
27
26
25
24
23
22
21
19
20
A16
A12
A6
A18
DQ2
GND
15
16
18
17
DQ4
DQ3
1
NC
2
3
A15
A16
NC
VCC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
4
5
6
7
8
9
10
11
12
13
14
15
16
17
A17
A14
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34
A18
GND
V
BAT
34-Pin POWERCAP MODULE (P CM)
(Uese DS9034PC+ or DS9034PCI+ POWERCAP)
19-5647; Rev 12/ 10
DS1250Y/AB
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DESCRIPTION
The DS1250 4096k Nonvolatile SRAMs are 4,194,304-bit, fully stat ic, nonvolat ile SRAMs organized a s
524,288 words by 8 bits. Each complete NV SRAM has a self-contained lithium energy source and
c on tr ol c irc uitry whi c h c ons ta n tl y mon itor s VCC fo r an out-of-toler a nc e c o nd itio n. Whe n s uch a cond ition
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enabled t o p revent d ata co rrupt ion. DI P-package DS1250 device s can be used in place of exist ing 512k x
8 st at ic RAMs d ir ect ly confor ming to t he po pular byt e-w ide 32-pin DIP standard. DS1250 de vices in the
PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC
PowerCap to form a complete Nonvolatile SRAM module. There is no limit on the number of write
cycles that can be execut ed and no additio nal supp ort cir cuitry is required for microp r ocesso r interfac ing.
READ MODE
The DS1250 execut es a r ead cycle w he never
WE
(Wr ite Enable) is inactive ( h ig h) a nd
CE
(Chip Enable)
and
OE
(Output Enable) are active (low). The unique address specified by the 19 address inputs (A0 -
A18) de fines which o f the 524,288 byt es of data is to be accessed. Va lid data will be a vailable to the eight
data output drivers wit hin tACC (Access Time) after the last address input signal is stable, providing that
CE
and
OE
(Out put Enable) a ccess times ar e also satisf ied. If
OE
and
CE
access times are not sat isfied,
t hen data access must be measured from the later -oc curring signal (
CE
or
OE
) and t he l i mit ing par amet er
is either tCO for
CE
or tOE for
OE
rather than address access.
WRITE MODE
The DS1250 executes a write cycle whenever the
WE
and
CE
signals are active (low) after address
input s are stab le. T he lat er -o ccurring fal ling edge of
CE
or WE w ill det ermine t he start o f the wr ite c yc le.
The write cycle is terminated by the earlier rising edge of
CE
or
WE
. All address inputs must be kept
valid throughout the write cycle.
WE
must return to the high state for a minimum recovery time (tWR)
before another cycle can be initiated. The
OE
control signal should be kept inactive (high) during writ e
c ycle s t o a void bus co ntent io n. H oweve r, if t he o ut put driver s ar e e nabled (
CE
and
OE
ac tive) t he n
WE
will dis ab le the outp uts i n tODW fro m its falling edge.
DATA RETENTION MODE
The DS1250AB provides full functional capability for VCC greater than 4.75 volts and write protects by
4.5 volts. The DS1250Y provides full functional capability for VCC greater than 4.5 volts and write
prot e ct s by 4 . 2 5 volt s . Da t a is mainta in ed in t he a bs enc e o f V CC w ithout any addit io nal suppo rt c ircu itry.
The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high-
impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,
the power switching circuit connects external VCC to RAM and disconnects the lithium energy source.
No rmal RAM op erat ion can re sume a fter VCC exceeds 4.75 vo lt s for the DS1250AB and 4.5 vo lt s fo r the
DS1250Y.
FRESH NESS SEAL
Each DS1250 device is shipped from Maxim with its lithium energy source disconnected, guaranteeing
full ener gy capa cit y. When VCC is first applied at a leve l greater t han 4.25 volts, the lithiu m energy so ur ce
is enabled for bat tery back-up o peration.
DS1250Y/AB
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PACKAGES
The DS1250 is available in two packages: 32-pin DIP and 34-pin PowerCap Mo dule (PCM). The 32-pin
DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a single
package with a JEDEC-standard 600-mil DIP pinout. The 34-pin PowerCap Module integrates SRAM
memory and nonvolatile control into a module base along with contacts for connection to the lithium
battery in the DS9034PC PowerCap. The PowerCap Module package design allows a DS1250 PCM
device to be surface mounted without subjecting its lithium backup battery to destructive high-
temperature reflow soldering. After a DS1250 PCM module base is reflow soldered, a DS9034PC
PowerCap is snapped on top of the PCM to form a complete Nonvo latile SRAM module. The DS9034PC
is keyed to prevent improper attachment. DS1250 module bases and DS9034PC PowerCaps are ordered
separately and s hipped in separate cont ainers. See the DS90 34P C dat a sheet for furt her information.
DS1250Y/AB
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ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground -0.3V to +6. 0V
Operating Te mperat ur e
Commercial: 0°C to +70°C
Industrial: -40°C to +85°C
Stor ag e T emperat ur e
EDIP -40°C to +85°C
Power Cap -55°C to +125°C
Lead Temperature ( soldering, 10s) +260°C
Soldering Temper ature (reflow, PowerCap) +260°C
Note: EDIP is wa ve or ha nd solder ed o nl y.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
DS1250AB Power S upply
Voltage VCC 4.75 5.0 5.25 V
DS1250Y Power Supply Voltage VCC 4.5 5.0 5.5 V
Logic 1 VIH 2.2 VCC V
Logic 0 VIL 0.0 +0.8 V
DC ELECTRICAL CHARACTERISTICS (VCC = 5V ±5% for DS1250AB)
(TA: See Note 10) (VCC = 5V ±10% for DS12 50Y)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Cu r r ent IIL -1.0 +1.0 µA
I/O Leakage Cu r r ent
CE
≥ VIH ≤ VCC IIO -1.0 +1.0 µA
Output Current @ 2.4V IOH -1.0 mA
Output Current @ 0.4V IOL 2.0 mA
St andby Current
CE
=2.2V ICCS1 200 600 μA
St andby Current
CE
=VCC-0.5V ICCS2 50 150 μA
Operating Current ICCO1 85 mA
Write Protection Voltage (DS1250AB) VTP 4.50 4.62 4.75 V
Wr it e Protection Volt age (DS1250Y) VTP 4.25 4.37 4.5 V
CAPACITANCE (TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CIN 5 10 pF
I nput/O utput C a pacit a nce CI/O 5 10 pF
DS1250Y/AB
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AC ELECTRICAL C HAR AC TE R IS TIC S (VCC = 5V ±5% for DS12 50AB)
(TA: See Note 10) (VCC = 5V ±10% for DS1250Y)
PARAMETER SYMBOL DS1250AB-70
DS1250Y-70 UNITS NOTES
MIN MAX
Re a d Cycle Time tRC 70 ns
Access Time tACC 70 ns
OE
to O utp ut Valid tOE 35 ns
CE
to O utp ut Valid tCO 70 ns
OE
or
CE
to O utp ut Active tCOE 5 ns 5
Out put High-Z from Deselection tOD 25 ns 5
Output Hold from Address Change tOH 5 ns
Write Cycle Time tWC 70 ns
Writ e P ulse Width tWP 55 ns 3
A ddress Setup Time tAW 0 ns
Writ e Recover y Ti me tWR1
tWR2
5
15
ns
ns 12
13
Out put High-Z fr om
WE
tODW 25 ns 5
Output Active from
WE
tOEW 5 ns 5
Da ta Setu p Time tDS 30 ns 4
Da ta Hold Time tDH1
tDH2
0
10
ns
ns 12
13
DS1250Y/AB
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READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8, and 12
DS1250Y/AB
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WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8, and 13
POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
DS1250Y/AB
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POWER-DOWN/POWER-UP TIMING (TA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
VCC Fail Detect to
CE
and
WE
Inactive tPD 1.5 µs 11
VCC s l e w fr om VTP to 0V tF 150 µs
VCC slew from 0V to VTP tR 150 µs
VCC Valid to
CE
and
WE
Inactive tPU 2 ms
VCC Valid to E nd of Write Pr otection tREC 125 ms
(TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expect ed Data Ret ent io n T ime tDR 10 years 9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mo de.
NOTES:
1.
WE
is high for a Read Cycle.
2.
OE
= VIH o r V IL. If
OE
= VIH d uri ng w rite cycle, the outpu t buffers rema in in a hi gh-impeda nce state.
3. tWP is specified as the logical AND of
CE
and
WE
. tWP is measured from the latter of
CE
or
WE
go ing lo w t o t he ear lier o f
CE
or
WE
go ing h ig h.
4. tDH, tDS are measured from the ear lier o f
CE
or
WE
go ing h ig h.
5. T hese para met er s ar e samp led w ith a 5 pF load and are not 100% t ested.
6. I f the
CE
lo w tra ns it io n o cc ur s s imu lta neo usly w it h o r la tt er t han the
WE
low t ransit ion, the o utput
buff e rs rema in in a high-impedance stat e during this per iod.
7. If the
CE
high transition occurs prior to or simultaneously with the
WE
high transition, the output
bu ffe r s r e ma in in h ig h-impedance state during t his period.
8. If
WE
is low or the
WE
lo w t ra ns ition o cc ur s pr ior t o o r s imu lt ane o u s l y w it h t he
CE
lo w t ra ns ition ,
the out put bu f f e rs remain i n a high-impedance state during this per iod.
9. Each DS1250 has a built -in switc h that d isco nnect s the lit hiu m sou rce unt il t he user fir st app lies VCC.
The expect ed tDR is defined as accu mulat ive time in the absence o f VCC st arting fro m t he time power
is first applied by the user. This parameter is assured by component selection, process control, and
design. It is not measured directly during production testing.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
co mmer cia l pr od uct s, this r ang e is 0°C t o 70°C. For indu strial product s (IND), this range is -40°C t o
+85°C.
11. In a power-dow n c onditio n the volt a ge on a ny p i n may not e xc ee d the volt age on VCC.
12. tWR1 and tDH1 are measur ed fro m
WE
going high.
13. tWR2 and tDH2 are measur ed fro m
CE
go ing h ig h.
14. DS1250 modules are reco gnized by Underwrit ers Laborator ies (UL) under file E 99151.
DS1250Y/AB
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DC TEST CONDITIONS AC TEST CONDITIONS
Output s Open Output Load: 100 pF + 1TTL Gate
Cycle = 200 ns for operating current Input Pulse Levels: 0 - 3.0V
All voltages are refer enced to grou nd Timing Measur ement Referen ce Le vels
Input: 1.5V
Output : 1.5V
Input pulse Rise and Fall Times: 5 ns
ORDERING INFORMATION
PART TEMP RANGE
SUPPLY
TOLERANCE
PIN-PACKAGE
SPEED GRADE
(ns)
DS1250AB-70+
0°C to +70°C
5V ± 5%
32 740 EDIP
70
DS1250ABP-70+
0°C to +70°C
5V ± 5%
34 PowerCap*
70
DS1250AB-70IND+
-40°C to +85°C
5V
±
5%
32 740 EDIP
70
DS1250ABP-70IND+
-40°C to +85°C
5V ± 5%
34 PowerCap*
70
DS1250Y-70+
0°C to +70°C
5V ± 10%
32 740 EDIP
70
DS1250YP-70+
0°C to +70°C
5V ± 10%
34 PowerCap*
70
DS1250Y-70IND+
-40°C to +85°C
5V
±
10%
32 740 EDIP
70
DS1250YP-70IND+
-40°C to +85°C
5V
±
10%
34 PowerCap*
70
+Denotes a lead(Pb)-free/RoHS-compli ant package.
*DS9034PC+ or DS9034PCI+ (Pow erCap) required. Must be ordered separately.
PACKAGE INFORMATION
For the latest package outline information a nd land patterns, go to www.maxim-ic.com/packages. N ote that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix
character, b ut the dr awing pertains to t he p ackage re gardless of RoHS sta tus.
PACKAGE TYPE PACK AG E CODE OUTLINE NO. LAND PATTERN NO.
32 EDIP MDT32+6 —
21-0245
34 PCAP PC2+5 —
21-0246
DS1250Y/AB
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REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
121907
Added the Package Information table; remov ed th e DIP module
package drawing and dimension t able
8
12/10
Updated t he storage informat ion, sold ering temperature, and lead
t emperat ur e info rmatio n in the Absolute Maximum Ratings
section; removed the -100 MIN/MA X information from th e AC
Electrical Characteristics t able; updat ed the Ordering
Information tab le (r emo ved -100 parts and leaded -70 part s);
updated the Package Information table
1, 4, 5, 9