REVISIONS LTR DESCRIPTION A DATE (YR-MO-DA) Add logic diagram. Correct the parameters in waveforms, figure 4. Update boilerplate to MIL-PRF-38535 requirements. Editorial changes throughout. - jak 04-01-15 APPROVED Thomas M. Hess REV SHEET REV SHEET REV STATUS REV A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Jeffery Tunstall DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A COLUMBUS, OHIO 43216 http://www.dscc.dla.mil CHECKED BY Ray Monnin APPROVED BY Michael A. Frye DRAWING APPROVAL DATE 88-11-10 REVISION LEVEL A MICROCIRCUIT, DIGITAL, FAST CMOS, 9-BIT NONINVERTING REGISTER, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON SIZE CAGE CODE A 67268 SHEET DSCC FORM 2233 APR 97 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 1 OF 5962-88656 13 5962-E076-04 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-88656 01 K A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54FCT823A 9-bit non-inverting register with clock enable and clear, TTL compatible inputs 02 54FCT823B 9-bit non-inverting register with clock enable and clear, TTL compatible inputs 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter K L 3 Descriptive designator GDFP2-F24 or CDFP3-F24 GDFP3-T24 or CDIP4-T24 CQCC1-N28 Terminals Package style 24 24 28 Flat pack Dual-in-line package Square chip carrier package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ Supply voltage range ........................................................... Input voltage range .............................................................. Output voltage range ........................................................... DC input diode current (IIK) .................................................. DC output diode current (IOK)............................................... DC output current ................................................................ Maximum power dissipation (PD) 2/ .................................... Thermal resistance, junction-to-case (JC)........................... Storage temperature range.................................................. Junction temperature (TJ) .................................................... Lead temperature (soldering, 10 seconds) .......................... -0.5 V dc to +6.0 V dc -0.5 V dc to VCC + 0.5 V dc -0.5 V dc to VCC + 0.5 V dc -20 mA -50 mA 100 mA 500 mW See MIL-STD-1835 -65C to +150C +175C +300C 1.4 Recommended operating conditions. Supply voltage range (VCC).................................................. Maximum low level input voltage (VIL) ................................. Minimum high level input voltage (VIH) ................................ Case operating temperature range (TC)............................... +4.5 V dc to +5.5 V dc 0.8 V dc 2.0 V dc -55C to +125C 1/ All voltages referenced to GND. 2/ Must withstand the added PD due to short circuit test, e.g.; IOS. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88656 A REVISION LEVEL A SHEET 2 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88656 A REVISION LEVEL A SHEET 3 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked as listed in MIL-HDBK-103 (see 6.6 herein). For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. 3.5.1 Certification/compliance mark. A compliance indicator "C" shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator "C" shall be replaced with a "Q" or "QML" certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required in accordance with MIL-PRF-38535, appendix A. 3.9 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88656 A REVISION LEVEL A SHEET 4 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C VCC = 5.0 V dc 10% unless otherwise specified Group A subgroups Device type Limits Min High level output voltage Low level output voltage VOH VOL Unit Max VCC = 4.5 V VIL = 0.8 V VIH = 2.0 V IOH = -300 A 1, 2, 3 All 4.3 IOH = -15 mA 1, 2, 3 All 2.4 VCC = 4.5 V VIL = 0.8 V VIH = 2.0 V IOL = 300 A 1, 2, 3 All 0.2 IOL = 32 mA 1, 2, 3 All 0.5 V V Input clamp voltage VIK VCC = 4.5 V, IIN = -18 mA 1 All -1.2 V High level input current IIH VCC = 5.5 V, VIN = 5.5 V 1, 2, 3 All 5.0 A Low level input current High impedance current, output high High impedance current, output low IIL VCC = 5.5 V, VIN = GND 1, 2, 3 All -5.0 A IOZH VCC = 5.5 V, VIN = 5.5 V 1, 2, 3 All 10.0 A IOZL VCC = 5.5 V, VIN = GND 1, 2, 3 All -10.0 A Short circuit output current Quiescent power supply current (CMOS inputs) IOS VCC = 5.5 V 1/ 1, 2, 3 All 1, 2, 3 All 1.5 mA Quiescent power supply current (TTL inputs) ICC 1, 2, 3 All 2.0 mA Dynamic power supply current ICCD 3/ All 0.25 mA/ MHz Total power supply current ICC VIN 5.3 V or VIN 0.2 V VCC = 5.5 V, fi = 10 MHz OE = GND Outputs open One bit toggling, 50% duty cycle 1, 2, 3 All 4.0 mA VIN = 3.4 V or VIN = GND VCC = 5.5 V, fi = 10 MHz OE = GND Outputs open One bit toggling, 50% duty cycle 1, 2, 3 All 6.0 mA ICCQ VIN 0.2 V or VIN 5.3 V VCC = 5.5 V fi = 0 MHz VCC = 5.5 V VIN = 3.4 V 2/ VCC = 5.5 V, OE = GND -75 mA VIN 5.3 V or VIN 0.2 V Outputs open, One bit toggling 50% duty cycle 4/ See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88656 A REVISION LEVEL A SHEET 5 TABLE I. Electrical performance characteristics - Continued. Test Symbol Input capacitance Output capacitance Functional tests CIN COUT Propagation delay time, CP to Yn tPLH1, tPHL1 Propagation delay time , output enable, OE to Yn Propagation delay time, output disable, OE to Yn tPZH, tPZL tPHZ, tPLZ See 4.3.1c See 4.3.1c See 4.3.1d RL = 500 See figure 4 OE = low RL = 500 See figure 4 RL = 500 See figure 4 Group A subgroups Device type CL = 50 pF 4 4 7, 8 9, 10, 11 CL = 300 pF 5/ 9, 10, 11 CL = 50 pF 9, 10, 11 CL = 300 pF 5/ 9, 10, 11 CL = 50 pF 9, 10, 11 CL = 5.0 pF 5/ 9, 10, 11 All All All 01 02 01 02 01 02 01 02 01 02 01 02 01 02 01 02 01 02 01 02 01 02 01 02 01 02 01 02 CL = 50 pF RL = 500 See figure 4 Limits Min Propagation delay time, CLR to Yn Dn to CP setup time ts1 Dn to CP hold time th1 9, 10, 11 OE (low-to-high) to CP setup time ts2 9, 10, 11 OE to CP hold time th2 9, 10, 11 CLR recovery time (low-to-high) CP pulse width ts3 9, 10, 11 tw1 9, 10, 11 tw2 9, 10, 11 CLR pulse width, (CLR = low) tPHL2 Conditions -55C TC +125C VCC = 5.0 V dc 10% unless otherwise specified 9, 10, 11 9, 10, 11 Unit Max 10 12 pF pF 12.0 8.5 20.0 16 15.0 9.0 25.0 16.0 18.0 8.0 10.0 7.0 20.0 9.5 ns ns ns ns ns ns ns 4.0 3.0 2.0 1.5 4.0 3.0 2.0 0.0 7.0 6.0 7.0 6.0 7.0 6.0 ns ns ns ns ns ns ns 1/ Not more than one output should be shorted at one time, and the duration of the short circuit condition should not exceed one second. 2/ TTL driven input (VIN = 3.4 V); all other inputs at VCC or GND. 3/ This parameter is not directly testable, but is derived for use in total power supply calculations. 4/ ICC = ICCQ + (ICC x DH x NT) + (ICCD (fI x NI + fCP/2)) Where: DH = Duty cycle for TTL inputs high. NT = Number of TTL inputs at DH. fI = Input frequency in MHz. NI = Number of inputs at fI. fCP = clock frequency in MHz 5/ This parameter is guaranteed, if not tested, to the specified limits. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88656 A REVISION LEVEL A SHEET 6 Device types Case outlines Terminal number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 01 and 02 K and L 3 Terminal symbol NC OE D0 D1 D2 D3 D4 NC D5 D6 D7 D8 CLR GND NC CP EN Y8 Y7 Y6 Y5 NC Y4 Y3 Y2 Y1 Y0 VCC OE D0 D1 D2 D3 D4 D5 D6 D7 D8 CLR GND CP EN Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 VCC --------- NC = No connection. Terminal description Symbol Description Dn (n = 0 to 8) Data inputs CLR Clear input. For both inverting and noninverting registers, when the clear input is low and OE is low, the Qn outputs on the flip-flop are low. When the clear input is high, data can be entered into the register. CP Clock pulse for the register; enters data into the register on the low-to-high transition. Yn (n = 0 to 8) Register output EN Clock enable. When the clock enable is low, data on the Dn input is transferred to the Qn output of the flip-flop on the low-to-high transition of the clock. When the clock enable is high, the Qn outputs do not change state regardless of the data or clock input transitions. OE Output enable control input. When the OE input is high, the Yn outputs are in the high impedance state. When the OE input is low, the true regisiter data is present at the Yn outputs. Qn (n = 0 to 8) Internal outputs of the flip-flop. FIGURE 1. Terminal connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88656 A REVISION LEVEL A SHEET 7 Inputs OE H H H L H L H H L L CLR X X L L H H H H H H EN L L X X H H L L L L Dn L H X X H H L H L H CP X X X X Internal outputs Outputs Qn L H L L NC NC L H L H Yn Z Z Z L Z NC Z Z L H Function High Z Clear Hold Load L = Low voltage level H = High voltage level X = Irrelevant NC = No change Z = High impedance state = Low-to-high transition FIGURE 2. Truth table. FIGURE 3. Logic diagram. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88656 A REVISION LEVEL A SHEET 8 FIGURE 4. Switching waveforms and test circuit. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88656 A REVISION LEVEL A SHEET 9 NOTES: 1. Diagram shown for input control enable - low and input control disable - high. 2. Pulse generator for all pulses: tf 2.5 ns, tr 2.5 ns. FIGURE 4. Switching waveforms and test circuit - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88656 A REVISION LEVEL A SHEET 10 Test tPLZ tPZL All other Switch Closed Closed Open NOTES: 1/ RL = 500. 2/ Load capacitance includes jig and probe capacitance. See characteristics in table I for values. 3/ RT = Termination should be equal to ZOUT of pulse generators. FIGURE 4. Switching waveforms and test circuit - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88656 A REVISION LEVEL A SHEET 11 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD-883. (2) TA = +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. TABLE II. Electrical test requirements. MIL-STD-883 test requirements Interim electrical parameters (method 5004) Final electrical test parameters (method 5004) Group A test requirements (method 5005) Groups C and D end-point electrical parameters (method 5005) Subgroups (in accordance with MIL-STD-883, method 5005, table I) ---1*, 2, 3, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3 * PDA applies to subgroup 1. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-883 including groups A, B, C, and D inspections. The following additional criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 5, and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (CIN and COUT measurements) shall be measured only for the initial test and after process or design changes which may affect input capacitance. Test all applicable pins on five devices with zero failures. d. Subgroups 7 and 8 shall include verification of the truth table as specified on figure 2 herein. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88656 A REVISION LEVEL A SHEET 12 4.3.2 Groups C and D inspections. a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test conditions, method 1005 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. (2) TA = +125C, minimum. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing. 6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus when a system application requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. 6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43216-5000, or telephone (614) 692-0547. 6.6 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103. The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88656 A REVISION LEVEL A SHEET 13 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 04-01-15 Approved sources of supply for SMD 5962-88656 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. Standard microcircuit drawing PIN 1/ 5962-8865601KA 5962-8865601LA 5962-88656013A 5962-8865602KA 5962-8865602LA 5962-88656023A Vendor CAGE number 3/ 61772 61772 3/ 61772 61772 Vendor similar PIN 2/ 54FCT823AEB IDT54FCT823ADB IDT54FCT823ALB 54FCT245BEB IDT54FCT823BDB IDT54FCT823BLB 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. 3/ Not available from an approved source of supply. Vendor CAGE number 61772 Vendor name and address Integrated Device Technology, Inc. 2975 Stender Way Santa Clara, CA 95054 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.