Dual SPDT CMOS Analog Switch HI-5051/883 Features This CMOS analog switch offers low resistance switching performance for analog voltages up to the supply rails and for signal currents up to 70mA. "ON" resistance is low and stays reasonably constant over the full range of operating signal voltage and current. RON remains exceptionally constant for input voltages between +5V and -5V and currents up to 50mA. Switch impedance also changes very little over temperature, particularly between 0C and +75C. RON is nominally 25. * This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The HI-5051/883 provides break-before-make switching and is TTL and CMOS compatible for maximum application versatility. Performance is further enhanced by Dielectric Isolation processing which insures latch-free operation with very low input and output leakage currents (0.8nA at +25C). The HI-5051/883 switch also features very low power operation (1.5mW at +25C). The HI-5051/883 is available in a 20 Ld CLCC package and operates over the -55C to +125C temperature range. * Wide Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . 15V * Low "ON" Resistance . . . . . . . . . . . . . . . 25 (Typ), 50 (Max) * High Current Capability . . . . . . . . . . . . . . . . . . . . . 70mA (Max) * Break-Before-Make Switching - Turn-On Time. . . . . . . . . . . . . . . . . 370ns (Typ), 800ns (Max) - Turn-Off Time . . . . . . . . . . . . . . . 280ns (Typ), 400ns (Max) * No Latch-Up * Input MOS Gates are Protected from Electrostatic Discharge * DTL, TTL, CMOS, PMOS Compatible Applications * High Frequency Switching * Sample and Hold * Digital Filters * Operational Amplifier Gain Switching Functional Diagram Pin Configuration LOGIC "1" INPUT HI-5051/883 20 LD CLCC TOP VIEW VL 12 LOGIC "0" INPUT S1 NC D1 NC S1 A1 3 2 1 20 S3 19 A1 D3 4 18 V- S3 5 17 VR NC 6 16 NC S4 7 15 VL D4 8 14 V+ 9 10 11 12 A2 S2 S4 11 16 1 4 15 3 D1 D3 8 6 D2 10 9 5 13 VR 13 V+ D4 14 V- TYPICAL SWITCH NC D2 NC S2 A2 S NOTE: Unused pins may be internally connected. Ground all unused pins. A Ordering Information PART NUMBER PART MARKING TEMP. RANGE (C) HI4-5051/883 HI4-5051 883 -55 to +125 May 3, 2012 FN8289.0 1 PACKAGE PKG. DWG. # 20 Ld CLCC J20.A N P D NOTE: Source and Drain are arbitrarily depicted as Analog Input and Output, respectively. They may be interchanged without affecting performance. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 1989, 2012. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. HI-5051/883 Absolute Maximum Ratings Thermal Information Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V VSUPPLY to Ground (V+, V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V VR to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY VL to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY Digital and Analog Input Voltage (VA, VS, VD) . . . . . . . . . . . . +VSUPPLY +4V -VSUPPLY -4V Peak Current (Source to Drain) (Pulse at 1ms, 10% Duty Cycle Max) . . . . . . . . . . . . . . . . . . . . . . . . 70mA Continuous Current (Any Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<2000V Thermal Resistance JA (C/W) JC (C/W) CLCC Package. . . . . . . . . . . . . . . . . . . . . . . . 8O 20 Package Power Dissipation at +75C CLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Package Power Dissipation Derating Factor above +75C CLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.5mW/C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . . . . . . . .+300C Recommended Operating Conditions Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . .-55C to +125C Operating Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V Logic Supply Voltage (VL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.0V Logic Reference Voltage (VR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.0V Analog Input Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Address Low Level (VAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 0.8V Address High Level (VAH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V to +5.0V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. TABLE 1. D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Tested at: Supply Voltage = 15V, VL = +5.0V, VR = 0.0V, VAH = 2.4V, VAL = +0.8V, unused pins are grounded, unless otherwise specified. D.C. PARAMETERS Switch "ON" Resistance SYMBOL RDS2 CONDITIONS VD = -10V, IS = 10mA S1/S2/S3/S4 VD = 10V, IS = -10mA S1/S2/S3/S4 Source "OFF" Leakage Current IS(OFF) VS = -10V, VD = 10V S1/S2/S3/S4 VS = 10V, VD = -10V S1/S2/S3/S4 Drain "OFF" Leakage Current ID(OFF) VD = -10V, VS = 10V S1/S2/S3/S4 VD = 10V, VS = -10V S1/S2/S3/S4 Channel "ON" Leakage Current ID(ON) VD = VS = 10V S1/S2/S3/S4 VD = VS = -10V S1/S2/S3/S4 Low Level Address Current IAL VA = 0V A1 , A2 High Level Address Current IAH VA = 2.4V, 5V A1 , A2 Positive Supply Current +ICC VA = 0V, 5V A1 , A2 Negative Supply Current -ICC 2 VA = 0V, 5V A1 , A2 GROUP A SUBGROUPS TEMPERATURE (C) MIN MAX UNITS 1 +25 - 45 2, 3 -55 to +125 - 50 1 +25 - 45 2, 3 -55 to +125 - 50 1 +25 -1 1 nA 2, 3 -55 to +125 -100 100 nA 1 +25 -1 1 nA 2, 3 -55 to +125 -100 100 nA 1 +25 -1 1 nA 2, 3 -55 to +125 -100 100 nA 1 +25 -1 1 nA 2, 3 -55 to +125 -100 100 nA 1 +25 -2 2 nA 2, 3 -55 to +125 -200 200 nA 1 +25 -2 2 nA 2, 3 -55 to +125 -200 200 nA 1 +25 -1 1 A 2, 3 -55 to +125 -10 1 A 1 +25 -1 1 A 2, 3 -55 to +125 -1 10 A 1 +25 - 200 A 2, 3 -55 to +125 - 300 A 1 +25 -200 - A 2, 3 -55 to +125 -300 - A FN8289.0 May 3, 2012 HI-5051/883 TABLE 1. D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) Device Tested at: Supply Voltage = 15V, VL = +5.0V, VR = 0.0V, VAH = 2.4V, VAL = +0.8V, unused pins are grounded, unless otherwise specified. D.C. PARAMETERS SYMBOL Logic Supply Current +IL Reference Supply Current CONDITIONS GROUP A SUBGROUPS TEMPERATURE (C) MIN MAX UNITS 1 +25 - 200 A 2, 3 -55 to +125 - 300 A 1 +25 -200 - A 2, 3 -55 to +125 -300 - A VA = 0V, 5V VA = 0V, 5V +IR TABLE 2. A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Tested at: Supply Voltage = 15V, VL = +5.0V, VR = 0.0V, VAH = +5.0V, VAL = +0.0V, unused pins are grounded, unless otherwise specified. PARAMETERS SYMBOL Turn "ON" Time tON Turn "OFF" Time tOFF GROUP A SUBGROUPS TEMPERATURE (C) MIN MAX UNITS VS = 10V, -10V CL = 10pF RL = 1k 11 -55 - 450 ns 9 +25 - 500 ns 10 +125 - 800 ns VS = 10V, -10V CL = 10pF RL = 1k 11 -55 - 350 ns 9 +25 - 450 ns 10 +125 - 600 ns CONDITIONS TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS (NOTE 1) Device Characterized at: Supply Voltage = 15V, VL = +5.0V, VR = 0.0V, VAH = 4.0V, VAL = 0.8V, unused pins are grounded, unless otherwise specified. PARAMETERS SYMBOL "ON" Resistance Match (Channel to Channel) NOTE TEMPERATURE (C) MIN MAX UNITS RON2 Match VD = 10V ID = 10mA 1 +25 - 10 CA VA = 0V, 5V 1 +25 - 45 pF Address Capacitance CONDITIONS Switch Input Capacitance CS(OFF) Switch Off: VA = 0V 1 +25 - 60 pF Switch Output Capacitance CD(OFF) Switch Off: VA = 0V 1 +25 - 60 pF CD(ON) Switch On: VA = 5V 1 +25 - 60 pF Drain to Source Capacitance CDS(OFF) Switch Off: VA = 0V 1 +25 - 10 pF Off Isolation VISO VS = 2VP-P @ f = 100kHz, RL = 100 1 +25 - 60 dB Crosstalk VCT VS = 2VP-P @ f = 100kHz, RL = 100 1 +25 - 60 dB Charge Transfer Error VCTE VS = GND, CL = 0.01F VA = 0V to 4V @ f = 200kHz 1 +25 - 30 mV NOTE: 1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production runs which reflect lot to lot and within lot variation. TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS Interim Electrical Parameters (Pre Burn-in) Final Electrical Test Parameters SUBGROUPS (See Tables 1 and 2) 1 1 (Note 2), 2, 3, 9, 10, 11 Group A Test Requirements 1, 2, 3, 9, 10, 11 Groups C & D Endpoints 1 NOTE: 2. PDA applies to Subgroup 1 only. 3 FN8289.0 May 3, 2012 HI-5051/883 Test Circuits 10mA RON = V2 V2 10mA ID(OFF) IS(OFF) IN OUT A 10V IN OUT 10V 10V FIGURE 1. RDS FIGURE 2. IS(OFF) IN OUT ID(OFF) IS(OFF) A A IN OUT A A 10V 10V ID(ON) 10V FIGURE 3. ID(OFF) FIGURE 4. ID(ON) +VCC +ICC OUT IN VA +VCC IN OUT GND VA -ICC IA -VCC -VCC GND FIGURE 5. ADDRESS CURRENT 4 FIGURE 6. SUPPLY CURRENTS FN8289.0 May 3, 2012 HI-5051/883 Test Circuits (Continued) SWITCHED CHANNEL IN VIN OUT 50 2VP-P VOUT VIN 2VP-P RL 50 VOUT V IN CROSSTALK = 20 Log ---------------- V OUT V IN OFF ISOLATION = 20 Log ---------------- V OUT RL RL NOTE: Applies only to dual or double throw switches. FIGURE 7. OFF ISOLATION FIGURE 8. CROSSTALK D S 0.01MF DRIVER f = 200kHz SQUARE WAVE tR 20ns TO MEASUREMENT CIRCUITRY WITH INPUT RESISTANCE OF 1M OR GREATER IF PULSE TEST IS USED: tR, tF 20ns VIN (DRIVER) VCTE DROOP CAUSED BY DEVICE LEAKAGE AND MEASUREMENT CIRCUITRY SWITCHING TRANSIENT NOTE: VCTE may be a positive or negative value. FIGURE 9. CHARGE TRANSFER Test Characteristics VAH VA VAL 90% 90% IN1 OUT 1 tON +10V 90% IN2 1k VA tOFF 90% OUT 2 1k tOFF tON FIGURE 10. ON/OFF SWITCH TIME (tON, tOFF) 5 FN8289.0 May 3, 2012 HI-5051/883 Test Characteristics (Continued) 720 720 660 660 600 600 540 540 480 480 420 420 tON 360 300 360 tON 300 tOFF 240 240 180 180 120 120 tOFF 60 60 2.4 3.0 3.6 4.2 4.8 0 0.5 DIGITAL "HIGH" (VAH) 1.0 1.5 DIGITAL "LOW" (VAL) FIGURE 11. SWITCHING TIMES FOR DIGITAL TRANSITION FIGURE 12. SWITCHING TIMES FOR NEGATIVE DIGITAL TRANSITION Test Waveforms 5V 5V INPUT INPUT OUTPUT OUTPUT 5V 100ns Vertical Scale: Input = 5V/Div, (TTL; VAH = 5V, VAL = 0V) Output = 5V/Div Horizontal Scale: 100ns/Div FIGURE 13. 6 5V 100ns Vertical Scale: Input = 5V/Div, (CMOS; VAH = 10V, VAL = 0V) Output = 5V/Div Horizontal Scale: 100ns/Div FIGURE 14. FN8289.0 May 3, 2012 HI-5051/883 Burn-In Circuit HI-5051/883 CERAMIC LCC NOTES: R1 thru R4 = 10k, 5%, 1/4W (Min) C1, C2, C3 = 0.01F/Socket (Min) or 0.1F/Row, (Min) D1, D2, D3 = 1N4002 or Equivalent/Board VL = 5.5V 0.5V A2 = A2 = 5.5V 0.5V |(V+) - (V-)| = 30V 7 FN8289.0 May 3, 2012 HI-5051/883 Schematic Diagrams V+ R3 V+ VR A1 (A2) N1 TO (VR') V+ N3 IN OUT P2 N2 VP1 V- A1 (A2) NOTE: Connect V+ to VL for minimizing power consumption when driving from CMOS circuits. FIGURE 15. TTL/CMOS REFERENCE CIRCUIT FIGURE 16. SWITCH CELL V+ P3 P5 P1 V+ P4 N1 P6 D1 R4 P8 P7 P9 P10 P11 P12 A1 A1 VR' A 200 D2 A2 A2 VL' N6 V- N7 N8 N9 N10 N11 N12 P2 N4 N2 N5 N3 V- NOTE: All N-Channel bodies to V-, all P-Channel bodies to V+ except as shown. DIGITAL INPUT BUFFER AND LEVEL SHIFTER 8 FN8289.0 May 3, 2012 HI-5051/883 Die Characteristics GLASSIVATION: Type: Nitride over Silox Silox Thickness: 12kA 2kA Nitride Thickness: 3.5kA 1kA DIE DIMENSIONS: 96mils x 81mils x 20mils (2430m x 2050m x 508m) SUBSTRATE POTENTIAL (Powered-up): V- METALLIZATION: DEVICE COUNT: 82 Type: Aluminum Thickness: 16kA 2kA WORST CASE CURRENT DENSITY: 1.0 x 105A/cm2 at 20mA Metallization Mask Layout HI-5051/883 D1 S1 A1 D3 VS3 VR VL S4 D4 V+ 10 D2 9 S2 A2 FN8289.0 May 3, 2012 HI-5051/883 Design Information The information contained in this section has been developed through characterization and is for use as application and design information only. No guarantee is implied. Typical Performance Curves TA = +25C, VSUPPLY = 15V NORMALIZED ON RESISTANCE (REFERRED TO +25C) ON RESISTANCE () 80 60 V+ = +12V V- = -12V V+ = +10V V- = -10V 40 20 V+ = +15V V- = -15V 0 -15 0 -5 -10 5 10 1.2 1.1 VIN = 0V 1.0 0.9 0.8 0.7 0.6 15 -50 -25 0 ANALOG SIGNAL LEVEL (V) 50 75 100 125 FIGURE 18. NORMALIZED ON RESISTANCE vs TEMPERATURE 1.4 100nA 1.3 10nA LEAKAGE CURRENT NORMALIZED ON RESISTANCE (REFERRED TO 1mA) FIGURE 17. ON RESISTANCE vs ANALOG SIGNAL LEVEL AND POWER SUPPLY VOLTAGE 1.2 1.1 IS(OFF) = ID(OFF) 1nA ID(ON) 100pA 1.0 0 20 40 60 10pA 25 80 50 75 ANALOG CURRENT (mA) 100 125 TEMPERATURE (C) FIGURE 19. NORMALIZED ON RESISTANCE vs ANALOG CURRENT FIGURE 20. ON/OFF LEAKAGE CURRENTS vs TEMPERATURE 200 CROSSTALK (dB) -200 OFF ISOLATION (dB) 25 TEMPERATURE (C) -160 RL = 100 -120 -80 RL = 10k -40 1 10 100 1k 10k RL = 100 120 RL = 1k 80 RL = 10k 40 100k FREQUENCY (Hz) FIGURE 21. OFF ISOLATION vs FREQUENCY 10 160 1M 0 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 22. CROSSTALK vs FREQUENCY FN8289.0 May 3, 2012 HI-5051/883 Design Information The information contained in this section has been developed through characterization and is for use as application and design information only. No guarantee is implied. Typical Performance Curves TA = +25C, VSUPPLY = 15V (Continued) POWER CONSUMPTION (mW) 200 160 120 80 40 0 1k 10k 100k 1M TOGGLE FREQUENCY (50% DUTY CYCLE) (Hz) FIGURE 23. POWER CONSUMPTION vs FREQUENCY For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN8289.0 May 3, 2012 HI-5051/883 Ceramic Leadless Chip Carrier Packages (CLCC) J20.A MIL-STD-1835 CQCC1-N20 (C-2) 20 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE 0.010 S E H S D INCHES D3 j x 45o E3 B E h x 45o 0.010 S E F S A MIN MAX MIN MAX NOTES A 0.060 0.100 1.52 2.54 6, 7 A1 0.050 0.088 1.27 2.23 - B - - B1 0.022 0.028 B2 PLANE 1 -E- L -H- L3 - 0.006 0.022 0.15 0.56 - 0.358 8.69 9.09 - D1 0.200 BSC 5.08 BSC D2 0.100 BSC 2.54 BSC D3 - E 0.342 E3 e j e 1.83 REF 0.342 h B1 2, 4 D e1 0.007 M E F S H S 0.71 B3 0.358 0.358 8.69 0.200 BSC E2 PLANE 2 0.56 0.072 REF E1 A1 MILLIMETERS SYMBOL 2 9.09 - 2.54 BSC 0.358 - 0.050 BSC 0.015 - 9.09 5.08 BSC 0.100 BSC - - - 9.09 2 1.27 BSC - 0.38 0.040 REF 0.020 REF - 2 1.02 REF 5 0.51 REF 5 L 0.045 0.055 1.14 1.40 - L1 0.045 0.055 1.14 1.40 - L2 0.075 0.095 1.91 2.41 - L3 0.003 0.015 0.08 0.38 - ND 5 5 NE 5 5 3 3 N 20 20 3 Rev. 0 5/18/94 -F- NOTES: B3 E1 E2 L2 B2 L1 D2 e1 D1 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol "N" is the maximum number of terminals. Symbols "ND" and "NE" are the number of terminals along the sides of length "D" and "E", respectively. 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension "A" controls the overall package thickness. The maximum "A" dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Controlling dimension: INCH. 12 FN8289.0 May 3, 2012