1
Dual SPDT CMOS Analog Switch
HI-5051/883
This CMOS analog switch offers low resistance switching
performance for analog voltages up to the supply rails and for
signal currents up to 70mA. “ON” resistance is low and stays
reasonably constant over the full range of operating signal
voltage and current. RON remains exceptionally constant for
input voltages between +5V and -5V and currents up to 50mA.
Switch impedance also changes very little over temperature,
particularly between 0°C and +75°C. RON is nominally 25Ω.
The HI-5051/883 provides break-before-make switching and
is TTL and CMOS compatible for maximum application
versatility. Performance is further enhanced by Dielectric
Isolation processing which insures latch-free operation with
very low input and output leakage currents (0.8nA at +25°C).
The HI-5051/883 switch also features very low power
operation (1.5mW at +25°C). The HI-5051/883 is available in a
20 Ld CLCC package and operates over the -55°C to +125°C
temperature range.
Features
• This Circuit is Processed in Accordance to MIL-STD-883 and
is Fully Conformant Under the Provisions of Paragraph 1.2.1.
• Wide Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . ±15V
• Low “ON” Resistance. . . . . . . . . . . . . . . 25Ω (Typ), 50Ω (Max)
• High Current Capability . . . . . . . . . . . . . . . . . . . . . 70mA (Max)
• Break-Before-Make Switching
- Turn-On Time. . . . . . . . . . . . . . . . . 370ns (Typ), 800ns (Max)
- Turn-Off Time . . . . . . . . . . . . . . . 280ns (Typ), 400ns (Max)
•No Latch-Up
• Input MOS Gates are Protected from Electrostatic Discharge
• DTL, TTL, CMOS, PMOS Compatible
Applications
• High Frequency Switching
• Sample and Hold
• Digital Filters
• Operational Amplifier Gain Switching
Functional Diagram
LOGIC “1” INPUT
NOTE: Source and Drain are arbitrarily depicted as Analog Input and
Output, respectively. They may be interchanged without affecting
performance.
Pin Configuration
HI-5051/883
20 LD CLCC
TOP VIEW
LOGIC “0” INPUT
NOTE: Unused pins may be internally connected. Ground all unused pins.
Ordering Information
PART
NUMBER
PART
MARKING
TEMP. RANGE
(°C) PACKAGE
PKG.
DWG.
#
HI4-5051/883 HI4-5051 883 -55 to +125 20 Ld CLCC J20.A
V-
V+
S2
VL
VR
S3
NC
NC
NC NC A2
D2
D3
S4
D4
S1
NC NC A1
D1
32120 19
18
17
16
15
14
910 11 12 13
4
5
6
7
8
S
N
AP
D
1
3
8
6
5
9
10
12
15
4
16 11
13 14
D1
D2
D4
D3
S1
A1
A2
S4
S3
S2
V-VR
V+VL
TYPICAL SWITCH
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 1989, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
May 3, 2012
FN8289.0
HI-5051/883
2FN8289.0
May 3, 2012
Absolute Maximum Ratings Thermal Information
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
±VSUPPLY to Ground (V+, V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18V
VR to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY
VL to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY
Digital and Analog Input Voltage (VA, VS, VD) . . . . . . . . . . . . +VSUPPLY +4V
-VSUPPLY -4V
Peak Current (Source to Drain)
(Pulse at 1ms, 10% Duty Cycle Max) . . . . . . . . . . . . . . . . . . . . . . . . 70mA
Continuous Current (Any Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<2000V
Thermal Resistance θJA (°C/W) θJC (°C/W)
CLCC Package. . . . . . . . . . . . . . . . . . . . . . . . 8O 20
Package Power Dissipation at +75°C
CLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Package Power Dissipation Derating Factor above +75°C
CLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.5mW/°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . . . . . . . .+300°C
Recommended Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Operating Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±15V
Logic Supply Voltage (VL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.0V
Logic Reference Voltage (VR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.0V
Analog Input Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VSUPPLY
Address Low Level (VAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 0.8V
Address High Level (VAH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V to +5.0V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
TABLE 1. D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: Supply Voltage = ±15V, VL = +5.0V, VR = 0.0V, VAH = 2.4V, VAL = +0.8V, unused pins are grounded, unless otherwise specified.
D.C. PARAMETERS SYMBOL CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
(°C) MIN MAX UNITS
Switch “ON” Resistance RDS2 VD = -10V, IS = 10mA
S1/S2/S3/S4
1 +25 - 45 Ω
2, 3 -55 to +125 - 50 Ω
VD = 10V, IS = -10mA
S1/S2/S3/S4
1 +25 - 45 Ω
2, 3 -55 to +125 - 50 Ω
Source “OFF”
Leakage Current
IS(OFF) VS = -10V, VD = 10V
S1/S2/S3/S4
1 +25 -1 1 nA
2, 3 -55 to +125 -100 100 nA
VS = 10V, VD = -10V
S1/S2/S3/S4
1 +25 -1 1 nA
2, 3 -55 to +125 -100 100 nA
Drain “OFF”
Leakage Current
ID(OFF) VD = -10V, VS = 10V
S1/S2/S3/S4
1 +25 -1 1 nA
2, 3 -55 to +125 -100 100 nA
VD = 10V, VS = -10V
S1/S2/S3/S4
1 +25 -1 1 nA
2, 3 -55 to +125 -100 100 nA
Channel “ON”
Leakage Current
ID(ON) VD = VS = 10V
S1/S2/S3/S4
1 +25 -2 2 nA
2, 3 -55 to +125 -200 200 nA
VD = VS = -10V
S1/S2/S3/S4
1 +25 -2 2 nA
2, 3 -55 to +125 -200 200 nA
Low Level Address Current IAL VA = 0V
A1, A2
1 +25 -1 1 µA
2, 3 -55 to +125 -10 1 µA
High Level Address Current IAH VA = 2.4V, 5V
A1, A2
1 +25 -1 1 µA
2, 3 -55 to +125 -1 10 µA
Positive Supply Current +ICC VA = 0V, 5V
A1, A2
1 +25 - 200 µA
2, 3 -55 to +125 - 300 µA
Negative Supply Current -ICC VA = 0V, 5V
A1, A2
1 +25 -200 - µA
2, 3 -55 to +125 -300 - µA
HI-5051/883
3FN8289.0
May 3, 2012
Logic Supply Current +ILVA = 0V, 5V 1 +25 - 200 µA
2, 3 -55 to +125 - 300 µA
Reference Supply Current +IRVA = 0V, 5V 1 +25 -200 - µA
2, 3 -55 to +125 -300 - µA
TABLE 1. D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Tested at: Supply Voltage = ±15V, VL = +5.0V, VR = 0.0V, VAH = 2.4V, VAL = +0.8V, unused pins are grounded, unless otherwise specified.
D.C. PARAMETERS SYMBOL CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
(°C) MIN MAX UNITS
TABLE 2. A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: Supply Voltage = ±15V, VL = +5.0V, VR = 0.0V, VAH = +5.0V, VAL = +0.0V, unused pins are grounded, unless otherwise specified.
PARAMETERS SYMBOL CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
(°C) MIN MAX UNITS
Turn “ON” Time tON VS = 10V, -10V
CL = 10pF
RL = 1kΩ
11 -55 - 450 ns
9 +25 - 500 ns
10 +125 - 800 ns
Turn “OFF” Time tOFF VS = 10V, -10V
CL = 10pF
RL = 1kΩ
11 -55 - 350 ns
9 +25 - 450 ns
10 +125 - 600 ns
TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS (NOTE 1)
Device Characterized at: Supply Voltage = ±15V, VL = +5.0V, VR = 0.0V, VAH = 4.0V, VAL = 0.8V, unused pins are grounded, unless otherwise specified.
PARAMETERS SYMBOL CONDITIONS NOTE
TEMPERATURE
(°C) MIN MAX UNITS
“ON” Resistance Match
(Channel to Channel)
RON2 Match VD = ±10V
ID = 10mA
1 +25 - 10 Ω
Address Capacitance CAVA = 0V, 5V 1 +25 - 45 pF
Switch Input Capacitance CS(OFF) Switch Off: VA = 0V 1 +25 - 60 pF
Switch Output Capacitance CD(OFF) Switch Off: VA = 0V 1 +25 - 60 pF
CD(ON) Switch On: VA = 5V 1 +25 - 60 pF
Drain to Source Capacitance CDS(OFF) Switch Off: VA = 0V 1 +25 - 10 pF
Off Isolation VISO VS = 2VP-P @ f = 100kHz,
RL=100Ω
1 +25 - 60 dB
Crosstalk VCT VS = 2VP-P @ f = 100kHz,
RL=100Ω
1 +25 - 60 dB
Charge Transfer Error VCTE VS = GND, CL = 0.01µF
VA = 0V to 4V @ f = 200kHz
1 +25 - 30 mV
NOTE:
1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab
characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from
multiple production runs which reflect lot to lot and within lot variation.
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS SUBGROUPS (See Tables 1 and 2)
Interim Electrical Parameters (Pre Burn-in) 1
Final Electrical Test Parameters 1 (Note 2), 2, 3, 9, 10, 11
Group A Test Requirements 1, 2, 3, 9, 10, 11
Groups C & D Endpoints 1
NOTE:
2. PDA applies to Subgroup 1 only.
HI-5051/883
4FN8289.0
May 3, 2012
Test Circuits
FIGURE 1. RDS FIGURE 2. IS(OFF)
FIGURE 3. ID(OFF) FIGURE 4. ID(ON)
FIGURE 5. ADDRESS CURRENT FIGURE 6. SUPPLY CURRENTS
IN OUT
10mA
V2
RON = 10mA
V2
±10V
IN OUT AA
±10V
ID(OFF)
IS(OFF)
±1 0 V
IN OUT AA
±10V
ID(OFF)
IS(OFF)
±10V
IN OUT
A
±10V
ID(ON)
+VCC
OUT
-VCC
GND
IN
IA
VA
GND
+ICC
+VCC
OUT
IN
VA
-ICC
-VCC
HI-5051/883
5FN8289.0
May 3, 2012
FIGURE 7. OFF ISOLATION
NOTE: Applies only to dual or double throw switches.
FIGURE 8. CROSSTALK
NOTE: VCTE may be a positive or negative value.
FIGURE 9. CHARGE TRANSFER
Test Circuits (Continued)
50ΩRL
VOUT
VIN
2VP-P
IN OUT
OFF ISOLATION 20 Log VIN
VOUT
----------------
⎝⎠
⎜⎟
⎛⎞
=
50Ω
RL
RL
VOUT
VIN
2VP-P
SWITCHED
CHANNEL
CROSSTALK 20 Log VIN
VOUT
----------------
⎝⎠
⎜⎟
⎛⎞
=
DTO MEASUREMENT
SCIRCUITRY WITH INPUT
RESISTANCE OF 1MΩ
OR GREATER
0.01MF
DRIVER
f = 200kHz
SQUARE WAVE
tR ≤ 20ns
IF PULSE TEST IS USED:
tR, tF ≤ 20ns
VIN (DRIVER)
VCTE DROOP CAUSED BY
DEVICE LEAKAGE
AND MEASUREMENT
CIRCUITRY
SWITCHING TRANSIENT
Test Characteristics
FIGURE 10. ON/OFF SWITCH TIME (tON, tOFF)
90% 90%
tOFF
tON
tON tOFF
90%
90%
VA
OUT 1
OUT 2
VAH
+10V
IN1
IN2
VA
1k 1k
VAL
HI-5051/883
6FN8289.0
May 3, 2012
FIGURE 11. SWITCHING TIMES FOR DIGITAL TRANSITION FIGURE 12. SWITCHING TIMES FOR NEGATIVE DIGITAL TRANSITION
Test Characteristics (Continued)
DIGITAL “HIGH” (VAH)
2.4 3.0 3.6 4.2 4.8
720
660
600
540
480
420
360
300
240
180
120
60
tON
tOFF
DIGITAL “LOW” (VAL)
0 0.5 1.0 1.5
720
660
600
540
480
420
360
300
240
180
120
60
tON
tOFF
Test Waveforms
Vertical Scale: Input = 5V/Div, (TTL; VAH = 5V, VAL = 0V)
Output = 5V/Div
Horizontal Scale: 100ns/Div
FIGURE 13.
Vertical Scale: Input = 5V/Div, (CMOS; VAH = 10V, VAL = 0V)
Output = 5V/Div
Horizontal Scale: 100ns/Div
FIGURE 14.
5V
5V 100ns
INPUT
OUTPUT
5V
5V 100ns
INPUT
OUTPUT
HI-5051/883
7FN8289.0
May 3, 2012
Burn-In Circuit
HI-5051/88 3 CERAMIC LCC
NOTES:
R1 thru R4 = 10kΩ, ±5%, 1/4W (Min)
C1, C2, C3 = 0.01µF/Socket (Min) or 0.1µF/Row, (Min)
D1, D2, D3 = 1N4002 or Equivalent/Board
VL = 5.5V ±0.5V
A2 = A2 = 5.5V ±0.5V
|(V+) - (V-)| = 30V
HI-5051/883
8FN8289.0
May 3, 2012
Schematic Diagrams
NOTE: Connect V+ to VL for minimizing power consumption when
driving from CMOS circuits.
FIGURE 15. TTL/CMOS REFERENCE CIRCUIT FIGURE 16. SWITCH CELL
NOTE: All N-Channel bodies to V-, all P-Channel bodies to V+ except as shown.
DIGITAL INPUT BUFFER AND LEVEL SHIFTER
TO (VR’)
VR
V-
V+ V+ R3
P2 N2
N1
N3
V-
P1
IN OUT
V+
A1 (A2)
A1 (A2)
N1
N2
P2
P1
P3
P5
P4
P6 P7 P8 P9 P10 P11 P12
A1
A2
N12N11N10N9N8N7N6
N5
N4
N3
V-
VL'
VR'
V+
V+
D2
D1
V-
A
R4
200Ω
A1
A2
HI-5051/883
9FN8289.0
May 3, 2012
Die Characteristics
DIE DIMENSIONS:
96mils x 81mils x 20mils
(2430µm x 2050µm x 508µm)
METALLIZATION:
Type: Aluminum
Thickness: 16kÅ ±2kÅ
GLASSIVATION:
Type: Nitride over Silox
Silox Thickness: 12kÅ ±2kÅ
Nitride Thickness: 3.5kÅ ±1kÅ
SUBSTRATE POTENTIAL (Powered-up): V-
DEVICE COUNT: 82
WORST CASE CURRENT DENSITY:
1.0 x 105A/cm2 at 20mA
Metallization Mask Layout
HI-5051/883
V-
VR
VL
V+
D3
S3
S4
D4
D1S1A1
S2
D2A2
10
HI-5051/883
10 FN8289.0
May 3, 2012
Design Information The information contained in this section has been developed through characterization and is for use as
application and design information only. No guarantee is implied.
Typical Performance Curves TA = +25°C, VSUPPLY = ±15V
FIGURE 17. ON RESISTANCE vs ANALOG SIGNAL LEVEL AND POWER
SUPPLY VOLTAGE
FIGURE 18. NORMALIZED ON RESISTANCE vs TEMPERATURE
FIGURE 19. NORMALIZED ON RESISTANCE vs ANALOG CURRENT FIGURE 20. ON/OFF LEAKAGE CURRENTS vs TEMPERATURE
FIGURE 21. OFF ISOLATION vs FREQUENCY FIGURE 22. CROSSTALK vs FREQUENCY
ANALOG SIGNAL LEVEL (V)
ON RESISTANCE (Ω)
80
60
40
20
0
-15 -10 -5 051015
V+ = +10V
V- = -10V
V+ = +12V
V- = -12V
V+ = +15V
V- = -15V
TEMPERATURE (°C)
-50 -25 0 75 100 1255025
0.6
1.2
1.1
1.0
0.9
0.8
0.7
NORMALIZED ON RESISTANCE
(REFERRED TO +25°C)
VIN = 0V
ANALOG CURRENT (mA)
40 60 80200
1.4
NORMALIZED ON RESISTANCE
1.3
1.2
1.1
1.0
(REFERRED TO 1mA)
ID(ON)
TEMPERATURE (°C)
75 100 1255025
IS(OFF) = ID(OFF)
100nA
10nA
1nA
100pA
10pA
LEAKAGE CURRENT
FREQUENCY (Hz)
10k 100k 1M1001
-200
OFF ISOLATION (dB)
-160
-120
-80
-40
1k10
RL = 100Ω
RL = 10kΩ
FREQUENCY (Hz)
200
160
120
80
40
10k 100k 1M10011k10
0
CROSSTALK (dB)
RL = 100Ω
RL = 10kΩ
RL = 1kΩ
HI-5051/883
11
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8289.0
May 3, 2012
For additional products, see www.intersil.com/product_tree
FIGURE 23. POWER CONSUMPTION vs FREQUENCY
Design Information The information contained in this section has been developed through characterization and is for use as
application and design information only. No guarantee is implied.
Typical Performance Curves TA = +25°C, VSUPPLY = ±15V (Continued)
TOGGLE FREQUENCY (50% DUTY CYCLE) (Hz)
200
160
120
80
40
10k 100k 1M1k
0
POWER CONSUMPTION (mW)
HI-5051/883
12 FN8289.0
May 3, 2012
Ceramic Leadless Chip Carrier Packages (CLCC)
D
j x 45oD3
B
h x 45o
AA1
E
LL3
e
B3
L1
D2
D1
e1
E2
E1
L2
PLANE 2
PLANE 1
E3
B2
0.010 E HS S
0.010 E F
SS
-E-
0.007 E FM S HS
B1
-H-
-F-
J20.A MIL-STD-1835 CQCC1-N20 (C-2)
20 PAD CERAMIC LEADLESS CHIP CARRIER PACKA GE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.060 0.100 1.52 2.54 6, 7
A1 0.050 0.088 1.27 2.23 -
B-----
B1 0.022 0.028 0.56 0.71 2, 4
B2 0.072 REF 1.83 REF -
B3 0.006 0.022 0.15 0.56 -
D 0.342 0.358 8.69 9.09 -
D1 0.200 BSC 5.08 BSC -
D2 0.100 BSC 2.54 BSC -
D3 -0.358-9.09 2
E 0.342 0.358 8.69 9.09 -
E1 0.200 BSC 5.08 BSC -
E2 0.100 BSC 2.54 BSC -
E3 -0.358-9.09 2
e 0.050 BSC 1.27 BSC -
e1 0.015 - 0.38 - 2
h 0.040 REF 1.02 REF 5
j 0.020 REF 0.51 REF 5
L 0.045 0.055 1.14 1.40 -
L1 0.045 0.055 1.14 1.40 -
L2 0.075 0.095 1.91 2.41 -
L3 0.003 0.015 0.08 0.38 -
ND 5 5 3
NE 5 5 3
N20 203
Rev. 0 5/18/94
NOTES:
1. Metallized castellations shall be connected to plane 1 terminals and ex-
tend toward plane 2 across at least two layers of ceramic or completely
across all of the ceramic layers to make electrical connection with the
optional plane 2 terminals.
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.38mm) shall be maintained between all metallized features (e.g., lid,
castellations, terminals, thermal pads, etc.)
3. Symbol “N” is the maximum number of terminals. Symbols “ND” an d
“NE” are the number of terminals along the sides of length “D” and
“E”, respectively.
4. The required plane 1 terminals and optional plane 2 terminals (i f used)
shall be electrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the manufac-
turer’s option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic layers.
7. Dimension “A” controls the overall package thickness. The maximum
“A” dimension is package height before being solder dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
